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[linux-2.6-block.git] / arch / ppc / 8xx_io / fec.c
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1da177e4
LT		 1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
10 *
11 * Includes support for the following PHYs: QS6612, LXT970, LXT971/2.
12 *
13 * Right now, I am very wasteful with the buffers. I allocate memory
14 * pages and then divide them into 2K frame buffers. This way I know I
15 * have buffers large enough to hold one frame within one buffer descriptor.
16 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
17 * will be much more memory efficient and will easily handle lots of
18 * small packets.
19 *
20 * Much better multiple PHY support by Magnus Damm.
21 * Copyright (c) 2000 Ericsson Radio Systems AB.
22 *
23 * Make use of MII for PHY control configurable.
24 * Some fixes.
25 * Copyright (c) 2000-2002 Wolfgang Denk, DENX Software Engineering.
26 *
27 * Support for AMD AM79C874 added.
28 * Thomas Lange, thomas@corelatus.com
29 */
30
1da177e4
LT		 31#include <linux/kernel.h>
32#include <linux/sched.h>
33#include <linux/string.h>
34#include <linux/ptrace.h>
35#include <linux/errno.h>
36#include <linux/ioport.h>
37#include <linux/slab.h>
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/init.h>
41#include <linux/delay.h>
42#include <linux/netdevice.h>
43#include <linux/etherdevice.h>
44#include <linux/skbuff.h>
45#include <linux/spinlock.h>
46#include <linux/bitops.h>
47#ifdef CONFIG_FEC_PACKETHOOK
48#include <linux/pkthook.h>
49#endif
50
51#include <asm/8xx_immap.h>
52#include <asm/pgtable.h>
53#include <asm/mpc8xx.h>
54#include <asm/irq.h>
55#include <asm/uaccess.h>
56#include <asm/commproc.h>
57
58#ifdef CONFIG_USE_MDIO
59/* Forward declarations of some structures to support different PHYs
60*/
61
62typedef struct {
63 uint mii_data;
64 void (*funct)(uint mii_reg, struct net_device *dev);
65} phy_cmd_t;
66
67typedef struct {
68 uint id;
69 char *name;
70
71 const phy_cmd_t *config;
72 const phy_cmd_t *startup;
73 const phy_cmd_t *ack_int;
74 const phy_cmd_t *shutdown;
75} phy_info_t;
76#endif /* CONFIG_USE_MDIO */
77
78/* The number of Tx and Rx buffers. These are allocated from the page
79 * pool. The code may assume these are power of two, so it is best
80 * to keep them that size.
81 * We don't need to allocate pages for the transmitter. We just use
82 * the skbuffer directly.
83 */
84#ifdef CONFIG_ENET_BIG_BUFFERS
85#define FEC_ENET_RX_PAGES 16
86#define FEC_ENET_RX_FRSIZE 2048
87#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
88#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
89#define TX_RING_SIZE 16 /* Must be power of two */
90#define TX_RING_MOD_MASK 15 /* for this to work */
91#else
92#define FEC_ENET_RX_PAGES 4
93#define FEC_ENET_RX_FRSIZE 2048
94#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
95#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
96#define TX_RING_SIZE 8 /* Must be power of two */
97#define TX_RING_MOD_MASK 7 /* for this to work */
98#endif
99
100/* Interrupt events/masks.
101*/
102#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
103#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
104#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
105#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
106#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
107#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
108#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
109#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
110#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
111#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
112
113/*
114*/
115#define FEC_ECNTRL_PINMUX 0x00000004
116#define FEC_ECNTRL_ETHER_EN 0x00000002
117#define FEC_ECNTRL_RESET 0x00000001
118
119#define FEC_RCNTRL_BC_REJ 0x00000010
120#define FEC_RCNTRL_PROM 0x00000008
121#define FEC_RCNTRL_MII_MODE 0x00000004
122#define FEC_RCNTRL_DRT 0x00000002
123#define FEC_RCNTRL_LOOP 0x00000001
124
125#define FEC_TCNTRL_FDEN 0x00000004
126#define FEC_TCNTRL_HBC 0x00000002
127#define FEC_TCNTRL_GTS 0x00000001
128
129/* Delay to wait for FEC reset command to complete (in us)
130*/
131#define FEC_RESET_DELAY 50
132
133/* The FEC stores dest/src/type, data, and checksum for receive packets.
134 */
135#define PKT_MAXBUF_SIZE 1518
136#define PKT_MINBUF_SIZE 64
137#define PKT_MAXBLR_SIZE 1520
138
139/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
140 * tx_bd_base always point to the base of the buffer descriptors. The
141 * cur_rx and cur_tx point to the currently available buffer.
142 * The dirty_tx tracks the current buffer that is being sent by the
143 * controller. The cur_tx and dirty_tx are equal under both completely
144 * empty and completely full conditions. The empty/ready indicator in
145 * the buffer descriptor determines the actual condition.
146 */
147struct fec_enet_private {
148 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
149 struct sk_buff* tx_skbuff[TX_RING_SIZE];
150 ushort skb_cur;
151 ushort skb_dirty;
152
153 /* CPM dual port RAM relative addresses.
154 */
155 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
156 cbd_t *tx_bd_base;
157 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
158 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
159
160 /* Virtual addresses for the receive buffers because we can't
161 * do a __va() on them anymore.
162 */
163 unsigned char *rx_vaddr[RX_RING_SIZE];
164
165 struct net_device_stats stats;
166 uint tx_full;
167 spinlock_t lock;
168
169#ifdef CONFIG_USE_MDIO
170 uint phy_id;
171 uint phy_id_done;
172 uint phy_status;
173 uint phy_speed;
174 phy_info_t *phy;
8b0ed2fb 175 struct work_struct phy_task;
6d5aefb8 176 struct net_device *dev;
1da177e4
LT		 177
178 uint sequence_done;
179
180 uint phy_addr;
181#endif /* CONFIG_USE_MDIO */
182
183 int link;
184 int old_link;
185 int full_duplex;
186
187#ifdef CONFIG_FEC_PACKETHOOK
188 unsigned long ph_lock;
189 fec_ph_func *ph_rxhandler;
190 fec_ph_func *ph_txhandler;
191 __u16 ph_proto;
192 volatile __u32 *ph_regaddr;
193 void *ph_priv;
194#endif
195};
196
197static int fec_enet_open(struct net_device *dev);
198static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
199#ifdef CONFIG_USE_MDIO
200static void fec_enet_mii(struct net_device *dev);
201#endif /* CONFIG_USE_MDIO */
39e3eb72 202static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
1da177e4
LT		 203#ifdef CONFIG_FEC_PACKETHOOK
204static void fec_enet_tx(struct net_device *dev, __u32 regval);
205static void fec_enet_rx(struct net_device *dev, __u32 regval);
206#else
207static void fec_enet_tx(struct net_device *dev);
208static void fec_enet_rx(struct net_device *dev);
209#endif
210static int fec_enet_close(struct net_device *dev);
211static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
212static void set_multicast_list(struct net_device *dev);
213static void fec_restart(struct net_device *dev, int duplex);
214static void fec_stop(struct net_device *dev);
215static ushort my_enet_addr[3];
216
217#ifdef CONFIG_USE_MDIO
218/* MII processing. We keep this as simple as possible. Requests are
219 * placed on the list (if there is room). When the request is finished
220 * by the MII, an optional function may be called.
221 */
222typedef struct mii_list {
223 uint mii_regval;
224 void (*mii_func)(uint val, struct net_device *dev);
225 struct mii_list *mii_next;
226} mii_list_t;
227
228#define NMII 20
229mii_list_t mii_cmds[NMII];
230mii_list_t *mii_free;
231mii_list_t *mii_head;
232mii_list_t *mii_tail;
233
234static int mii_queue(struct net_device *dev, int request,
235 void (*func)(uint, struct net_device *));
236
237/* Make MII read/write commands for the FEC.
238*/
239#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
240#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
241 (VAL & 0xffff))
242#define mk_mii_end 0
243#endif /* CONFIG_USE_MDIO */
244
245/* Transmitter timeout.
246*/
247#define TX_TIMEOUT (2*HZ)
248
249#ifdef CONFIG_USE_MDIO
250/* Register definitions for the PHY.
251*/
252
253#define MII_REG_CR 0 /* Control Register */
254#define MII_REG_SR 1 /* Status Register */
255#define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
256#define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
257#define MII_REG_ANAR 4 /* A-N Advertisement Register */
258#define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
259#define MII_REG_ANER 6 /* A-N Expansion Register */
260#define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
261#define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
262
263/* values for phy_status */
264
265#define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
266#define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
267#define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
268#define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
269#define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
270#define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
271#define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
272
273#define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
274#define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
275#define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
276#define PHY_STAT_SPMASK 0xf000 /* mask for speed */
277#define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
278#define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
279#define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
280#define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
281#endif /* CONFIG_USE_MDIO */
282
283#ifdef CONFIG_FEC_PACKETHOOK
284int
285fec_register_ph(struct net_device *dev, fec_ph_func *rxfun, fec_ph_func *txfun,
286 __u16 proto, volatile __u32 *regaddr, void *priv)
287{
288 struct fec_enet_private *fep;
289 int retval = 0;
290
291 fep = dev->priv;
292
293 if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) {
294 /* Someone is messing with the packet hook */
295 return -EAGAIN;
296 }
297 if (fep->ph_rxhandler != NULL || fep->ph_txhandler != NULL) {
298 retval = -EBUSY;
299 goto out;
300 }
301 fep->ph_rxhandler = rxfun;
302 fep->ph_txhandler = txfun;
303 fep->ph_proto = proto;
304 fep->ph_regaddr = regaddr;
305 fep->ph_priv = priv;
306
307 out:
308 fep->ph_lock = 0;
309
310 return retval;
311}
312
313
314int
315fec_unregister_ph(struct net_device *dev)
316{
317 struct fec_enet_private *fep;
318 int retval = 0;
319
320 fep = dev->priv;
321
322 if (test_and_set_bit(0, (void*)&fep->ph_lock) != 0) {
323 /* Someone is messing with the packet hook */
324 return -EAGAIN;
325 }
326
327 fep->ph_rxhandler = fep->ph_txhandler = NULL;
328 fep->ph_proto = 0;
329 fep->ph_regaddr = NULL;
330 fep->ph_priv = NULL;
331
332 fep->ph_lock = 0;
333
334 return retval;
335}
336
337EXPORT_SYMBOL(fec_register_ph);
338EXPORT_SYMBOL(fec_unregister_ph);
339
340#endif /* CONFIG_FEC_PACKETHOOK */
341
342static int
343fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
344{
345 struct fec_enet_private *fep;
346 volatile fec_t *fecp;
347 volatile cbd_t *bdp;
348
349 fep = dev->priv;
350 fecp = (volatile fec_t*)dev->base_addr;
351
352 if (!fep->link) {
353 /* Link is down or autonegotiation is in progress. */
354 return 1;
355 }
356
357 /* Fill in a Tx ring entry */
358 bdp = fep->cur_tx;
359
360#ifndef final_version
361 if (bdp->cbd_sc & BD_ENET_TX_READY) {
362 /* Ooops. All transmit buffers are full. Bail out.
363 * This should not happen, since dev->tbusy should be set.
364 */
365 printk("%s: tx queue full!.\n", dev->name);
366 return 1;
367 }
368#endif
369
370 /* Clear all of the status flags.
371 */
372 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
373
374 /* Set buffer length and buffer pointer.
375 */
376 bdp->cbd_bufaddr = __pa(skb->data);
377 bdp->cbd_datlen = skb->len;
378
379 /* Save skb pointer.
380 */
381 fep->tx_skbuff[fep->skb_cur] = skb;
382
383 fep->stats.tx_bytes += skb->len;
384 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
385
386 /* Push the data cache so the CPM does not get stale memory
387 * data.
388 */
389 flush_dcache_range((unsigned long)skb->data,
390 (unsigned long)skb->data + skb->len);
391
392 /* disable interrupts while triggering transmit */
393 spin_lock_irq(&fep->lock);
394
395 /* Send it on its way. Tell FEC its ready, interrupt when done,
396 * its the last BD of the frame, and to put the CRC on the end.
397 */
398
399 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
400 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
401
402 dev->trans_start = jiffies;
403
404 /* Trigger transmission start */
405 fecp->fec_x_des_active = 0x01000000;
406
407 /* If this was the last BD in the ring, start at the beginning again.
408 */
409 if (bdp->cbd_sc & BD_ENET_TX_WRAP) {
410 bdp = fep->tx_bd_base;
411 } else {
412 bdp++;
413 }
414
415 if (bdp->cbd_sc & BD_ENET_TX_READY) {
416 netif_stop_queue(dev);
417 fep->tx_full = 1;
418 }
419
420 fep->cur_tx = (cbd_t *)bdp;
421
422 spin_unlock_irq(&fep->lock);
423
424 return 0;
425}
426
427static void
428fec_timeout(struct net_device *dev)
429{
430 struct fec_enet_private *fep = dev->priv;
431
432 printk("%s: transmit timed out.\n", dev->name);
433 fep->stats.tx_errors++;
434#ifndef final_version
435 {
436 int i;
437 cbd_t *bdp;
438
439 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
440 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
441 (unsigned long)fep->dirty_tx,
442 (unsigned long)fep->cur_rx);
443
444 bdp = fep->tx_bd_base;
445 printk(" tx: %u buffers\n", TX_RING_SIZE);
446 for (i = 0 ; i < TX_RING_SIZE; i++) {
447 printk(" %08x: %04x %04x %08x\n",
448 (uint) bdp,
449 bdp->cbd_sc,
450 bdp->cbd_datlen,
451 bdp->cbd_bufaddr);
452 bdp++;
453 }
454
455 bdp = fep->rx_bd_base;
456 printk(" rx: %lu buffers\n", RX_RING_SIZE);
457 for (i = 0 ; i < RX_RING_SIZE; i++) {
458 printk(" %08x: %04x %04x %08x\n",
459 (uint) bdp,
460 bdp->cbd_sc,
461 bdp->cbd_datlen,
462 bdp->cbd_bufaddr);
463 bdp++;
464 }
465 }
466#endif
467 if (!fep->tx_full)
468 netif_wake_queue(dev);
469}
470
471/* The interrupt handler.
472 * This is called from the MPC core interrupt.
473 */
fbccb3d7 474static irqreturn_t
39e3eb72 475fec_enet_interrupt(int irq, void * dev_id)
1da177e4
LT		 476{
477 struct net_device *dev = dev_id;
478 volatile fec_t *fecp;
479 uint int_events;
480#ifdef CONFIG_FEC_PACKETHOOK
481 struct fec_enet_private *fep = dev->priv;
482 __u32 regval;
483
484 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
485#endif
486 fecp = (volatile fec_t*)dev->base_addr;
487
488 /* Get the interrupt events that caused us to be here.
489 */
490 while ((int_events = fecp->fec_ievent) != 0) {
491 fecp->fec_ievent = int_events;
492 if ((int_events & (FEC_ENET_HBERR | FEC_ENET_BABR |
493 FEC_ENET_BABT | FEC_ENET_EBERR)) != 0) {
494 printk("FEC ERROR %x\n", int_events);
495 }
496
497 /* Handle receive event in its own function.
498 */
499 if (int_events & FEC_ENET_RXF) {
500#ifdef CONFIG_FEC_PACKETHOOK
501 fec_enet_rx(dev, regval);
502#else
503 fec_enet_rx(dev);
504#endif
505 }
506
507 /* Transmit OK, or non-fatal error. Update the buffer
508 descriptors. FEC handles all errors, we just discover
509 them as part of the transmit process.
510 */
511 if (int_events & FEC_ENET_TXF) {
512#ifdef CONFIG_FEC_PACKETHOOK
513 fec_enet_tx(dev, regval);
514#else
515 fec_enet_tx(dev);
516#endif
517 }
518
519 if (int_events & FEC_ENET_MII) {
520#ifdef CONFIG_USE_MDIO
521 fec_enet_mii(dev);
522#else
523printk("%s[%d] %s: unexpected FEC_ENET_MII event\n", __FILE__,__LINE__,__FUNCTION__);
524#endif /* CONFIG_USE_MDIO */
525 }
526
527 }
fbccb3d7 528 return IRQ_RETVAL(IRQ_HANDLED);
1da177e4
LT		 529}
530
531
532static void
533#ifdef CONFIG_FEC_PACKETHOOK
534fec_enet_tx(struct net_device *dev, __u32 regval)
535#else
536fec_enet_tx(struct net_device *dev)
537#endif
538{
539 struct fec_enet_private *fep;
540 volatile cbd_t *bdp;
541 struct sk_buff *skb;
542
543 fep = dev->priv;
544 /* lock while transmitting */
545 spin_lock(&fep->lock);
546 bdp = fep->dirty_tx;
547
548 while ((bdp->cbd_sc&BD_ENET_TX_READY) == 0) {
549 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
550
551 skb = fep->tx_skbuff[fep->skb_dirty];
552 /* Check for errors. */
553 if (bdp->cbd_sc & (BD_ENET_TX_HB | BD_ENET_TX_LC |
554 BD_ENET_TX_RL | BD_ENET_TX_UN |
555 BD_ENET_TX_CSL)) {
556 fep->stats.tx_errors++;
557 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
558 fep->stats.tx_heartbeat_errors++;
559 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
560 fep->stats.tx_window_errors++;
561 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
562 fep->stats.tx_aborted_errors++;
563 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
564 fep->stats.tx_fifo_errors++;
565 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
566 fep->stats.tx_carrier_errors++;
567 } else {
568#ifdef CONFIG_FEC_PACKETHOOK
569 /* Packet hook ... */
570 if (fep->ph_txhandler &&
571 ((struct ethhdr *)skb->data)->h_proto
572 == fep->ph_proto) {
573 fep->ph_txhandler((__u8*)skb->data, skb->len,
574 regval, fep->ph_priv);
575 }
576#endif
577 fep->stats.tx_packets++;
578 }
579
580#ifndef final_version
581 if (bdp->cbd_sc & BD_ENET_TX_READY)
582 printk("HEY! Enet xmit interrupt and TX_READY.\n");
583#endif
584 /* Deferred means some collisions occurred during transmit,
585 * but we eventually sent the packet OK.
586 */
587 if (bdp->cbd_sc & BD_ENET_TX_DEF)
588 fep->stats.collisions++;
589
590 /* Free the sk buffer associated with this last transmit.
591 */
592#if 0
593printk("TXI: %x %x %x\n", bdp, skb, fep->skb_dirty);
594#endif
595 dev_kfree_skb_irq (skb/*, FREE_WRITE*/);
596 fep->tx_skbuff[fep->skb_dirty] = NULL;
597 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
598
599 /* Update pointer to next buffer descriptor to be transmitted.
600 */
601 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
602 bdp = fep->tx_bd_base;
603 else
604 bdp++;
605
606 /* Since we have freed up a buffer, the ring is no longer
607 * full.
608 */
609 if (fep->tx_full) {
610 fep->tx_full = 0;
611 if (netif_queue_stopped(dev))
612 netif_wake_queue(dev);
613 }
614#ifdef CONFIG_FEC_PACKETHOOK
615 /* Re-read register. Not exactly guaranteed to be correct,
616 but... */
617 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
618#endif
619 }
620 fep->dirty_tx = (cbd_t *)bdp;
621 spin_unlock(&fep->lock);
622}
623
624
625/* During a receive, the cur_rx points to the current incoming buffer.
626 * When we update through the ring, if the next incoming buffer has
627 * not been given to the system, we just set the empty indicator,
628 * effectively tossing the packet.
629 */
630static void
631#ifdef CONFIG_FEC_PACKETHOOK
632fec_enet_rx(struct net_device *dev, __u32 regval)
633#else
634fec_enet_rx(struct net_device *dev)
635#endif
636{
637 struct fec_enet_private *fep;
638 volatile fec_t *fecp;
639 volatile cbd_t *bdp;
640 struct sk_buff *skb;
641 ushort pkt_len;
642 __u8 *data;
643
644 fep = dev->priv;
645 fecp = (volatile fec_t*)dev->base_addr;
646
647 /* First, grab all of the stats for the incoming packet.
648 * These get messed up if we get called due to a busy condition.
649 */
650 bdp = fep->cur_rx;
651
652while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) {
653
654#ifndef final_version
655 /* Since we have allocated space to hold a complete frame,
656 * the last indicator should be set.
657 */
658 if ((bdp->cbd_sc & BD_ENET_RX_LAST) == 0)
659 printk("FEC ENET: rcv is not +last\n");
660#endif
661
662 /* Check for errors. */
663 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
664 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
665 fep->stats.rx_errors++;
666 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
667 /* Frame too long or too short. */
668 fep->stats.rx_length_errors++;
669 }
670 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
671 fep->stats.rx_frame_errors++;
672 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
673 fep->stats.rx_crc_errors++;
674 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
675 fep->stats.rx_crc_errors++;
676 }
677
678 /* Report late collisions as a frame error.
679 * On this error, the BD is closed, but we don't know what we
680 * have in the buffer. So, just drop this frame on the floor.
681 */
682 if (bdp->cbd_sc & BD_ENET_RX_CL) {
683 fep->stats.rx_errors++;
684 fep->stats.rx_frame_errors++;
685 goto rx_processing_done;
686 }
687
688 /* Process the incoming frame.
689 */
690 fep->stats.rx_packets++;
691 pkt_len = bdp->cbd_datlen;
692 fep->stats.rx_bytes += pkt_len;
693 data = fep->rx_vaddr[bdp - fep->rx_bd_base];
694
695#ifdef CONFIG_FEC_PACKETHOOK
696 /* Packet hook ... */
697 if (fep->ph_rxhandler) {
698 if (((struct ethhdr *)data)->h_proto == fep->ph_proto) {
699 switch (fep->ph_rxhandler(data, pkt_len, regval,
700 fep->ph_priv)) {
701 case 1:
702 goto rx_processing_done;
703 break;
704 case 0:
705 break;
706 default:
707 fep->stats.rx_errors++;
708 goto rx_processing_done;
709 }
710 }
711 }
712
713 /* If it wasn't filtered - copy it to an sk buffer. */
714#endif
715
716 /* This does 16 byte alignment, exactly what we need.
717 * The packet length includes FCS, but we don't want to
718 * include that when passing upstream as it messes up
719 * bridging applications.
720 */
721 skb = dev_alloc_skb(pkt_len-4);
722
723 if (skb == NULL) {
724 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
725 fep->stats.rx_dropped++;
726 } else {
1da177e4 727 skb_put(skb,pkt_len-4); /* Make room */
8c7b7faa 728 skb_copy_to_linear_data(skb, data, pkt_len-4);
1da177e4
LT		 729 skb->protocol=eth_type_trans(skb,dev);
730 netif_rx(skb);
731 }
732 rx_processing_done:
733
734 /* Clear the status flags for this buffer.
735 */
736 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
737
738 /* Mark the buffer empty.
739 */
740 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
741
742 /* Update BD pointer to next entry.
743 */
744 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
745 bdp = fep->rx_bd_base;
746 else
747 bdp++;
748
749#if 1
750 /* Doing this here will keep the FEC running while we process
751 * incoming frames. On a heavily loaded network, we should be
752 * able to keep up at the expense of system resources.
753 */
754 fecp->fec_r_des_active = 0x01000000;
755#endif
756#ifdef CONFIG_FEC_PACKETHOOK
757 /* Re-read register. Not exactly guaranteed to be correct,
758 but... */
759 if (fep->ph_regaddr) regval = *fep->ph_regaddr;
760#endif
761 } /* while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) */
762 fep->cur_rx = (cbd_t *)bdp;
763
764#if 0
765 /* Doing this here will allow us to process all frames in the
766 * ring before the FEC is allowed to put more there. On a heavily
767 * loaded network, some frames may be lost. Unfortunately, this
768 * increases the interrupt overhead since we can potentially work
769 * our way back to the interrupt return only to come right back
770 * here.
771 */
772 fecp->fec_r_des_active = 0x01000000;
773#endif
774}
775
776
777#ifdef CONFIG_USE_MDIO
778static void
779fec_enet_mii(struct net_device *dev)
780{
781 struct fec_enet_private *fep;
782 volatile fec_t *ep;
783 mii_list_t *mip;
784 uint mii_reg;
785
786 fep = (struct fec_enet_private *)dev->priv;
787 ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec);
788 mii_reg = ep->fec_mii_data;
789
790 if ((mip = mii_head) == NULL) {
791 printk("MII and no head!\n");
792 return;
793 }
794
795 if (mip->mii_func != NULL)
796 (*(mip->mii_func))(mii_reg, dev);
797
798 mii_head = mip->mii_next;
799 mip->mii_next = mii_free;
800 mii_free = mip;
801
802 if ((mip = mii_head) != NULL) {
803 ep->fec_mii_data = mip->mii_regval;
804
805 }
806}
807
808static int
809mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
810{
811 struct fec_enet_private *fep;
812 unsigned long flags;
813 mii_list_t *mip;
814 int retval;
815
816 /* Add PHY address to register command.
817 */
818 fep = dev->priv;
819 regval |= fep->phy_addr << 23;
820
821 retval = 0;
822
823 /* lock while modifying mii_list */
824 spin_lock_irqsave(&fep->lock, flags);
825
826 if ((mip = mii_free) != NULL) {
827 mii_free = mip->mii_next;
828 mip->mii_regval = regval;
829 mip->mii_func = func;
830 mip->mii_next = NULL;
831 if (mii_head) {
832 mii_tail->mii_next = mip;
833 mii_tail = mip;
834 } else {
835 mii_head = mii_tail = mip;
836 (&(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec))->fec_mii_data = regval;
837 }
838 } else {
839 retval = 1;
840 }
841
842 spin_unlock_irqrestore(&fep->lock, flags);
843
844 return(retval);
845}
846
847static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
848{
849 int k;
850
851 if(!c)
852 return;
853
854 for(k = 0; (c+k)->mii_data != mk_mii_end; k++)
855 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
856}
857
858static void mii_parse_sr(uint mii_reg, struct net_device *dev)
859{
860 struct fec_enet_private *fep = dev->priv;
861 volatile uint *s = &(fep->phy_status);
862
863 *s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
864
865 if (mii_reg & 0x0004)
866 *s |= PHY_STAT_LINK;
867 if (mii_reg & 0x0010)
868 *s |= PHY_STAT_FAULT;
869 if (mii_reg & 0x0020)
870 *s |= PHY_STAT_ANC;
871
872 fep->link = (*s & PHY_STAT_LINK) ? 1 : 0;
873}
874
875static void mii_parse_cr(uint mii_reg, struct net_device *dev)
876{
877 struct fec_enet_private *fep = dev->priv;
878 volatile uint *s = &(fep->phy_status);
879
880 *s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP);
881
882 if (mii_reg & 0x1000)
883 *s |= PHY_CONF_ANE;
884 if (mii_reg & 0x4000)
885 *s |= PHY_CONF_LOOP;
886}
887
888static void mii_parse_anar(uint mii_reg, struct net_device *dev)
889{
890 struct fec_enet_private *fep = dev->priv;
891 volatile uint *s = &(fep->phy_status);
892
893 *s &= ~(PHY_CONF_SPMASK);
894
895 if (mii_reg & 0x0020)
896 *s |= PHY_CONF_10HDX;
897 if (mii_reg & 0x0040)
898 *s |= PHY_CONF_10FDX;
899 if (mii_reg & 0x0080)
900 *s |= PHY_CONF_100HDX;
901 if (mii_reg & 0x00100)
902 *s |= PHY_CONF_100FDX;
903}
904#if 0
905static void mii_disp_reg(uint mii_reg, struct net_device *dev)
906{
907 printk("reg %u = 0x%04x\n", (mii_reg >> 18) & 0x1f, mii_reg & 0xffff);
908}
909#endif
910
911/* ------------------------------------------------------------------------- */
912/* The Level one LXT970 is used by many boards */
913
914#ifdef CONFIG_FEC_LXT970
915
916#define MII_LXT970_MIRROR 16 /* Mirror register */
917#define MII_LXT970_IER 17 /* Interrupt Enable Register */
918#define MII_LXT970_ISR 18 /* Interrupt Status Register */
919#define MII_LXT970_CONFIG 19 /* Configuration Register */
920#define MII_LXT970_CSR 20 /* Chip Status Register */
921
922static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
923{
924 struct fec_enet_private *fep = dev->priv;
925 volatile uint *s = &(fep->phy_status);
926
927 *s &= ~(PHY_STAT_SPMASK);
928
929 if (mii_reg & 0x0800) {
930 if (mii_reg & 0x1000)
931 *s |= PHY_STAT_100FDX;
932 else
933 *s |= PHY_STAT_100HDX;
934 }
935 else {
936 if (mii_reg & 0x1000)
937 *s |= PHY_STAT_10FDX;
938 else
939 *s |= PHY_STAT_10HDX;
940 }
941}
942
943static phy_info_t phy_info_lxt970 = {
944 0x07810000,
945 "LXT970",
946
947 (const phy_cmd_t []) { /* config */
948#if 0
949// { mk_mii_write(MII_REG_ANAR, 0x0021), NULL },
950
951 /* Set default operation of 100-TX....for some reason
952 * some of these bits are set on power up, which is wrong.
953 */
954 { mk_mii_write(MII_LXT970_CONFIG, 0), NULL },
955#endif
956 { mk_mii_read(MII_REG_CR), mii_parse_cr },
957 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
958 { mk_mii_end, }
959 },
960 (const phy_cmd_t []) { /* startup - enable interrupts */
961 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
962 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
963 { mk_mii_end, }
964 },
965 (const phy_cmd_t []) { /* ack_int */
966 /* read SR and ISR to acknowledge */
967
968 { mk_mii_read(MII_REG_SR), mii_parse_sr },
969 { mk_mii_read(MII_LXT970_ISR), NULL },
970
971 /* find out the current status */
972
973 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
974 { mk_mii_end, }
975 },
976 (const phy_cmd_t []) { /* shutdown - disable interrupts */
977 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
978 { mk_mii_end, }
979 },
980};
981
982#endif /* CONFIG_FEC_LXT970 */
983
984/* ------------------------------------------------------------------------- */
985/* The Level one LXT971 is used on some of my custom boards */
986
987#ifdef CONFIG_FEC_LXT971
988
989/* register definitions for the 971 */
990
991#define MII_LXT971_PCR 16 /* Port Control Register */
992#define MII_LXT971_SR2 17 /* Status Register 2 */
993#define MII_LXT971_IER 18 /* Interrupt Enable Register */
994#define MII_LXT971_ISR 19 /* Interrupt Status Register */
995#define MII_LXT971_LCR 20 /* LED Control Register */
996#define MII_LXT971_TCR 30 /* Transmit Control Register */
997
998/*
999 * I had some nice ideas of running the MDIO faster...
1000 * The 971 should support 8MHz and I tried it, but things acted really
1001 * weird, so 2.5 MHz ought to be enough for anyone...
1002 */
1003
1004static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
1005{
1006 struct fec_enet_private *fep = dev->priv;
1007 volatile uint *s = &(fep->phy_status);
1008
1009 *s &= ~(PHY_STAT_SPMASK);
1010
1011 if (mii_reg & 0x4000) {
1012 if (mii_reg & 0x0200)
1013 *s |= PHY_STAT_100FDX;
1014 else
1015 *s |= PHY_STAT_100HDX;
1016 }
1017 else {
1018 if (mii_reg & 0x0200)
1019 *s |= PHY_STAT_10FDX;
1020 else
1021 *s |= PHY_STAT_10HDX;
1022 }
1023 if (mii_reg & 0x0008)
1024 *s |= PHY_STAT_FAULT;
1025}
1026
1027static phy_info_t phy_info_lxt971 = {
1028 0x0001378e,
1029 "LXT971",
1030
1031 (const phy_cmd_t []) { /* config */
1032// { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */
1033 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1034 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1035 { mk_mii_end, }
1036 },
1037 (const phy_cmd_t []) { /* startup - enable interrupts */
1038 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
1039 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1040
1041 /* Somehow does the 971 tell me that the link is down
1042 * the first read after power-up.
1043 * read here to get a valid value in ack_int */
1044
1045 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1046 { mk_mii_end, }
1047 },
1048 (const phy_cmd_t []) { /* ack_int */
1049 /* find out the current status */
1050
1051 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1052 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
1053
1054 /* we only need to read ISR to acknowledge */
1055
1056 { mk_mii_read(MII_LXT971_ISR), NULL },
1057 { mk_mii_end, }
1058 },
1059 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1060 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
1061 { mk_mii_end, }
1062 },
1063};
1064
1065#endif /* CONFIG_FEC_LXT970 */
1066
1067
1068/* ------------------------------------------------------------------------- */
1069/* The Quality Semiconductor QS6612 is used on the RPX CLLF */
1070
1071#ifdef CONFIG_FEC_QS6612
1072
1073/* register definitions */
1074
1075#define MII_QS6612_MCR 17 /* Mode Control Register */
1076#define MII_QS6612_FTR 27 /* Factory Test Register */
1077#define MII_QS6612_MCO 28 /* Misc. Control Register */
1078#define MII_QS6612_ISR 29 /* Interrupt Source Register */
1079#define MII_QS6612_IMR 30 /* Interrupt Mask Register */
1080#define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
1081
1082static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
1083{
1084 struct fec_enet_private *fep = dev->priv;
1085 volatile uint *s = &(fep->phy_status);
1086
1087 *s &= ~(PHY_STAT_SPMASK);
1088
1089 switch((mii_reg >> 2) & 7) {
1090 case 1: *s |= PHY_STAT_10HDX; break;
1091 case 2: *s |= PHY_STAT_100HDX; break;
1092 case 5: *s |= PHY_STAT_10FDX; break;
1093 case 6: *s |= PHY_STAT_100FDX; break;
1094 }
1095}
1096
1097static phy_info_t phy_info_qs6612 = {
1098 0x00181440,
1099 "QS6612",
1100
1101 (const phy_cmd_t []) { /* config */
1102// { mk_mii_write(MII_REG_ANAR, 0x061), NULL }, /* 10 Mbps */
1103
1104 /* The PHY powers up isolated on the RPX,
1105 * so send a command to allow operation.
1106 */
1107
1108 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1109
1110 /* parse cr and anar to get some info */
1111
1112 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1113 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1114 { mk_mii_end, }
1115 },
1116 (const phy_cmd_t []) { /* startup - enable interrupts */
1117 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1118 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1119 { mk_mii_end, }
1120 },
1121 (const phy_cmd_t []) { /* ack_int */
1122
1123 /* we need to read ISR, SR and ANER to acknowledge */
1124
1125 { mk_mii_read(MII_QS6612_ISR), NULL },
1126 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1127 { mk_mii_read(MII_REG_ANER), NULL },
1128
1129 /* read pcr to get info */
1130
1131 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1132 { mk_mii_end, }
1133 },
1134 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1135 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1136 { mk_mii_end, }
1137 },
1138};
1139
1140#endif /* CONFIG_FEC_QS6612 */
1141
1142/* ------------------------------------------------------------------------- */
1143/* The Advanced Micro Devices AM79C874 is used on the ICU862 */
1144
1145#ifdef CONFIG_FEC_AM79C874
1146
1147/* register definitions for the 79C874 */
1148
1149#define MII_AM79C874_MFR 16 /* Miscellaneous Features Register */
1150#define MII_AM79C874_ICSR 17 /* Interrupt Control/Status Register */
1151#define MII_AM79C874_DR 18 /* Diagnostic Register */
1152#define MII_AM79C874_PMLR 19 /* Power Management & Loopback Register */
1153#define MII_AM79C874_MCR 21 /* Mode Control Register */
1154#define MII_AM79C874_DC 23 /* Disconnect Counter */
1155#define MII_AM79C874_REC 24 /* Receiver Error Counter */
1156
1157static void mii_parse_amd79c874_dr(uint mii_reg, struct net_device *dev, uint data)
1158{
1159 volatile struct fec_enet_private *fep = dev->priv;
1160 uint s = fep->phy_status;
1161
1162 s &= ~(PHY_STAT_SPMASK);
1163
1164 /* Register 18: Bit 10 is data rate, 11 is Duplex */
1165 switch ((mii_reg >> 10) & 3) {
1166 case 0: s |= PHY_STAT_10HDX; break;
1167 case 1: s |= PHY_STAT_100HDX; break;
1168 case 2: s |= PHY_STAT_10FDX; break;
1169 case 3: s |= PHY_STAT_100FDX; break;
1170 }
1171
1172 fep->phy_status = s;
1173}
1174
1175static phy_info_t phy_info_amd79c874 = {
1176 0x00022561,
1177 "AM79C874",
1178
1179 (const phy_cmd_t []) { /* config */
1180// { mk_mii_write(MII_REG_ANAR, 0x021), NULL }, /* 10 Mbps, HD */
1181 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1182 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1183 { mk_mii_end, }
1184 },
1185 (const phy_cmd_t []) { /* startup - enable interrupts */
1186 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1187 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1188 { mk_mii_end, }
1189 },
1190 (const phy_cmd_t []) { /* ack_int */
1191 /* find out the current status */
1192
1193 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1194 { mk_mii_read(MII_AM79C874_DR), mii_parse_amd79c874_dr },
1195
1196 /* we only need to read ICSR to acknowledge */
1197
1198 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1199 { mk_mii_end, }
1200 },
1201 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1202 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1203 { mk_mii_end, }
1204 },
1205};
1206
1207#endif /* CONFIG_FEC_AM79C874 */
1208
1209static phy_info_t *phy_info[] = {
1210
1211#ifdef CONFIG_FEC_LXT970
1212 &phy_info_lxt970,
1213#endif /* CONFIG_FEC_LXT970 */
1214
1215#ifdef CONFIG_FEC_LXT971
1216 &phy_info_lxt971,
1217#endif /* CONFIG_FEC_LXT971 */
1218
1219#ifdef CONFIG_FEC_QS6612
1220 &phy_info_qs6612,
1221#endif /* CONFIG_FEC_QS6612 */
1222
1223#ifdef CONFIG_FEC_AM79C874
1224 &phy_info_amd79c874,
1225#endif /* CONFIG_FEC_AM79C874 */
1226
1227 NULL
1228};
1229
1230static void mii_display_status(struct net_device *dev)
1231{
1232 struct fec_enet_private *fep = dev->priv;
1233 volatile uint *s = &(fep->phy_status);
1234
1235 if (!fep->link && !fep->old_link) {
1236 /* Link is still down - don't print anything */
1237 return;
1238 }
1239
1240 printk("%s: status: ", dev->name);
1241
1242 if (!fep->link) {
1243 printk("link down");
1244 } else {
1245 printk("link up");
1246
1247 switch(*s & PHY_STAT_SPMASK) {
1248 case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break;
1249 case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break;
1250 case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break;
1251 case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break;
1252 default:
1253 printk(", Unknown speed/duplex");
1254 }
1255
1256 if (*s & PHY_STAT_ANC)
1257 printk(", auto-negotiation complete");
1258 }
1259
1260 if (*s & PHY_STAT_FAULT)
1261 printk(", remote fault");
1262
1263 printk(".\n");
1264}
1265
6d5aefb8 1266static void mii_display_config(struct work_struct *work)
1da177e4 1267{
6d5aefb8
DH		 1268 struct fec_enet_private *fep =
1269 container_of(work, struct fec_enet_private, phy_task);
1270 struct net_device *dev = fep->dev;
1da177e4
LT		 1271 volatile uint *s = &(fep->phy_status);
1272
1273 printk("%s: config: auto-negotiation ", dev->name);
1274
1275 if (*s & PHY_CONF_ANE)
1276 printk("on");
1277 else
1278 printk("off");
1279
1280 if (*s & PHY_CONF_100FDX)
1281 printk(", 100FDX");
1282 if (*s & PHY_CONF_100HDX)
1283 printk(", 100HDX");
1284 if (*s & PHY_CONF_10FDX)
1285 printk(", 10FDX");
1286 if (*s & PHY_CONF_10HDX)
1287 printk(", 10HDX");
1288 if (!(*s & PHY_CONF_SPMASK))
1289 printk(", No speed/duplex selected?");
1290
1291 if (*s & PHY_CONF_LOOP)
1292 printk(", loopback enabled");
1293
1294 printk(".\n");
1295
1296 fep->sequence_done = 1;
1297}
1298
6d5aefb8 1299static void mii_relink(struct work_struct *work)
1da177e4 1300{
6d5aefb8
DH		 1301 struct fec_enet_private *fep =
1302 container_of(work, struct fec_enet_private, phy_task);
1303 struct net_device *dev = fep->dev;
1da177e4
LT		 1304 int duplex;
1305
1306 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1307 mii_display_status(dev);
1308 fep->old_link = fep->link;
1309
1310 if (fep->link) {
1311 duplex = 0;
1312 if (fep->phy_status
1313 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1314 duplex = 1;
1315 fec_restart(dev, duplex);
1316 }
1317 else
1318 fec_stop(dev);
1319
1320#if 0
1321 enable_irq(fep->mii_irq);
1322#endif
1323
1324}
1325
1326static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1327{
1328 struct fec_enet_private *fep = dev->priv;
1329
6d5aefb8
DH		 1330 fep->dev = dev;
1331 INIT_WORK(&fep->phy_task, mii_relink);
8b0ed2fb 1332 schedule_work(&fep->phy_task);
1da177e4
LT		 1333}
1334
1335static void mii_queue_config(uint mii_reg, struct net_device *dev)
1336{
1337 struct fec_enet_private *fep = dev->priv;
1338
6d5aefb8
DH		 1339 fep->dev = dev;
1340 INIT_WORK(&fep->phy_task, mii_display_config);
8b0ed2fb 1341 schedule_work(&fep->phy_task);
1da177e4
LT		 1342}
1343
1344
1345
1346phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink },
1347 { mk_mii_end, } };
1348phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config },
1349 { mk_mii_end, } };
1350
1351
1352
1353/* Read remainder of PHY ID.
1354*/
1355static void
1356mii_discover_phy3(uint mii_reg, struct net_device *dev)
1357{
1358 struct fec_enet_private *fep;
1359 int i;
1360
1361 fep = dev->priv;
1362 fep->phy_id |= (mii_reg & 0xffff);
1363
1364 for(i = 0; phy_info[i]; i++)
1365 if(phy_info[i]->id == (fep->phy_id >> 4))
1366 break;
1367
1368 if(!phy_info[i])
1369 panic("%s: PHY id 0x%08x is not supported!\n",
1370 dev->name, fep->phy_id);
1371
1372 fep->phy = phy_info[i];
1373 fep->phy_id_done = 1;
1374
1375 printk("%s: Phy @ 0x%x, type %s (0x%08x)\n",
1376 dev->name, fep->phy_addr, fep->phy->name, fep->phy_id);
1377}
1378
1379/* Scan all of the MII PHY addresses looking for someone to respond
1380 * with a valid ID. This usually happens quickly.
1381 */
1382static void
1383mii_discover_phy(uint mii_reg, struct net_device *dev)
1384{
1385 struct fec_enet_private *fep;
1386 uint phytype;
1387
1388 fep = dev->priv;
1389
1390 if ((phytype = (mii_reg & 0xffff)) != 0xffff) {
1391
1392 /* Got first part of ID, now get remainder.
1393 */
1394 fep->phy_id = phytype << 16;
1395 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2), mii_discover_phy3);
1396 } else {
1397 fep->phy_addr++;
1398 if (fep->phy_addr < 32) {
1399 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1400 mii_discover_phy);
1401 } else {
1402 printk("fec: No PHY device found.\n");
1403 }
1404 }
1405}
1406#endif /* CONFIG_USE_MDIO */
1407
1408/* This interrupt occurs when the PHY detects a link change.
1409*/
fbccb3d7 1410static
1da177e4 1411#ifdef CONFIG_RPXCLASSIC
fbccb3d7 1412void mii_link_interrupt(void *dev_id)
1da177e4 1413#else
39e3eb72 1414irqreturn_t mii_link_interrupt(int irq, void * dev_id)
1da177e4
LT		 1415#endif
1416{
1417#ifdef CONFIG_USE_MDIO
1418 struct net_device *dev = dev_id;
1419 struct fec_enet_private *fep = dev->priv;
1420 volatile immap_t *immap = (immap_t *)IMAP_ADDR;
1421 volatile fec_t *fecp = &(immap->im_cpm.cp_fec);
1422 unsigned int ecntrl = fecp->fec_ecntrl;
1423
1424 /* We need the FEC enabled to access the MII
1425 */
1426 if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) {
1427 fecp->fec_ecntrl |= FEC_ECNTRL_ETHER_EN;
1428 }
1429#endif /* CONFIG_USE_MDIO */
1430
1431#if 0
1432 disable_irq(fep->mii_irq); /* disable now, enable later */
1433#endif
1434
1435
1436#ifdef CONFIG_USE_MDIO
1437 mii_do_cmd(dev, fep->phy->ack_int);
1438 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1439
1440 if ((ecntrl & FEC_ECNTRL_ETHER_EN) == 0) {
1441 fecp->fec_ecntrl = ecntrl; /* restore old settings */
1442 }
1443#else
1444printk("%s[%d] %s: unexpected Link interrupt\n", __FILE__,__LINE__,__FUNCTION__);
1445#endif /* CONFIG_USE_MDIO */
1446
fbccb3d7
ASRF		 1447#ifndef CONFIG_RPXCLASSIC
1448 return IRQ_RETVAL(IRQ_HANDLED);
1449#endif /* CONFIG_RPXCLASSIC */
1da177e4
LT		 1450}
1451
1452static int
1453fec_enet_open(struct net_device *dev)
1454{
1455 struct fec_enet_private *fep = dev->priv;
1456
1457 /* I should reset the ring buffers here, but I don't yet know
1458 * a simple way to do that.
1459 */
1460
1461#ifdef CONFIG_USE_MDIO
1462 fep->sequence_done = 0;
1463 fep->link = 0;
1464
1465 if (fep->phy) {
1466 mii_do_cmd(dev, fep->phy->ack_int);
1467 mii_do_cmd(dev, fep->phy->config);
1468 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1469 while(!fep->sequence_done)
1470 schedule();
1471
1472 mii_do_cmd(dev, fep->phy->startup);
1473 netif_start_queue(dev);
1474 return 0; /* Success */
1475 }
1476 return -ENODEV; /* No PHY we understand */
1477#else
1478 fep->link = 1;
1479 netif_start_queue(dev);
1480 return 0; /* Success */
1481#endif /* CONFIG_USE_MDIO */
1482
1483}
1484
1485static int
1486fec_enet_close(struct net_device *dev)
1487{
1488 /* Don't know what to do yet.
1489 */
1490 netif_stop_queue(dev);
1491 fec_stop(dev);
1492
1493 return 0;
1494}
1495
1496static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
1497{
1498 struct fec_enet_private *fep = (struct fec_enet_private *)dev->priv;
1499
1500 return &fep->stats;
1501}
1502
1503/* Set or clear the multicast filter for this adaptor.
1504 * Skeleton taken from sunlance driver.
1505 * The CPM Ethernet implementation allows Multicast as well as individual
1506 * MAC address filtering. Some of the drivers check to make sure it is
1507 * a group multicast address, and discard those that are not. I guess I
1508 * will do the same for now, but just remove the test if you want
1509 * individual filtering as well (do the upper net layers want or support
1510 * this kind of feature?).
1511 */
1512
1513static void set_multicast_list(struct net_device *dev)
1514{
1515 struct fec_enet_private *fep;
1516 volatile fec_t *ep;
1517
1518 fep = (struct fec_enet_private *)dev->priv;
1519 ep = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec);
1520
1521 if (dev->flags&IFF_PROMISC) {
1522
1523 /* Log any net taps. */
1524 printk("%s: Promiscuous mode enabled.\n", dev->name);
1525 ep->fec_r_cntrl |= FEC_RCNTRL_PROM;
1526 } else {
1527
1528 ep->fec_r_cntrl &= ~FEC_RCNTRL_PROM;
1529
1530 if (dev->flags & IFF_ALLMULTI) {
1531 /* Catch all multicast addresses, so set the
1532 * filter to all 1's.
1533 */
1534 ep->fec_hash_table_high = 0xffffffff;
1535 ep->fec_hash_table_low = 0xffffffff;
1536 }
1537#if 0
1538 else {
1539 /* Clear filter and add the addresses in the list.
1540 */
1541 ep->sen_gaddr1 = 0;
1542 ep->sen_gaddr2 = 0;
1543 ep->sen_gaddr3 = 0;
1544 ep->sen_gaddr4 = 0;
1545
1546 dmi = dev->mc_list;
1547
1548 for (i=0; i<dev->mc_count; i++) {
1549
1550 /* Only support group multicast for now.
1551 */
1552 if (!(dmi->dmi_addr[0] & 1))
1553 continue;
1554
1555 /* The address in dmi_addr is LSB first,
1556 * and taddr is MSB first. We have to
1557 * copy bytes MSB first from dmi_addr.
1558 */
1559 mcptr = (u_char *)dmi->dmi_addr + 5;
1560 tdptr = (u_char *)&ep->sen_taddrh;
1561 for (j=0; j<6; j++)
1562 *tdptr++ = *mcptr--;
1563
1564 /* Ask CPM to run CRC and set bit in
1565 * filter mask.
1566 */
1567 cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC1, CPM_CR_SET_GADDR) | CPM_CR_FLG;
1568 /* this delay is necessary here -- Cort */
1569 udelay(10);
1570 while (cpmp->cp_cpcr & CPM_CR_FLG);
1571 }
1572 }
1573#endif
1574 }
1575}
1576
1577/* Initialize the FEC Ethernet on 860T.
1578 */
1579static int __init fec_enet_init(void)
1580{
1581 struct net_device *dev;
1582 struct fec_enet_private *fep;
1583 int i, j, k, err;
1584 unsigned char *eap, *iap, *ba;
fc007ddd 1585 dma_addr_t mem_addr;
1da177e4
LT		 1586 volatile cbd_t *bdp;
1587 cbd_t *cbd_base;
1588 volatile immap_t *immap;
1589 volatile fec_t *fecp;
1590 bd_t *bd;
1591#ifdef CONFIG_SCC_ENET
1592 unsigned char tmpaddr[6];
1593#endif
1594
1595 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1596
1597 bd = (bd_t *)__res;
1598
1599 dev = alloc_etherdev(sizeof(*fep));
1600 if (!dev)
1601 return -ENOMEM;
1602
1603 fep = dev->priv;
1604
1605 fecp = &(immap->im_cpm.cp_fec);
1606
1607 /* Whack a reset. We should wait for this.
1608 */
1609 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
1610 for (i = 0;
1611 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
1612 ++i) {
1613 udelay(1);
1614 }
1615 if (i == FEC_RESET_DELAY) {
1616 printk ("FEC Reset timeout!\n");
1617 }
1618
1619 /* Set the Ethernet address. If using multiple Enets on the 8xx,
1620 * this needs some work to get unique addresses.
1621 */
1622 eap = (unsigned char *)my_enet_addr;
1623 iap = bd->bi_enetaddr;
1624
1625#ifdef CONFIG_SCC_ENET
1626 /*
1627 * If a board has Ethernet configured both on a SCC and the
1628 * FEC, it needs (at least) 2 MAC addresses (we know that Sun
1629 * disagrees, but anyway). For the FEC port, we create
1630 * another address by setting one of the address bits above
1631 * something that would have (up to now) been allocated.
1632 */
1633 for (i=0; i<6; i++)
1634 tmpaddr[i] = *iap++;
1635 tmpaddr[3] |= 0x80;
1636 iap = tmpaddr;
1637#endif
1638
1639 for (i=0; i<6; i++) {
1640 dev->dev_addr[i] = *eap++ = *iap++;
1641 }
1642
1643 /* Allocate memory for buffer descriptors.
1644 */
1645 if (((RX_RING_SIZE + TX_RING_SIZE) * sizeof(cbd_t)) > PAGE_SIZE) {
1646 printk("FEC init error. Need more space.\n");
1647 printk("FEC initialization failed.\n");
1648 return 1;
1649 }
fc007ddd
ASRF		 1650 cbd_base = (cbd_t *)dma_alloc_coherent(dev->class_dev.dev, PAGE_SIZE,
1651 &mem_addr, GFP_KERNEL);
1da177e4
LT		 1652
1653 /* Set receive and transmit descriptor base.
1654 */
1655 fep->rx_bd_base = cbd_base;
1656 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1657
1658 fep->skb_cur = fep->skb_dirty = 0;
1659
1660 /* Initialize the receive buffer descriptors.
1661 */
1662 bdp = fep->rx_bd_base;
1663 k = 0;
1664 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
1665
1666 /* Allocate a page.
1667 */
fc007ddd
ASRF		 1668 ba = (unsigned char *)dma_alloc_coherent(dev->class_dev.dev,
1669 PAGE_SIZE,
1670 &mem_addr,
1671 GFP_KERNEL);
1da177e4
LT		 1672 /* BUG: no check for failure */
1673
1674 /* Initialize the BD for every fragment in the page.
1675 */
1676 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
1677 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1678 bdp->cbd_bufaddr = mem_addr;
1679 fep->rx_vaddr[k++] = ba;
1680 mem_addr += FEC_ENET_RX_FRSIZE;
1681 ba += FEC_ENET_RX_FRSIZE;
1682 bdp++;
1683 }
1684 }
1685
1686 /* Set the last buffer to wrap.
1687 */
1688 bdp--;
1689 bdp->cbd_sc |= BD_SC_WRAP;
1690
1691#ifdef CONFIG_FEC_PACKETHOOK
1692 fep->ph_lock = 0;
1693 fep->ph_rxhandler = fep->ph_txhandler = NULL;
1694 fep->ph_proto = 0;
1695 fep->ph_regaddr = NULL;
1696 fep->ph_priv = NULL;
1697#endif
1698
1699 /* Install our interrupt handler.
1700 */
1701 if (request_irq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1702 panic("Could not allocate FEC IRQ!");
1703
1704#ifdef CONFIG_RPXCLASSIC
1705 /* Make Port C, bit 15 an input that causes interrupts.
1706 */
1707 immap->im_ioport.iop_pcpar &= ~0x0001;
1708 immap->im_ioport.iop_pcdir &= ~0x0001;
1709 immap->im_ioport.iop_pcso &= ~0x0001;
1710 immap->im_ioport.iop_pcint |= 0x0001;
1711 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1712
1713 /* Make LEDS reflect Link status.
1714 */
1715 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1716#endif
1717
1718#ifdef PHY_INTERRUPT
1719 ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |=
1720 (0x80000000 >> PHY_INTERRUPT);
1721
1722 if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0, "mii", dev) != 0)
1723 panic("Could not allocate MII IRQ!");
1724#endif
1725
1726 dev->base_addr = (unsigned long)fecp;
1727
1728 /* The FEC Ethernet specific entries in the device structure. */
1729 dev->open = fec_enet_open;
1730 dev->hard_start_xmit = fec_enet_start_xmit;
1731 dev->tx_timeout = fec_timeout;
1732 dev->watchdog_timeo = TX_TIMEOUT;
1733 dev->stop = fec_enet_close;
1734 dev->get_stats = fec_enet_get_stats;
1735 dev->set_multicast_list = set_multicast_list;
1736
1737#ifdef CONFIG_USE_MDIO
1738 for (i=0; i<NMII-1; i++)
1739 mii_cmds[i].mii_next = &mii_cmds[i+1];
1740 mii_free = mii_cmds;
1741#endif /* CONFIG_USE_MDIO */
1742
1743 /* Configure all of port D for MII.
1744 */
1745 immap->im_ioport.iop_pdpar = 0x1fff;
1746
1747 /* Bits moved from Rev. D onward.
1748 */
1749 if ((mfspr(SPRN_IMMR) & 0xffff) < 0x0501)
1750 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1751 else
1752 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1753
1754#ifdef CONFIG_USE_MDIO
1755 /* Set MII speed to 2.5 MHz
1756 */
1757 fecp->fec_mii_speed = fep->phy_speed =
1758 (( (bd->bi_intfreq + 500000) / 2500000 / 2 ) & 0x3F ) << 1;
1759#else
1760 fecp->fec_mii_speed = 0; /* turn off MDIO */
1761#endif /* CONFIG_USE_MDIO */
1762
1763 err = register_netdev(dev);
1764 if (err) {
1765 free_netdev(dev);
1766 return err;
1767 }
1768
1769 printk ("%s: FEC ENET Version 0.2, FEC irq %d"
1770#ifdef PHY_INTERRUPT
1771 ", MII irq %d"
1772#endif
1773 ", addr ",
1774 dev->name, FEC_INTERRUPT
1775#ifdef PHY_INTERRUPT
1776 , PHY_INTERRUPT
1777#endif
1778 );
1779 for (i=0; i<6; i++)
1780 printk("%02x%c", dev->dev_addr[i], (i==5) ? '\n' : ':');
1781
1782#ifdef CONFIG_USE_MDIO /* start in full duplex mode, and negotiate speed */
1783 fec_restart (dev, 1);
1784#else /* always use half duplex mode only */
1785 fec_restart (dev, 0);
1786#endif
1787
1788#ifdef CONFIG_USE_MDIO
1789 /* Queue up command to detect the PHY and initialize the
1790 * remainder of the interface.
1791 */
1792 fep->phy_id_done = 0;
1793 fep->phy_addr = 0;
1794 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1795#endif /* CONFIG_USE_MDIO */
1796
1797 return 0;
1798}
1799module_init(fec_enet_init);
1800
1801/* This function is called to start or restart the FEC during a link
1802 * change. This only happens when switching between half and full
1803 * duplex.
1804 */
1805static void
1806fec_restart(struct net_device *dev, int duplex)
1807{
1808 struct fec_enet_private *fep;
1809 int i;
1810 volatile cbd_t *bdp;
1811 volatile immap_t *immap;
1812 volatile fec_t *fecp;
1813
1814 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1815
1816 fecp = &(immap->im_cpm.cp_fec);
1817
1818 fep = dev->priv;
1819
1820 /* Whack a reset. We should wait for this.
1821 */
1822 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
1823 for (i = 0;
1824 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
1825 ++i) {
1826 udelay(1);
1827 }
1828 if (i == FEC_RESET_DELAY) {
1829 printk ("FEC Reset timeout!\n");
1830 }
1831
1832 /* Set station address.
1833 */
1834 fecp->fec_addr_low = (my_enet_addr[0] << 16) | my_enet_addr[1];
1835 fecp->fec_addr_high = my_enet_addr[2];
1836
1837 /* Reset all multicast.
1838 */
1839 fecp->fec_hash_table_high = 0;
1840 fecp->fec_hash_table_low = 0;
1841
1842 /* Set maximum receive buffer size.
1843 */
1844 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
1845 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1846
1847 /* Set receive and transmit descriptor base.
1848 */
1849 fecp->fec_r_des_start = iopa((uint)(fep->rx_bd_base));
1850 fecp->fec_x_des_start = iopa((uint)(fep->tx_bd_base));
1851
1852 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1853 fep->cur_rx = fep->rx_bd_base;
1854
1855 /* Reset SKB transmit buffers.
1856 */
1857 fep->skb_cur = fep->skb_dirty = 0;
1858 for (i=0; i<=TX_RING_MOD_MASK; i++) {
1859 if (fep->tx_skbuff[i] != NULL) {
1860 dev_kfree_skb(fep->tx_skbuff[i]);
1861 fep->tx_skbuff[i] = NULL;
1862 }
1863 }
1864
1865 /* Initialize the receive buffer descriptors.
1866 */
1867 bdp = fep->rx_bd_base;
1868 for (i=0; i<RX_RING_SIZE; i++) {
1869
1870 /* Initialize the BD for every fragment in the page.
1871 */
1872 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1873 bdp++;
1874 }
1875
1876 /* Set the last buffer to wrap.
1877 */
1878 bdp--;
1879 bdp->cbd_sc |= BD_SC_WRAP;
1880
a8de5ce9 1881 /* ...and the same for transmit.
1da177e4
LT		 1882 */
1883 bdp = fep->tx_bd_base;
1884 for (i=0; i<TX_RING_SIZE; i++) {
1885
1886 /* Initialize the BD for every fragment in the page.
1887 */
1888 bdp->cbd_sc = 0;
1889 bdp->cbd_bufaddr = 0;
1890 bdp++;
1891 }
1892
1893 /* Set the last buffer to wrap.
1894 */
1895 bdp--;
1896 bdp->cbd_sc |= BD_SC_WRAP;
1897
1898 /* Enable MII mode.
1899 */
1900 if (duplex) {
1901 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; /* MII enable */
1902 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; /* FD enable */
1903 }
1904 else {
1905 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
1906 fecp->fec_x_cntrl = 0;
1907 }
1908 fep->full_duplex = duplex;
1909
1910 /* Enable big endian and don't care about SDMA FC.
1911 */
1912 fecp->fec_fun_code = 0x78000000;
1913
1914#ifdef CONFIG_USE_MDIO
1915 /* Set MII speed.
1916 */
1917 fecp->fec_mii_speed = fep->phy_speed;
1918#endif /* CONFIG_USE_MDIO */
1919
1920 /* Clear any outstanding interrupt.
1921 */
1922 fecp->fec_ievent = 0xffc0;
1923
1924 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1925
1926 /* Enable interrupts we wish to service.
1927 */
1928 fecp->fec_imask = ( FEC_ENET_TXF | FEC_ENET_TXB |
1929 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII );
1930
1931 /* And last, enable the transmit and receive processing.
1932 */
1933 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
1934 fecp->fec_r_des_active = 0x01000000;
1935}
1936
1937static void
1938fec_stop(struct net_device *dev)
1939{
1940 volatile immap_t *immap;
1941 volatile fec_t *fecp;
1942 struct fec_enet_private *fep;
1943 int i;
1944
1945 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1946
1947 fecp = &(immap->im_cpm.cp_fec);
1948
1949 if ((fecp->fec_ecntrl & FEC_ECNTRL_ETHER_EN) == 0)
1950 return; /* already down */
1951
1952 fep = dev->priv;
1953
1954
1955 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
1956
1957 for (i = 0;
1958 ((fecp->fec_ievent & 0x10000000) == 0) && (i < FEC_RESET_DELAY);
1959 ++i) {
1960 udelay(1);
1961 }
1962 if (i == FEC_RESET_DELAY) {
1963 printk ("FEC timeout on graceful transmit stop\n");
1964 }
1965
1966 /* Clear outstanding MII command interrupts.
1967 */
1968 fecp->fec_ievent = FEC_ENET_MII;
1969
1970 /* Enable MII command finished interrupt
1971 */
1972 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1973 fecp->fec_imask = FEC_ENET_MII;
1974
1975#ifdef CONFIG_USE_MDIO
1976 /* Set MII speed.
1977 */
1978 fecp->fec_mii_speed = fep->phy_speed;
1979#endif /* CONFIG_USE_MDIO */
1980
1981 /* Disable FEC
1982 */
1983 fecp->fec_ecntrl &= ~(FEC_ECNTRL_ETHER_EN);
1984}
Linux 6.x block layer and io_uring tree(s)