[linux-2.6-block.git] / arch / powerpc / sysdev / xive / native.c

/*
 * Copyright 2016,2017 IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#define pr_fmt(fmt) "xive: " fmt

#include <linux/types.h>
#include <linux/irq.h>
#include <linux/debugfs.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/seq_file.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/cpumask.h>
#include <linux/mm.h>

#include <asm/prom.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/irq.h>
#include <asm/errno.h>
#include <asm/xive.h>
#include <asm/xive-regs.h>
#include <asm/opal.h>
#include <asm/kvm_ppc.h>

#include "xive-internal.h"


static u32 xive_provision_size;
static u32 *xive_provision_chips;
static u32 xive_provision_chip_count;
static u32 xive_queue_shift;
static u32 xive_pool_vps = XIVE_INVALID_VP;
static struct kmem_cache *xive_provision_cache;
static bool xive_has_single_esc;

int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
{
	__be64 flags, eoi_page, trig_page;
	__be32 esb_shift, src_chip;
	u64 opal_flags;
	s64 rc;

	memset(data, 0, sizeof(*data));

	rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page,
				    &esb_shift, &src_chip);
	if (rc) {
		pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n",
		       hw_irq, rc);
		return -EINVAL;
	}

	opal_flags = be64_to_cpu(flags);
	if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI)
		data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
	if (opal_flags & OPAL_XIVE_IRQ_LSI)
		data->flags |= XIVE_IRQ_FLAG_LSI;
	if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
		data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
	if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
		data->flags |= XIVE_IRQ_FLAG_MASK_FW;
	if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
		data->flags |= XIVE_IRQ_FLAG_EOI_FW;
	data->eoi_page = be64_to_cpu(eoi_page);
	data->trig_page = be64_to_cpu(trig_page);
	data->esb_shift = be32_to_cpu(esb_shift);
	data->src_chip = be32_to_cpu(src_chip);

	data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
	if (!data->eoi_mmio) {
		pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
		return -ENOMEM;
	}

	data->hw_irq = hw_irq;

	if (!data->trig_page)
		return 0;
	if (data->trig_page == data->eoi_page) {
		data->trig_mmio = data->eoi_mmio;
		return 0;
	}

	data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
	if (!data->trig_mmio) {
		pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
		return -ENOMEM;
	}
	return 0;
}
EXPORT_SYMBOL_GPL(xive_native_populate_irq_data);

int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
{
	s64 rc;

	for (;;) {
		rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq);
		if (rc != OPAL_BUSY)
			break;
		msleep(1);
	}
	return rc == 0 ? 0 : -ENXIO;
}
EXPORT_SYMBOL_GPL(xive_native_configure_irq);


/* This can be called multiple time to change a queue configuration */
int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
				__be32 *qpage, u32 order, bool can_escalate)
{
	s64 rc = 0;
	__be64 qeoi_page_be;
	__be32 esc_irq_be;
	u64 flags, qpage_phys;

	/* If there's an actual queue page, clean it */
	if (order) {
		if (WARN_ON(!qpage))
			return -EINVAL;
		qpage_phys = __pa(qpage);
	} else
		qpage_phys = 0;

	/* Initialize the rest of the fields */
	q->msk = order ? ((1u << (order - 2)) - 1) : 0;
	q->idx = 0;
	q->toggle = 0;

	rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL,
				      &qeoi_page_be,
				      &esc_irq_be,
				      NULL);
	if (rc) {
		pr_err("Error %lld getting queue info prio %d\n", rc, prio);
		rc = -EIO;
		goto fail;
	}
	q->eoi_phys = be64_to_cpu(qeoi_page_be);

	/* Default flags */
	flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY | OPAL_XIVE_EQ_ENABLED;

	/* Escalation needed ? */
	if (can_escalate) {
		q->esc_irq = be32_to_cpu(esc_irq_be);
		flags |= OPAL_XIVE_EQ_ESCALATE;
	}

	/* Configure and enable the queue in HW */
	for (;;) {
		rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags);
		if (rc != OPAL_BUSY)
			break;
		msleep(1);
	}
	if (rc) {
		pr_err("Error %lld setting queue for prio %d\n", rc, prio);
		rc = -EIO;
	} else {
		/*
		 * KVM code requires all of the above to be visible before
		 * q->qpage is set due to how it manages IPI EOIs
		 */
		wmb();
		q->qpage = qpage;
	}
fail:
	return rc;
}
EXPORT_SYMBOL_GPL(xive_native_configure_queue);

static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
{
	s64 rc;

	/* Disable the queue in HW */
	for (;;) {
		rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0);
		if (rc != OPAL_BUSY)
			break;
		msleep(1);
	}
	if (rc)
		pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
}

void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
{
	__xive_native_disable_queue(vp_id, q, prio);
}
EXPORT_SYMBOL_GPL(xive_native_disable_queue);

static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
{
	struct xive_q *q = &xc->queue[prio];
	__be32 *qpage;

	qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
	if (IS_ERR(qpage))
		return PTR_ERR(qpage);

	return xive_native_configure_queue(get_hard_smp_processor_id(cpu),
					   q, prio, qpage, xive_queue_shift, false);
}

static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
{
	struct xive_q *q = &xc->queue[prio];
	unsigned int alloc_order;

	/*
	 * We use the variant with no iounmap as this is called on exec
	 * from an IPI and iounmap isn't safe
	 */
	__xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio);
	alloc_order = xive_alloc_order(xive_queue_shift);
	free_pages((unsigned long)q->qpage, alloc_order);
	q->qpage = NULL;
}

static bool xive_native_match(struct device_node *node)
{
	return of_device_is_compatible(node, "ibm,opal-xive-vc");
}

#ifdef CONFIG_SMP
static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
{
	struct device_node *np;
	unsigned int chip_id;
	s64 irq;

	/* Find the chip ID */
	np = of_get_cpu_node(cpu, NULL);
	if (np) {
		if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0)
			chip_id = 0;
	}

	/* Allocate an IPI and populate info about it */
	for (;;) {
		irq = opal_xive_allocate_irq(chip_id);
		if (irq == OPAL_BUSY) {
			msleep(1);
			continue;
		}
		if (irq < 0) {
			pr_err("Failed to allocate IPI on CPU %d\n", cpu);
			return -ENXIO;
		}
		xc->hw_ipi = irq;
		break;
	}
	return 0;
}
#endif /* CONFIG_SMP */

u32 xive_native_alloc_irq(void)
{
	s64 rc;

	for (;;) {
		rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);
		if (rc != OPAL_BUSY)
			break;
		msleep(1);
	}
	if (rc < 0)
		return 0;
	return rc;
}
EXPORT_SYMBOL_GPL(xive_native_alloc_irq);

void xive_native_free_irq(u32 irq)
{
	for (;;) {
		s64 rc = opal_xive_free_irq(irq);
		if (rc != OPAL_BUSY)
			break;
		msleep(1);
	}
}
EXPORT_SYMBOL_GPL(xive_native_free_irq);

#ifdef CONFIG_SMP
static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
{
	s64 rc;

	/* Free the IPI */
	if (!xc->hw_ipi)
		return;
	for (;;) {
		rc = opal_xive_free_irq(xc->hw_ipi);
		if (rc == OPAL_BUSY) {
			msleep(1);
			continue;
		}
		xc->hw_ipi = 0;
		break;
	}
}
#endif /* CONFIG_SMP */

static void xive_native_shutdown(void)
{
	/* Switch the XIVE to emulation mode */
	opal_xive_reset(OPAL_XIVE_MODE_EMU);
}

/*
 * Perform an "ack" cycle on the current thread, thus
 * grabbing the pending active priorities and updating
 * the CPPR to the most favored one.
 */
static void xive_native_update_pending(struct xive_cpu *xc)
{
	u8 he, cppr;
	u16 ack;

	/* Perform the acknowledge hypervisor to register cycle */
	ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG));

	/* Synchronize subsequent queue accesses */
	mb();

	/*
	 * Grab the CPPR and the "HE" field which indicates the source
	 * of the hypervisor interrupt (if any)
	 */
	cppr = ack & 0xff;
	he = GETFIELD(TM_QW3_NSR_HE, (ack >> 8));
	switch(he) {
	case TM_QW3_NSR_HE_NONE: /* Nothing to see here */
		break;
	case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */
		if (cppr == 0xff)
			return;
		/* Mark the priority pending */
		xc->pending_prio |= 1 << cppr;

		/*
		 * A new interrupt should never have a CPPR less favored
		 * than our current one.
		 */
		if (cppr >= xc->cppr)
			pr_err("CPU %d odd ack CPPR, got %d at %d\n",
			       smp_processor_id(), cppr, xc->cppr);

		/* Update our idea of what the CPPR is */
		xc->cppr = cppr;
		break;
	case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */
	case TM_QW3_NSR_HE_LSI:  /* Legacy FW LSI (unused) */
		pr_err("CPU %d got unexpected interrupt type HE=%d\n",
		       smp_processor_id(), he);
		return;
	}
}

static void xive_native_eoi(u32 hw_irq)
{
	/*
	 * Not normally used except if specific interrupts need
	 * a workaround on EOI.
	 */
	opal_int_eoi(hw_irq);
}

static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
{
	s64 rc;
	u32 vp;
	__be64 vp_cam_be;
	u64 vp_cam;

	if (xive_pool_vps == XIVE_INVALID_VP)
		return;

	/* Enable the pool VP */
	vp = xive_pool_vps + cpu;
	pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp);
	for (;;) {
		rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
		if (rc != OPAL_BUSY)
			break;
		msleep(1);
	}
	if (rc) {
		pr_err("Failed to enable pool VP on CPU %d\n", cpu);
		return;
	}

	/* Grab it's CAM value */
	rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
	if (rc) {
		pr_err("Failed to get pool VP info CPU %d\n", cpu);
		return;
	}
	vp_cam = be64_to_cpu(vp_cam_be);

	pr_debug("VP CAM = %llx\n", vp_cam);

	/* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
	pr_debug("(Old HW value: %08x)\n",
		 in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
	out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
	out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2,
		 TM_QW2W2_VP | vp_cam);
	pr_debug("(New HW value: %08x)\n",
		 in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
}

static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
{
	s64 rc;
	u32 vp;

	if (xive_pool_vps == XIVE_INVALID_VP)
		return;

	/* Pull the pool VP from the CPU */
	in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);

	/* Disable it */
	vp = xive_pool_vps + cpu;
	for (;;) {
		rc = opal_xive_set_vp_info(vp, 0, 0);
		if (rc != OPAL_BUSY)
			break;
		msleep(1);
	}
}

void xive_native_sync_source(u32 hw_irq)
{
	opal_xive_sync(XIVE_SYNC_EAS, hw_irq);
}
EXPORT_SYMBOL_GPL(xive_native_sync_source);

static const struct xive_ops xive_native_ops = {
	.populate_irq_data	= xive_native_populate_irq_data,
	.configure_irq		= xive_native_configure_irq,
	.setup_queue		= xive_native_setup_queue,
	.cleanup_queue		= xive_native_cleanup_queue,
	.match			= xive_native_match,
	.shutdown		= xive_native_shutdown,
	.update_pending		= xive_native_update_pending,
	.eoi			= xive_native_eoi,
	.setup_cpu		= xive_native_setup_cpu,
	.teardown_cpu		= xive_native_teardown_cpu,
	.sync_source		= xive_native_sync_source,
#ifdef CONFIG_SMP
	.get_ipi		= xive_native_get_ipi,
	.put_ipi		= xive_native_put_ipi,
#endif /* CONFIG_SMP */
	.name			= "native",
};

static bool xive_parse_provisioning(struct device_node *np)
{
	int rc;

	if (of_property_read_u32(np, "ibm,xive-provision-page-size",
				 &xive_provision_size) < 0)
		return true;
	rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4);
	if (rc < 0) {
		pr_err("Error %d getting provision chips array\n", rc);
		return false;
	}
	xive_provision_chip_count = rc;
	if (rc == 0)
		return true;

	xive_provision_chips = kzalloc(4 * xive_provision_chip_count,
				       GFP_KERNEL);
	if (WARN_ON(!xive_provision_chips))
		return false;

	rc = of_property_read_u32_array(np, "ibm,xive-provision-chips",
					xive_provision_chips,
					xive_provision_chip_count);
	if (rc < 0) {
		pr_err("Error %d reading provision chips array\n", rc);
		return false;
	}

	xive_provision_cache = kmem_cache_create("xive-provision",
						 xive_provision_size,
						 xive_provision_size,
						 0, NULL);
	if (!xive_provision_cache) {
		pr_err("Failed to allocate provision cache\n");
		return false;
	}
	return true;
}

static void xive_native_setup_pools(void)
{
	/* Allocate a pool big enough */
	pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids);

	xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids);
	if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP))
		pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n");

	pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n",
		 xive_pool_vps, nr_cpu_ids);
}

u32 xive_native_default_eq_shift(void)
{
	return xive_queue_shift;
}
EXPORT_SYMBOL_GPL(xive_native_default_eq_shift);

bool __init xive_native_init(void)
{
	struct device_node *np;
	struct resource r;
	void __iomem *tima;
	struct property *prop;
	u8 max_prio = 7;
	const __be32 *p;
	u32 val, cpu;
	s64 rc;

	if (xive_cmdline_disabled)
		return false;

	pr_devel("xive_native_init()\n");
	np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe");
	if (!np) {
		pr_devel("not found !\n");
		return false;
	}
	pr_devel("Found %pOF\n", np);

	/* Resource 1 is HV window */
	if (of_address_to_resource(np, 1, &r)) {
		pr_err("Failed to get thread mgmnt area resource\n");
		return false;
	}
	tima = ioremap(r.start, resource_size(&r));
	if (!tima) {
		pr_err("Failed to map thread mgmnt area\n");
		return false;
	}

	/* Read number of priorities */
	if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0)
		max_prio = val - 1;

	/* Iterate the EQ sizes and pick one */
	of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
		xive_queue_shift = val;
		if (val == PAGE_SHIFT)
			break;
	}

	/* Do we support single escalation */
	if (of_get_property(np, "single-escalation-support", NULL) != NULL)
		xive_has_single_esc = true;

	/* Configure Thread Management areas for KVM */
	for_each_possible_cpu(cpu)
		kvmppc_set_xive_tima(cpu, r.start, tima);

	/* Grab size of provisionning pages */
	xive_parse_provisioning(np);

	/* Switch the XIVE to exploitation mode */
	rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL);
	if (rc) {
		pr_err("Switch to exploitation mode failed with error %lld\n", rc);
		return false;
	}

	/* Setup some dummy HV pool VPs */
	xive_native_setup_pools();

	/* Initialize XIVE core with our backend */
	if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS,
			    max_prio)) {
		opal_xive_reset(OPAL_XIVE_MODE_EMU);
		return false;
	}
	pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
	return true;
}

static bool xive_native_provision_pages(void)
{
	u32 i;
	void *p;

	for (i = 0; i < xive_provision_chip_count; i++) {
		u32 chip = xive_provision_chips[i];

		/*
		 * XXX TODO: Try to make the allocation local to the node where
		 * the chip resides.
		 */
		p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL);
		if (!p) {
			pr_err("Failed to allocate provisioning page\n");
			return false;
		}
		opal_xive_donate_page(chip, __pa(p));
	}
	return true;
}

u32 xive_native_alloc_vp_block(u32 max_vcpus)
{
	s64 rc;
	u32 order;

	order = fls(max_vcpus) - 1;
	if (max_vcpus > (1 << order))
		order++;

	pr_debug("VP block alloc, for max VCPUs %d use order %d\n",
		 max_vcpus, order);

	for (;;) {
		rc = opal_xive_alloc_vp_block(order);
		switch (rc) {
		case OPAL_BUSY:
			msleep(1);
			break;
		case OPAL_XIVE_PROVISIONING:
			if (!xive_native_provision_pages())
				return XIVE_INVALID_VP;
			break;
		default:
			if (rc < 0) {
				pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n",
				       order, rc);
				return XIVE_INVALID_VP;
			}
			return rc;
		}
	}
}
EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block);

void xive_native_free_vp_block(u32 vp_base)
{
	s64 rc;

	if (vp_base == XIVE_INVALID_VP)
		return;

	rc = opal_xive_free_vp_block(vp_base);
	if (rc < 0)
		pr_warn("OPAL error %lld freeing VP block\n", rc);
}
EXPORT_SYMBOL_GPL(xive_native_free_vp_block);

int xive_native_enable_vp(u32 vp_id, bool single_escalation)
{
	s64 rc;
	u64 flags = OPAL_XIVE_VP_ENABLED;

	if (single_escalation)
		flags |= OPAL_XIVE_VP_SINGLE_ESCALATION;
	for (;;) {
		rc = opal_xive_set_vp_info(vp_id, flags, 0);
		if (rc != OPAL_BUSY)
			break;
		msleep(1);
	}
	return rc ? -EIO : 0;
}
EXPORT_SYMBOL_GPL(xive_native_enable_vp);

int xive_native_disable_vp(u32 vp_id)
{
	s64 rc;

	for (;;) {
		rc = opal_xive_set_vp_info(vp_id, 0, 0);
		if (rc != OPAL_BUSY)
			break;
		msleep(1);
	}
	return rc ? -EIO : 0;
}
EXPORT_SYMBOL_GPL(xive_native_disable_vp);

int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id)
{
	__be64 vp_cam_be;
	__be32 vp_chip_id_be;
	s64 rc;

	rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
	if (rc)
		return -EIO;
	*out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
	*out_chip_id = be32_to_cpu(vp_chip_id_be);

	return 0;
}
EXPORT_SYMBOL_GPL(xive_native_get_vp_info);

bool xive_native_has_single_escalation(void)
{
	return xive_has_single_esc;
}
EXPORT_SYMBOL_GPL(xive_native_has_single_escalation);
Commit	Line	Data
243e2511 BH	1	/*
	2	* Copyright 2016,2017 IBM Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9
	10	#define pr_fmt(fmt) "xive: " fmt
	11
	12	#include <linux/types.h>
	13	#include <linux/irq.h>
	14	#include <linux/debugfs.h>
	15	#include <linux/smp.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/seq_file.h>
	18	#include <linux/init.h>
	19	#include <linux/of.h>
	20	#include <linux/slab.h>
	21	#include <linux/spinlock.h>
	22	#include <linux/delay.h>
	23	#include <linux/cpumask.h>
	24	#include <linux/mm.h>
	25
	26	#include <asm/prom.h>
	27	#include <asm/io.h>
	28	#include <asm/smp.h>
	29	#include <asm/irq.h>
	30	#include <asm/errno.h>
	31	#include <asm/xive.h>
	32	#include <asm/xive-regs.h>
	33	#include <asm/opal.h>
5af50993	34	#include <asm/kvm_ppc.h>
243e2511 BH	35
	36	#include "xive-internal.h"
	37
	38
	39	static u32 xive_provision_size;
	40	static u32 *xive_provision_chips;
	41	static u32 xive_provision_chip_count;
	42	static u32 xive_queue_shift;
	43	static u32 xive_pool_vps = XIVE_INVALID_VP;
	44	static struct kmem_cache *xive_provision_cache;
bf4159da	45	static bool xive_has_single_esc;
243e2511 BH	46
	47	int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
	48	{
	49	__be64 flags, eoi_page, trig_page;
	50	__be32 esb_shift, src_chip;
	51	u64 opal_flags;
	52	s64 rc;
	53
	54	memset(data, 0, sizeof(*data));
	55
	56	rc = opal_xive_get_irq_info(hw_irq, &flags, &eoi_page, &trig_page,
	57	&esb_shift, &src_chip);
	58	if (rc) {
	59	pr_err("opal_xive_get_irq_info(0x%x) returned %lld\n",
	60	hw_irq, rc);
	61	return -EINVAL;
	62	}
	63
	64	opal_flags = be64_to_cpu(flags);
	65	if (opal_flags & OPAL_XIVE_IRQ_STORE_EOI)
	66	data->flags \|= XIVE_IRQ_FLAG_STORE_EOI;
	67	if (opal_flags & OPAL_XIVE_IRQ_LSI)
	68	data->flags \|= XIVE_IRQ_FLAG_LSI;
	69	if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
	70	data->flags \|= XIVE_IRQ_FLAG_SHIFT_BUG;
	71	if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
	72	data->flags \|= XIVE_IRQ_FLAG_MASK_FW;
	73	if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
	74	data->flags \|= XIVE_IRQ_FLAG_EOI_FW;
	75	data->eoi_page = be64_to_cpu(eoi_page);
	76	data->trig_page = be64_to_cpu(trig_page);
	77	data->esb_shift = be32_to_cpu(esb_shift);
	78	data->src_chip = be32_to_cpu(src_chip);
	79
	80	data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
	81	if (!data->eoi_mmio) {
	82	pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
	83	return -ENOMEM;
	84	}
	85
c58a14a9 CLG	86	data->hw_irq = hw_irq;
c58a14a9 CLG	87
243e2511 BH	88	if (!data->trig_page)
	89	return 0;
	90	if (data->trig_page == data->eoi_page) {
	91	data->trig_mmio = data->eoi_mmio;
	92	return 0;
	93	}
	94
	95	data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
	96	if (!data->trig_mmio) {
	97	pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
	98	return -ENOMEM;
	99	}
	100	return 0;
	101	}
5af50993	102	EXPORT_SYMBOL_GPL(xive_native_populate_irq_data);
243e2511 BH	103
	104	int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
	105	{
	106	s64 rc;
	107
	108	for (;;) {
	109	rc = opal_xive_set_irq_config(hw_irq, target, prio, sw_irq);
	110	if (rc != OPAL_BUSY)
	111	break;
	112	msleep(1);
	113	}
	114	return rc == 0 ? 0 : -ENXIO;
	115	}
5af50993 BH	116	EXPORT_SYMBOL_GPL(xive_native_configure_irq);
5af50993 BH	117
243e2511 BH	118
	119	/* This can be called multiple time to change a queue configuration */
	120	int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
	121	__be32 *qpage, u32 order, bool can_escalate)
	122	{
	123	s64 rc = 0;
	124	__be64 qeoi_page_be;
	125	__be32 esc_irq_be;
	126	u64 flags, qpage_phys;
	127
	128	/* If there's an actual queue page, clean it */
	129	if (order) {
	130	if (WARN_ON(!qpage))
	131	return -EINVAL;
	132	qpage_phys = __pa(qpage);
	133	} else
	134	qpage_phys = 0;
	135
	136	/* Initialize the rest of the fields */
	137	q->msk = order ? ((1u << (order - 2)) - 1) : 0;
	138	q->idx = 0;
	139	q->toggle = 0;
	140
	141	rc = opal_xive_get_queue_info(vp_id, prio, NULL, NULL,
	142	&qeoi_page_be,
	143	&esc_irq_be,
	144	NULL);
	145	if (rc) {
	146	pr_err("Error %lld getting queue info prio %d\n", rc, prio);
	147	rc = -EIO;
	148	goto fail;
	149	}
	150	q->eoi_phys = be64_to_cpu(qeoi_page_be);
	151
	152	/* Default flags */
	153	flags = OPAL_XIVE_EQ_ALWAYS_NOTIFY \| OPAL_XIVE_EQ_ENABLED;
	154
	155	/* Escalation needed ? */
	156	if (can_escalate) {
	157	q->esc_irq = be32_to_cpu(esc_irq_be);
	158	flags \|= OPAL_XIVE_EQ_ESCALATE;
	159	}
	160
	161	/* Configure and enable the queue in HW */
	162	for (;;) {
	163	rc = opal_xive_set_queue_info(vp_id, prio, qpage_phys, order, flags);
	164	if (rc != OPAL_BUSY)
	165	break;
	166	msleep(1);
	167	}
	168	if (rc) {
	169	pr_err("Error %lld setting queue for prio %d\n", rc, prio);
	170	rc = -EIO;
	171	} else {
	172	/*
	173	* KVM code requires all of the above to be visible before
	174	* q->qpage is set due to how it manages IPI EOIs
	175	*/
	176	wmb();
	177	q->qpage = qpage;
	178	}
	179	fail:
	180	return rc;
	181	}
5af50993	182	EXPORT_SYMBOL_GPL(xive_native_configure_queue);
243e2511 BH	183
	184	static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
	185	{
	186	s64 rc;
	187
	188	/* Disable the queue in HW */
	189	for (;;) {
	190	rc = opal_xive_set_queue_info(vp_id, prio, 0, 0, 0);
686978b1	191	if (rc != OPAL_BUSY)
243e2511 BH	192	break;
	193	msleep(1);
	194	}
	195	if (rc)
	196	pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
	197	}
	198
	199	void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
	200	{
	201	__xive_native_disable_queue(vp_id, q, prio);
	202	}
5af50993	203	EXPORT_SYMBOL_GPL(xive_native_disable_queue);
243e2511 BH	204
	205	static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
	206	{
	207	struct xive_q *q = &xc->queue[prio];
243e2511 BH	208	__be32 *qpage;
243e2511 BH	209
994ea2f4 CLG	210	qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
	211	if (IS_ERR(qpage))
	212	return PTR_ERR(qpage);
	213
243e2511 BH	214	return xive_native_configure_queue(get_hard_smp_processor_id(cpu),
	215	q, prio, qpage, xive_queue_shift, false);
	216	}
	217
	218	static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio)
	219	{
	220	struct xive_q *q = &xc->queue[prio];
	221	unsigned int alloc_order;
	222
	223	/*
	224	* We use the variant with no iounmap as this is called on exec
	225	* from an IPI and iounmap isn't safe
	226	*/
	227	__xive_native_disable_queue(get_hard_smp_processor_id(cpu), q, prio);
994ea2f4	228	alloc_order = xive_alloc_order(xive_queue_shift);
243e2511 BH	229	free_pages((unsigned long)q->qpage, alloc_order);
	230	q->qpage = NULL;
	231	}
	232
	233	static bool xive_native_match(struct device_node *node)
	234	{
	235	return of_device_is_compatible(node, "ibm,opal-xive-vc");
	236	}
	237
	238	#ifdef CONFIG_SMP
	239	static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc)
	240	{
	241	struct device_node *np;
	242	unsigned int chip_id;
	243	s64 irq;
	244
	245	/* Find the chip ID */
	246	np = of_get_cpu_node(cpu, NULL);
	247	if (np) {
	248	if (of_property_read_u32(np, "ibm,chip-id", &chip_id) < 0)
	249	chip_id = 0;
	250	}
	251
	252	/* Allocate an IPI and populate info about it */
	253	for (;;) {
	254	irq = opal_xive_allocate_irq(chip_id);
	255	if (irq == OPAL_BUSY) {
	256	msleep(1);
	257	continue;
	258	}
	259	if (irq < 0) {
	260	pr_err("Failed to allocate IPI on CPU %d\n", cpu);
	261	return -ENXIO;
	262	}
	263	xc->hw_ipi = irq;
	264	break;
	265	}
	266	return 0;
	267	}
5af50993	268	#endif /* CONFIG_SMP */
243e2511 BH	269
	270	u32 xive_native_alloc_irq(void)
	271	{
	272	s64 rc;
	273
	274	for (;;) {
	275	rc = opal_xive_allocate_irq(OPAL_XIVE_ANY_CHIP);
	276	if (rc != OPAL_BUSY)
	277	break;
	278	msleep(1);
	279	}
	280	if (rc < 0)
	281	return 0;
	282	return rc;
	283	}
5af50993	284	EXPORT_SYMBOL_GPL(xive_native_alloc_irq);
243e2511 BH	285
	286	void xive_native_free_irq(u32 irq)
	287	{
	288	for (;;) {
	289	s64 rc = opal_xive_free_irq(irq);
	290	if (rc != OPAL_BUSY)
	291	break;
	292	msleep(1);
	293	}
	294	}
5af50993	295	EXPORT_SYMBOL_GPL(xive_native_free_irq);
243e2511	296
5af50993	297	#ifdef CONFIG_SMP
243e2511 BH	298	static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc)
	299	{
	300	s64 rc;
	301
	302	/* Free the IPI */
	303	if (!xc->hw_ipi)
	304	return;
	305	for (;;) {
	306	rc = opal_xive_free_irq(xc->hw_ipi);
	307	if (rc == OPAL_BUSY) {
	308	msleep(1);
	309	continue;
	310	}
	311	xc->hw_ipi = 0;
	312	break;
	313	}
	314	}
	315	#endif /* CONFIG_SMP */
	316
	317	static void xive_native_shutdown(void)
	318	{
	319	/* Switch the XIVE to emulation mode */
	320	opal_xive_reset(OPAL_XIVE_MODE_EMU);
	321	}
	322
	323	/*
	324	* Perform an "ack" cycle on the current thread, thus
	325	* grabbing the pending active priorities and updating
	326	* the CPPR to the most favored one.
	327	*/
	328	static void xive_native_update_pending(struct xive_cpu *xc)
	329	{
	330	u8 he, cppr;
	331	u16 ack;
	332
	333	/* Perform the acknowledge hypervisor to register cycle */
	334	ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_HV_REG));
	335
	336	/* Synchronize subsequent queue accesses */
	337	mb();
	338
	339	/*
	340	* Grab the CPPR and the "HE" field which indicates the source
	341	* of the hypervisor interrupt (if any)
	342	*/
	343	cppr = ack & 0xff;
	344	he = GETFIELD(TM_QW3_NSR_HE, (ack >> 8));
	345	switch(he) {
	346	case TM_QW3_NSR_HE_NONE: /* Nothing to see here */
	347	break;
	348	case TM_QW3_NSR_HE_PHYS: /* Physical thread interrupt */
	349	if (cppr == 0xff)
	350	return;
	351	/* Mark the priority pending */
	352	xc->pending_prio \|= 1 << cppr;
	353
	354	/*
	355	* A new interrupt should never have a CPPR less favored
	356	* than our current one.
	357	*/
	358	if (cppr >= xc->cppr)
	359	pr_err("CPU %d odd ack CPPR, got %d at %d\n",
	360	smp_processor_id(), cppr, xc->cppr);
	361
362	/* Update our idea of what the CPPR is */
363	xc->cppr = cppr;
364	break;
365	case TM_QW3_NSR_HE_POOL: /* HV Pool interrupt (unused) */
366	case TM_QW3_NSR_HE_LSI: /* Legacy FW LSI (unused) */
367	pr_err("CPU %d got unexpected interrupt type HE=%d\n",
368	smp_processor_id(), he);
369	return;
370	}
371	}
372
373	static void xive_native_eoi(u32 hw_irq)
374	{
375	/*
376	* Not normally used except if specific interrupts need
377	* a workaround on EOI.
378	*/
379	opal_int_eoi(hw_irq);
380	}
381
382	static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
383	{
384	s64 rc;
385	u32 vp;
386	__be64 vp_cam_be;
387	u64 vp_cam;
388
389	if (xive_pool_vps == XIVE_INVALID_VP)
390	return;
391
392	/* Enable the pool VP */
5af50993	393	vp = xive_pool_vps + cpu;
243e2511 BH	394	pr_debug("CPU %d setting up pool VP 0x%x\n", cpu, vp);
	395	for (;;) {
	396	rc = opal_xive_set_vp_info(vp, OPAL_XIVE_VP_ENABLED, 0);
	397	if (rc != OPAL_BUSY)
	398	break;
	399	msleep(1);
	400	}
	401	if (rc) {
	402	pr_err("Failed to enable pool VP on CPU %d\n", cpu);
	403	return;
	404	}
	405
	406	/* Grab it's CAM value */
	407	rc = opal_xive_get_vp_info(vp, NULL, &vp_cam_be, NULL, NULL);
	408	if (rc) {
	409	pr_err("Failed to get pool VP info CPU %d\n", cpu);
	410	return;
	411	}
	412	vp_cam = be64_to_cpu(vp_cam_be);
	413
	414	pr_debug("VP CAM = %llx\n", vp_cam);
	415
	416	/* Push it on the CPU (set LSMFB to 0xff to skip backlog scan) */
	417	pr_debug("(Old HW value: %08x)\n",
	418	in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
	419	out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD0, 0xff);
	420	out_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2,
	421	TM_QW2W2_VP \| vp_cam);
	422	pr_debug("(New HW value: %08x)\n",
	423	in_be32(xive_tima + TM_QW2_HV_POOL + TM_WORD2));
	424	}
	425
	426	static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
	427	{
	428	s64 rc;
	429	u32 vp;
	430
	431	if (xive_pool_vps == XIVE_INVALID_VP)
	432	return;
	433
	434	/* Pull the pool VP from the CPU */
	435	in_be64(xive_tima + TM_SPC_PULL_POOL_CTX);
	436
	437	/* Disable it */
5af50993	438	vp = xive_pool_vps + cpu;
243e2511 BH	439	for (;;) {
	440	rc = opal_xive_set_vp_info(vp, 0, 0);
	441	if (rc != OPAL_BUSY)
	442	break;
	443	msleep(1);
	444	}
	445	}
	446
5af50993	447	void xive_native_sync_source(u32 hw_irq)
243e2511 BH	448	{
	449	opal_xive_sync(XIVE_SYNC_EAS, hw_irq);
	450	}
5af50993	451	EXPORT_SYMBOL_GPL(xive_native_sync_source);
243e2511 BH	452
	453	static const struct xive_ops xive_native_ops = {
	454	.populate_irq_data = xive_native_populate_irq_data,
	455	.configure_irq = xive_native_configure_irq,
	456	.setup_queue = xive_native_setup_queue,
	457	.cleanup_queue = xive_native_cleanup_queue,
	458	.match = xive_native_match,
	459	.shutdown = xive_native_shutdown,
	460	.update_pending = xive_native_update_pending,
	461	.eoi = xive_native_eoi,
	462	.setup_cpu = xive_native_setup_cpu,
	463	.teardown_cpu = xive_native_teardown_cpu,
	464	.sync_source = xive_native_sync_source,
	465	#ifdef CONFIG_SMP
	466	.get_ipi = xive_native_get_ipi,
	467	.put_ipi = xive_native_put_ipi,
	468	#endif /* CONFIG_SMP */
	469	.name = "native",
	470	};
	471
	472	static bool xive_parse_provisioning(struct device_node *np)
	473	{
	474	int rc;
	475
	476	if (of_property_read_u32(np, "ibm,xive-provision-page-size",
	477	&xive_provision_size) < 0)
	478	return true;
	479	rc = of_property_count_elems_of_size(np, "ibm,xive-provision-chips", 4);
	480	if (rc < 0) {
	481	pr_err("Error %d getting provision chips array\n", rc);
	482	return false;
	483	}
	484	xive_provision_chip_count = rc;
	485	if (rc == 0)
	486	return true;
	487
	488	xive_provision_chips = kzalloc(4 * xive_provision_chip_count,
	489	GFP_KERNEL);
	490	if (WARN_ON(!xive_provision_chips))
	491	return false;
	492
	493	rc = of_property_read_u32_array(np, "ibm,xive-provision-chips",
	494	xive_provision_chips,
	495	xive_provision_chip_count);
	496	if (rc < 0) {
	497	pr_err("Error %d reading provision chips array\n", rc);
	498	return false;
	499	}
	500
	501	xive_provision_cache = kmem_cache_create("xive-provision",
	502	xive_provision_size,
	503	xive_provision_size,
	504	0, NULL);
	505	if (!xive_provision_cache) {
	506	pr_err("Failed to allocate provision cache\n");
	507	return false;
	508	}
	509	return true;
	510	}
	511
5af50993 BH	512	static void xive_native_setup_pools(void)
	513	{
	514	/* Allocate a pool big enough */
9b130ad5	515	pr_debug("XIVE: Allocating VP block for pool size %u\n", nr_cpu_ids);
5af50993 BH	516
	517	xive_pool_vps = xive_native_alloc_vp_block(nr_cpu_ids);
	518	if (WARN_ON(xive_pool_vps == XIVE_INVALID_VP))
	519	pr_err("XIVE: Failed to allocate pool VP, KVM might not function\n");
	520
9b130ad5	521	pr_debug("XIVE: Pool VPs allocated at 0x%x for %u max CPUs\n",
5af50993 BH	522	xive_pool_vps, nr_cpu_ids);
	523	}
	524
243e2511 BH	525	u32 xive_native_default_eq_shift(void)
	526	{
	527	return xive_queue_shift;
	528	}
5af50993	529	EXPORT_SYMBOL_GPL(xive_native_default_eq_shift);
243e2511	530
df4c7983	531	bool __init xive_native_init(void)
243e2511 BH	532	{
	533	struct device_node *np;
	534	struct resource r;
	535	void __iomem *tima;
	536	struct property *prop;
	537	u8 max_prio = 7;
	538	const __be32 *p;
5af50993	539	u32 val, cpu;
243e2511 BH	540	s64 rc;
	541
	542	if (xive_cmdline_disabled)
	543	return false;
	544
	545	pr_devel("xive_native_init()\n");
	546	np = of_find_compatible_node(NULL, NULL, "ibm,opal-xive-pe");
	547	if (!np) {
	548	pr_devel("not found !\n");
	549	return false;
	550	}
b7c670d6	551	pr_devel("Found %pOF\n", np);
243e2511 BH	552
	553	/* Resource 1 is HV window */
	554	if (of_address_to_resource(np, 1, &r)) {
	555	pr_err("Failed to get thread mgmnt area resource\n");
	556	return false;
	557	}
	558	tima = ioremap(r.start, resource_size(&r));
	559	if (!tima) {
	560	pr_err("Failed to map thread mgmnt area\n");
	561	return false;
	562	}
	563
	564	/* Read number of priorities */
	565	if (of_property_read_u32(np, "ibm,xive-#priorities", &val) == 0)
	566	max_prio = val - 1;
	567
	568	/* Iterate the EQ sizes and pick one */
	569	of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, p, val) {
	570	xive_queue_shift = val;
	571	if (val == PAGE_SHIFT)
	572	break;
	573	}
	574
bf4159da BH	575	/* Do we support single escalation */
	576	if (of_get_property(np, "single-escalation-support", NULL) != NULL)
	577	xive_has_single_esc = true;
	578
5af50993 BH	579	/* Configure Thread Management areas for KVM */
	580	for_each_possible_cpu(cpu)
	581	kvmppc_set_xive_tima(cpu, r.start, tima);
	582
	583	/* Grab size of provisionning pages */
243e2511 BH	584	xive_parse_provisioning(np);
	585
	586	/* Switch the XIVE to exploitation mode */
	587	rc = opal_xive_reset(OPAL_XIVE_MODE_EXPL);
	588	if (rc) {
	589	pr_err("Switch to exploitation mode failed with error %lld\n", rc);
	590	return false;
	591	}
	592
5af50993 BH	593	/* Setup some dummy HV pool VPs */
	594	xive_native_setup_pools();
	595
243e2511 BH	596	/* Initialize XIVE core with our backend */
	597	if (!xive_core_init(&xive_native_ops, tima, TM_QW3_HV_PHYS,
	598	max_prio)) {
	599	opal_xive_reset(OPAL_XIVE_MODE_EMU);
	600	return false;
	601	}
	602	pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
	603	return true;
	604	}
	605
	606	static bool xive_native_provision_pages(void)
	607	{
	608	u32 i;
	609	void *p;
	610
	611	for (i = 0; i < xive_provision_chip_count; i++) {
	612	u32 chip = xive_provision_chips[i];
	613
	614	/*
	615	* XXX TODO: Try to make the allocation local to the node where
	616	* the chip resides.
	617	*/
	618	p = kmem_cache_alloc(xive_provision_cache, GFP_KERNEL);
	619	if (!p) {
	620	pr_err("Failed to allocate provisioning page\n");
	621	return false;
	622	}
	623	opal_xive_donate_page(chip, __pa(p));
	624	}
	625	return true;
	626	}
	627
	628	u32 xive_native_alloc_vp_block(u32 max_vcpus)
	629	{
	630	s64 rc;
	631	u32 order;
	632
	633	order = fls(max_vcpus) - 1;
	634	if (max_vcpus > (1 << order))
	635	order++;
	636
89d8bb16 BH	637	pr_debug("VP block alloc, for max VCPUs %d use order %d\n",
89d8bb16 BH	638	max_vcpus, order);
243e2511 BH	639
	640	for (;;) {
	641	rc = opal_xive_alloc_vp_block(order);
	642	switch (rc) {
	643	case OPAL_BUSY:
	644	msleep(1);
	645	break;
	646	case OPAL_XIVE_PROVISIONING:
	647	if (!xive_native_provision_pages())
	648	return XIVE_INVALID_VP;
	649	break;
	650	default:
	651	if (rc < 0) {
	652	pr_err("OPAL failed to allocate VCPUs order %d, err %lld\n",
	653	order, rc);
	654	return XIVE_INVALID_VP;
	655	}
	656	return rc;
	657	}
	658	}
	659	}
	660	EXPORT_SYMBOL_GPL(xive_native_alloc_vp_block);
	661
	662	void xive_native_free_vp_block(u32 vp_base)
	663	{
	664	s64 rc;
	665
	666	if (vp_base == XIVE_INVALID_VP)
	667	return;
	668
	669	rc = opal_xive_free_vp_block(vp_base);
	670	if (rc < 0)
	671	pr_warn("OPAL error %lld freeing VP block\n", rc);
	672	}
	673	EXPORT_SYMBOL_GPL(xive_native_free_vp_block);
5af50993	674
bf4159da	675	int xive_native_enable_vp(u32 vp_id, bool single_escalation)
5af50993 BH	676	{
5af50993 BH	677	s64 rc;
bf4159da	678	u64 flags = OPAL_XIVE_VP_ENABLED;
5af50993	679
bf4159da BH	680	if (single_escalation)
bf4159da BH	681	flags \|= OPAL_XIVE_VP_SINGLE_ESCALATION;
5af50993	682	for (;;) {
bf4159da	683	rc = opal_xive_set_vp_info(vp_id, flags, 0);
5af50993 BH	684	if (rc != OPAL_BUSY)
	685	break;
	686	msleep(1);
	687	}
	688	return rc ? -EIO : 0;
	689	}
	690	EXPORT_SYMBOL_GPL(xive_native_enable_vp);
	691
	692	int xive_native_disable_vp(u32 vp_id)
	693	{
	694	s64 rc;
	695
	696	for (;;) {
	697	rc = opal_xive_set_vp_info(vp_id, 0, 0);
	698	if (rc != OPAL_BUSY)
	699	break;
	700	msleep(1);
	701	}
	702	return rc ? -EIO : 0;
	703	}
	704	EXPORT_SYMBOL_GPL(xive_native_disable_vp);
	705
	706	int xive_native_get_vp_info(u32 vp_id, u32 out_cam_id, u32 out_chip_id)
	707	{
	708	__be64 vp_cam_be;
	709	__be32 vp_chip_id_be;
	710	s64 rc;
	711
	712	rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
	713	if (rc)
	714	return -EIO;
	715	*out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
	716	*out_chip_id = be32_to_cpu(vp_chip_id_be);
	717
	718	return 0;
	719	}
	720	EXPORT_SYMBOL_GPL(xive_native_get_vp_info);
bf4159da BH	721
	722	bool xive_native_has_single_escalation(void)
	723	{
	724	return xive_has_single_esc;
	725	}
	726	EXPORT_SYMBOL_GPL(xive_native_has_single_escalation);