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e58923ed DG |
1 | /* |
2 | * arch/powerpc/sysdev/uic.c | |
3 | * | |
4 | * IBM PowerPC 4xx Universal Interrupt Controller | |
5 | * | |
6 | * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/reboot.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/stddef.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/signal.h> | |
21 | #include <linux/sysdev.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <linux/irq.h> | |
26 | #include <linux/interrupt.h> | |
868afce2 | 27 | #include <linux/kernel_stat.h> |
e58923ed DG |
28 | #include <asm/irq.h> |
29 | #include <asm/io.h> | |
30 | #include <asm/prom.h> | |
31 | #include <asm/dcr.h> | |
32 | ||
33 | #define NR_UIC_INTS 32 | |
34 | ||
35 | #define UIC_SR 0x0 | |
36 | #define UIC_ER 0x2 | |
37 | #define UIC_CR 0x3 | |
38 | #define UIC_PR 0x4 | |
39 | #define UIC_TR 0x5 | |
40 | #define UIC_MSR 0x6 | |
41 | #define UIC_VR 0x7 | |
42 | #define UIC_VCR 0x8 | |
43 | ||
44 | #define uic_irq_to_hw(virq) (irq_map[virq].hwirq) | |
45 | ||
46 | struct uic *primary_uic; | |
47 | ||
48 | struct uic { | |
49 | int index; | |
50 | int dcrbase; | |
51 | ||
52 | spinlock_t lock; | |
53 | ||
54 | /* The remapper for this UIC */ | |
55 | struct irq_host *irqhost; | |
e58923ed DG |
56 | }; |
57 | ||
42a07ae2 | 58 | static void uic_unmask_irq(struct irq_data *d) |
e58923ed | 59 | { |
42a07ae2 LB |
60 | struct uic *uic = irq_data_get_irq_chip_data(d); |
61 | unsigned int src = uic_irq_to_hw(d->irq); | |
e58923ed | 62 | unsigned long flags; |
c8090563 | 63 | u32 er, sr; |
e58923ed | 64 | |
c8090563 | 65 | sr = 1 << (31-src); |
e58923ed | 66 | spin_lock_irqsave(&uic->lock, flags); |
c8090563 | 67 | /* ack level-triggered interrupts here */ |
1ac06cda | 68 | if (irqd_is_level_type(d)) |
c8090563 | 69 | mtdcr(uic->dcrbase + UIC_SR, sr); |
e58923ed | 70 | er = mfdcr(uic->dcrbase + UIC_ER); |
c8090563 | 71 | er |= sr; |
e58923ed DG |
72 | mtdcr(uic->dcrbase + UIC_ER, er); |
73 | spin_unlock_irqrestore(&uic->lock, flags); | |
74 | } | |
75 | ||
42a07ae2 | 76 | static void uic_mask_irq(struct irq_data *d) |
e58923ed | 77 | { |
42a07ae2 LB |
78 | struct uic *uic = irq_data_get_irq_chip_data(d); |
79 | unsigned int src = uic_irq_to_hw(d->irq); | |
e58923ed DG |
80 | unsigned long flags; |
81 | u32 er; | |
82 | ||
83 | spin_lock_irqsave(&uic->lock, flags); | |
84 | er = mfdcr(uic->dcrbase + UIC_ER); | |
85 | er &= ~(1 << (31 - src)); | |
86 | mtdcr(uic->dcrbase + UIC_ER, er); | |
87 | spin_unlock_irqrestore(&uic->lock, flags); | |
88 | } | |
89 | ||
42a07ae2 | 90 | static void uic_ack_irq(struct irq_data *d) |
e58923ed | 91 | { |
42a07ae2 LB |
92 | struct uic *uic = irq_data_get_irq_chip_data(d); |
93 | unsigned int src = uic_irq_to_hw(d->irq); | |
e58923ed DG |
94 | unsigned long flags; |
95 | ||
96 | spin_lock_irqsave(&uic->lock, flags); | |
97 | mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src)); | |
98 | spin_unlock_irqrestore(&uic->lock, flags); | |
99 | } | |
100 | ||
42a07ae2 | 101 | static void uic_mask_ack_irq(struct irq_data *d) |
b8b799a4 | 102 | { |
42a07ae2 LB |
103 | struct uic *uic = irq_data_get_irq_chip_data(d); |
104 | unsigned int src = uic_irq_to_hw(d->irq); | |
b8b799a4 VB |
105 | unsigned long flags; |
106 | u32 er, sr; | |
107 | ||
108 | sr = 1 << (31-src); | |
109 | spin_lock_irqsave(&uic->lock, flags); | |
110 | er = mfdcr(uic->dcrbase + UIC_ER); | |
111 | er &= ~sr; | |
112 | mtdcr(uic->dcrbase + UIC_ER, er); | |
c8090563 VB |
113 | /* On the UIC, acking (i.e. clearing the SR bit) |
114 | * a level irq will have no effect if the interrupt | |
115 | * is still asserted by the device, even if | |
116 | * the interrupt is already masked. Therefore | |
117 | * we only ack the egde interrupts here, while | |
118 | * level interrupts are ack'ed after the actual | |
119 | * isr call in the uic_unmask_irq() | |
120 | */ | |
1ac06cda | 121 | if (!irqd_is_level_type(d)) |
c8090563 | 122 | mtdcr(uic->dcrbase + UIC_SR, sr); |
b8b799a4 VB |
123 | spin_unlock_irqrestore(&uic->lock, flags); |
124 | } | |
125 | ||
42a07ae2 | 126 | static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
e58923ed | 127 | { |
42a07ae2 LB |
128 | struct uic *uic = irq_data_get_irq_chip_data(d); |
129 | unsigned int src = uic_irq_to_hw(d->irq); | |
e58923ed DG |
130 | unsigned long flags; |
131 | int trigger, polarity; | |
132 | u32 tr, pr, mask; | |
133 | ||
134 | switch (flow_type & IRQ_TYPE_SENSE_MASK) { | |
135 | case IRQ_TYPE_NONE: | |
42a07ae2 | 136 | uic_mask_irq(d); |
e58923ed DG |
137 | return 0; |
138 | ||
139 | case IRQ_TYPE_EDGE_RISING: | |
140 | trigger = 1; polarity = 1; | |
141 | break; | |
142 | case IRQ_TYPE_EDGE_FALLING: | |
143 | trigger = 1; polarity = 0; | |
144 | break; | |
145 | case IRQ_TYPE_LEVEL_HIGH: | |
146 | trigger = 0; polarity = 1; | |
147 | break; | |
148 | case IRQ_TYPE_LEVEL_LOW: | |
149 | trigger = 0; polarity = 0; | |
150 | break; | |
151 | default: | |
152 | return -EINVAL; | |
153 | } | |
154 | ||
155 | mask = ~(1 << (31 - src)); | |
156 | ||
157 | spin_lock_irqsave(&uic->lock, flags); | |
158 | tr = mfdcr(uic->dcrbase + UIC_TR); | |
159 | pr = mfdcr(uic->dcrbase + UIC_PR); | |
160 | tr = (tr & mask) | (trigger << (31-src)); | |
161 | pr = (pr & mask) | (polarity << (31-src)); | |
162 | ||
163 | mtdcr(uic->dcrbase + UIC_PR, pr); | |
164 | mtdcr(uic->dcrbase + UIC_TR, tr); | |
165 | ||
e58923ed DG |
166 | spin_unlock_irqrestore(&uic->lock, flags); |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
171 | static struct irq_chip uic_irq_chip = { | |
fc380c0c | 172 | .name = "UIC", |
42a07ae2 LB |
173 | .irq_unmask = uic_unmask_irq, |
174 | .irq_mask = uic_mask_irq, | |
175 | .irq_mask_ack = uic_mask_ack_irq, | |
176 | .irq_ack = uic_ack_irq, | |
177 | .irq_set_type = uic_set_irq_type, | |
e58923ed DG |
178 | }; |
179 | ||
e58923ed DG |
180 | static int uic_host_map(struct irq_host *h, unsigned int virq, |
181 | irq_hw_number_t hw) | |
182 | { | |
183 | struct uic *uic = h->host_data; | |
184 | ||
ec775d0e | 185 | irq_set_chip_data(virq, uic); |
e58923ed DG |
186 | /* Despite the name, handle_level_irq() works for both level |
187 | * and edge irqs on UIC. FIXME: check this is correct */ | |
ec775d0e | 188 | irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); |
e58923ed DG |
189 | |
190 | /* Set default irq type */ | |
ec775d0e | 191 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
e58923ed DG |
192 | |
193 | return 0; | |
194 | } | |
195 | ||
196 | static int uic_host_xlate(struct irq_host *h, struct device_node *ct, | |
40d50cf7 | 197 | const u32 *intspec, unsigned int intsize, |
e58923ed DG |
198 | irq_hw_number_t *out_hwirq, unsigned int *out_type) |
199 | ||
200 | { | |
201 | /* UIC intspecs must have 2 cells */ | |
202 | BUG_ON(intsize != 2); | |
203 | *out_hwirq = intspec[0]; | |
204 | *out_type = intspec[1]; | |
205 | return 0; | |
206 | } | |
207 | ||
208 | static struct irq_host_ops uic_host_ops = { | |
e58923ed DG |
209 | .map = uic_host_map, |
210 | .xlate = uic_host_xlate, | |
211 | }; | |
212 | ||
5aac48dc | 213 | void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) |
e58923ed | 214 | { |
ec775d0e | 215 | struct irq_chip *chip = irq_desc_get_chip(desc); |
1ac06cda | 216 | struct irq_data *idata = irq_desc_get_irq_data(desc); |
ec775d0e | 217 | struct uic *uic = irq_get_handler_data(virq); |
e58923ed DG |
218 | u32 msr; |
219 | int src; | |
220 | int subvirq; | |
221 | ||
239007b8 | 222 | raw_spin_lock(&desc->lock); |
1ac06cda TG |
223 | if (irqd_is_level_type(idata)) |
224 | chip->irq_mask(idata); | |
5aac48dc | 225 | else |
1ac06cda | 226 | chip->irq_mask_ack(idata); |
239007b8 | 227 | raw_spin_unlock(&desc->lock); |
5aac48dc | 228 | |
e58923ed | 229 | msr = mfdcr(uic->dcrbase + UIC_MSR); |
553fdff6 | 230 | if (!msr) /* spurious interrupt */ |
5aac48dc | 231 | goto uic_irq_ret; |
553fdff6 | 232 | |
e58923ed DG |
233 | src = 32 - ffs(msr); |
234 | ||
235 | subvirq = irq_linear_revmap(uic->irqhost, src); | |
236 | generic_handle_irq(subvirq); | |
237 | ||
5aac48dc | 238 | uic_irq_ret: |
239007b8 | 239 | raw_spin_lock(&desc->lock); |
1ac06cda TG |
240 | if (irqd_is_level_type(idata)) |
241 | chip->irq_ack(idata); | |
242 | if (!irqd_irq_disabled(idata) && chip->irq_unmask) | |
243 | chip->irq_unmask(idata); | |
239007b8 | 244 | raw_spin_unlock(&desc->lock); |
e58923ed DG |
245 | } |
246 | ||
247 | static struct uic * __init uic_init_one(struct device_node *node) | |
248 | { | |
249 | struct uic *uic; | |
250 | const u32 *indexp, *dcrreg; | |
251 | int len; | |
252 | ||
55b61fec | 253 | BUG_ON(! of_device_is_compatible(node, "ibm,uic")); |
e58923ed | 254 | |
ea96025a | 255 | uic = kzalloc(sizeof(*uic), GFP_KERNEL); |
e58923ed DG |
256 | if (! uic) |
257 | return NULL; /* FIXME: panic? */ | |
258 | ||
e58923ed | 259 | spin_lock_init(&uic->lock); |
12d371a6 | 260 | indexp = of_get_property(node, "cell-index", &len); |
e58923ed DG |
261 | if (!indexp || (len != sizeof(u32))) { |
262 | printk(KERN_ERR "uic: Device node %s has missing or invalid " | |
263 | "cell-index property\n", node->full_name); | |
264 | return NULL; | |
265 | } | |
266 | uic->index = *indexp; | |
267 | ||
12d371a6 | 268 | dcrreg = of_get_property(node, "dcr-reg", &len); |
e58923ed DG |
269 | if (!dcrreg || (len != 2*sizeof(u32))) { |
270 | printk(KERN_ERR "uic: Device node %s has missing or invalid " | |
271 | "dcr-reg property\n", node->full_name); | |
272 | return NULL; | |
273 | } | |
274 | uic->dcrbase = *dcrreg; | |
275 | ||
19fc65b5 | 276 | uic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, |
52964f87 | 277 | NR_UIC_INTS, &uic_host_ops, -1); |
19fc65b5 | 278 | if (! uic->irqhost) |
e58923ed | 279 | return NULL; /* FIXME: panic? */ |
e58923ed DG |
280 | |
281 | uic->irqhost->host_data = uic; | |
282 | ||
283 | /* Start with all interrupts disabled, level and non-critical */ | |
284 | mtdcr(uic->dcrbase + UIC_ER, 0); | |
285 | mtdcr(uic->dcrbase + UIC_CR, 0); | |
286 | mtdcr(uic->dcrbase + UIC_TR, 0); | |
287 | /* Clear any pending interrupts, in case the firmware left some */ | |
288 | mtdcr(uic->dcrbase + UIC_SR, 0xffffffff); | |
289 | ||
290 | printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index, | |
291 | NR_UIC_INTS, uic->dcrbase); | |
292 | ||
293 | return uic; | |
294 | } | |
295 | ||
296 | void __init uic_init_tree(void) | |
297 | { | |
298 | struct device_node *np; | |
299 | struct uic *uic; | |
300 | const u32 *interrupts; | |
301 | ||
302 | /* First locate and initialize the top-level UIC */ | |
26cb7d8b | 303 | for_each_compatible_node(np, NULL, "ibm,uic") { |
12d371a6 | 304 | interrupts = of_get_property(np, "interrupts", NULL); |
26cb7d8b | 305 | if (!interrupts) |
e58923ed | 306 | break; |
e58923ed DG |
307 | } |
308 | ||
309 | BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the | |
310 | * top-level interrupt controller */ | |
311 | primary_uic = uic_init_one(np); | |
26cb7d8b | 312 | if (!primary_uic) |
e58923ed DG |
313 | panic("Unable to initialize primary UIC %s\n", np->full_name); |
314 | ||
315 | irq_set_default_host(primary_uic->irqhost); | |
316 | of_node_put(np); | |
317 | ||
318 | /* The scan again for cascaded UICs */ | |
26cb7d8b | 319 | for_each_compatible_node(np, NULL, "ibm,uic") { |
12d371a6 | 320 | interrupts = of_get_property(np, "interrupts", NULL); |
e58923ed DG |
321 | if (interrupts) { |
322 | /* Secondary UIC */ | |
323 | int cascade_virq; | |
e58923ed DG |
324 | |
325 | uic = uic_init_one(np); | |
326 | if (! uic) | |
327 | panic("Unable to initialize a secondary UIC %s\n", | |
328 | np->full_name); | |
329 | ||
330 | cascade_virq = irq_of_parse_and_map(np, 0); | |
331 | ||
ec775d0e TG |
332 | irq_set_handler_data(cascade_virq, uic); |
333 | irq_set_chained_handler(cascade_virq, uic_irq_cascade); | |
e58923ed DG |
334 | |
335 | /* FIXME: setup critical cascade?? */ | |
336 | } | |
e58923ed DG |
337 | } |
338 | } | |
339 | ||
340 | /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ | |
341 | unsigned int uic_get_irq(void) | |
342 | { | |
343 | u32 msr; | |
344 | int src; | |
345 | ||
346 | BUG_ON(! primary_uic); | |
347 | ||
348 | msr = mfdcr(primary_uic->dcrbase + UIC_MSR); | |
349 | src = 32 - ffs(msr); | |
350 | ||
351 | return irq_linear_revmap(primary_uic->irqhost, src); | |
352 | } |