[linux-block.git] / arch / powerpc / sysdev / qe_lib / gpio.c

/*
 * QUICC Engine GPIOs
 *
 * Copyright (c) MontaVista Software, Inc. 2008.
 *
 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <asm/qe.h>

struct qe_gpio_chip {
	struct of_mm_gpio_chip mm_gc;
	spinlock_t lock;

	unsigned long pin_flags[QE_PIO_PINS];
#define QE_PIN_REQUESTED 0

	/* shadowed data register to clear/set bits safely */
	u32 cpdata;

	/* saved_regs used to restore dedicated functions */
	struct qe_pio_regs saved_regs;
};

static inline struct qe_gpio_chip *
to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
{
	return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
}

static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
{
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;

	qe_gc->cpdata = in_be32(&regs->cpdata);
	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
}

static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	return in_be32(&regs->cpdata) & pin_mask;
}

static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	unsigned long flags;
	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (val)
		qe_gc->cpdata |= pin_mask;
	else
		qe_gc->cpdata &= ~pin_mask;

	out_be32(&regs->cpdata, qe_gc->cpdata);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}

static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	return 0;
}

static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	unsigned long flags;

	qe_gpio_set(gc, gpio, val);

	spin_lock_irqsave(&qe_gc->lock, flags);

	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	return 0;
}

struct qe_pin {
	/*
	 * The qe_gpio_chip name is unfortunate, we should change that to
	 * something like qe_pio_controller. Someday.
	 */
	struct qe_gpio_chip *controller;
	int num;
};

/**
 * qe_pin_request - Request a QE pin
 * @np:		device node to get a pin from
 * @index:	index of a pin in the device tree
 * Context:	non-atomic
 *
 * This function return qe_pin so that you could use it with the rest of
 * the QE Pin Multiplexing API.
 */
struct qe_pin *qe_pin_request(struct device_node *np, int index)
{
	struct qe_pin *qe_pin;
	struct device_node *gpio_np;
	struct gpio_chip *gc;
	struct of_mm_gpio_chip *mm_gc;
	struct qe_gpio_chip *qe_gc;
	int err;
	int size;
	const void *gpio_spec;
	const u32 *gpio_cells;
	unsigned long flags;

	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
	if (!qe_pin) {
		pr_debug("%s: can't allocate memory\n", __func__);
		return ERR_PTR(-ENOMEM);
	}

	err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
					  &gpio_np, &gpio_spec);
	if (err) {
		pr_debug("%s: can't parse gpios property\n", __func__);
		goto err0;
	}

	if (!of_device_is_compatible(gpio_np, "fsl,mpc8323-qe-pario-bank")) {
		pr_debug("%s: tried to get a non-qe pin\n", __func__);
		err = -EINVAL;
		goto err1;
	}

	gc = of_node_to_gpiochip(gpio_np);
	if (!gc) {
		pr_debug("%s: gpio controller %s isn't registered\n",
			 np->full_name, gpio_np->full_name);
		err = -ENODEV;
		goto err1;
	}

	gpio_cells = of_get_property(gpio_np, "#gpio-cells", &size);
	if (!gpio_cells || size != sizeof(*gpio_cells) ||
			*gpio_cells != gc->of_gpio_n_cells) {
		pr_debug("%s: wrong #gpio-cells for %s\n",
			 np->full_name, gpio_np->full_name);
		err = -EINVAL;
		goto err1;
	}

	err = gc->of_xlate(gc, np, gpio_spec, NULL);
	if (err < 0)
		goto err1;

	mm_gc = to_of_mm_gpio_chip(gc);
	qe_gc = to_qe_gpio_chip(mm_gc);

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
		qe_pin->controller = qe_gc;
		qe_pin->num = err;
		err = 0;
	} else {
		err = -EBUSY;
	}

	spin_unlock_irqrestore(&qe_gc->lock, flags);

	if (!err)
		return qe_pin;
err1:
	of_node_put(gpio_np);
err0:
	kfree(qe_pin);
	pr_debug("%s failed with status %d\n", __func__, err);
	return ERR_PTR(err);
}
EXPORT_SYMBOL(qe_pin_request);

/**
 * qe_pin_free - Free a pin
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function frees the qe_pin structure and makes a pin available
 * for further qe_pin_request() calls.
 */
void qe_pin_free(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	unsigned long flags;
	const int pin = qe_pin->num;

	spin_lock_irqsave(&qe_gc->lock, flags);
	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
	spin_unlock_irqrestore(&qe_gc->lock, flags);

	kfree(qe_pin);
}
EXPORT_SYMBOL(qe_pin_free);

/**
 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function resets a pin to a dedicated peripheral function that
 * has been set up by the firmware.
 */
void qe_pin_set_dedicated(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
	int pin = qe_pin->num;
	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	if (second_reg) {
		clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
		clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
	} else {
		clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
		clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
	}

	if (sregs->cpdata & mask1)
		qe_gc->cpdata |= mask1;
	else
		qe_gc->cpdata &= ~mask1;

	out_be32(&regs->cpdata, qe_gc->cpdata);
	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}
EXPORT_SYMBOL(qe_pin_set_dedicated);

/**
 * qe_pin_set_gpio - Set a pin to the GPIO mode
 * @qe_pin:	pointer to the qe_pin structure
 * Context:	any
 *
 * This function sets a pin to the GPIO mode.
 */
void qe_pin_set_gpio(struct qe_pin *qe_pin)
{
	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	unsigned long flags;

	spin_lock_irqsave(&qe_gc->lock, flags);

	/* Let's make it input by default, GPIO API is able to change that. */
	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);

	spin_unlock_irqrestore(&qe_gc->lock, flags);
}
EXPORT_SYMBOL(qe_pin_set_gpio);

static int __init qe_add_gpiochips(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
		int ret;
		struct qe_gpio_chip *qe_gc;
		struct of_mm_gpio_chip *mm_gc;
		struct gpio_chip *gc;

		qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
		if (!qe_gc) {
			ret = -ENOMEM;
			goto err;
		}

		spin_lock_init(&qe_gc->lock);

		mm_gc = &qe_gc->mm_gc;
		gc = &mm_gc->gc;

		mm_gc->save_regs = qe_gpio_save_regs;
		gc->ngpio = QE_PIO_PINS;
		gc->direction_input = qe_gpio_dir_in;
		gc->direction_output = qe_gpio_dir_out;
		gc->get = qe_gpio_get;
		gc->set = qe_gpio_set;

		ret = of_mm_gpiochip_add(np, mm_gc);
		if (ret)
			goto err;
		continue;
err:
		pr_err("%s: registration failed with status %d\n",
		       np->full_name, ret);
		kfree(qe_gc);
		/* try others anyway */
	}
	return 0;
}
arch_initcall(qe_add_gpiochips);
Commit	Line	Data
32def337 AV	1	/*
	2	* QUICC Engine GPIOs
	3	*
	4	* Copyright (c) MontaVista Software, Inc. 2008.
	5	*
	6	* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
d14b3dd6	15	#include <linux/init.h>
32def337	16	#include <linux/spinlock.h>
1b9e8904	17	#include <linux/err.h>
32def337 AV	18	#include <linux/io.h>
	19	#include <linux/of.h>
	20	#include <linux/of_gpio.h>
	21	#include <linux/gpio.h>
5a0e3ad6	22	#include <linux/slab.h>
66b15db6	23	#include <linux/export.h>
32def337 AV	24	#include <asm/qe.h>
	25
	26	struct qe_gpio_chip {
	27	struct of_mm_gpio_chip mm_gc;
	28	spinlock_t lock;
	29
1b9e8904 AV	30	unsigned long pin_flags[QE_PIO_PINS];
	31	#define QE_PIN_REQUESTED 0
	32
32def337 AV	33	/* shadowed data register to clear/set bits safely */
32def337 AV	34	u32 cpdata;
1b9e8904 AV	35
	36	/* saved_regs used to restore dedicated functions */
	37	struct qe_pio_regs saved_regs;
32def337 AV	38	};
	39
	40	static inline struct qe_gpio_chip *
	41	to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
	42	{
	43	return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
	44	}
	45
	46	static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
	47	{
	48	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	49	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	50
	51	qe_gc->cpdata = in_be32(&regs->cpdata);
1b9e8904 AV	52	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
	53	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
	54	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
	55	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
	56	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
	57	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
32def337 AV	58	}
	59
	60	static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
	61	{
	62	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	63	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	64	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
	65
	66	return in_be32(&regs->cpdata) & pin_mask;
	67	}
	68
	69	static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	70	{
	71	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	72	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	73	struct qe_pio_regs __iomem *regs = mm_gc->regs;
	74	unsigned long flags;
	75	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
	76
	77	spin_lock_irqsave(&qe_gc->lock, flags);
	78
	79	if (val)
	80	qe_gc->cpdata \|= pin_mask;
	81	else
	82	qe_gc->cpdata &= ~pin_mask;
	83
	84	out_be32(&regs->cpdata, qe_gc->cpdata);
	85
	86	spin_unlock_irqrestore(&qe_gc->lock, flags);
	87	}
	88
	89	static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
	90	{
	91	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	92	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	93	unsigned long flags;
	94
	95	spin_lock_irqsave(&qe_gc->lock, flags);
	96
	97	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
	98
	99	spin_unlock_irqrestore(&qe_gc->lock, flags);
	100
	101	return 0;
	102	}
	103
	104	static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	105	{
	106	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	107	struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
	108	unsigned long flags;
	109
1dcd8ffc MB	110	qe_gpio_set(gc, gpio, val);
1dcd8ffc MB	111
32def337 AV	112	spin_lock_irqsave(&qe_gc->lock, flags);
	113
	114	__par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
	115
	116	spin_unlock_irqrestore(&qe_gc->lock, flags);
	117
32def337 AV	118	return 0;
	119	}
	120
1b9e8904 AV	121	struct qe_pin {
	122	/*
	123	* The qe_gpio_chip name is unfortunate, we should change that to
	124	* something like qe_pio_controller. Someday.
	125	*/
	126	struct qe_gpio_chip *controller;
	127	int num;
	128	};
	129
	130	/**
	131	* qe_pin_request - Request a QE pin
	132	* @np: device node to get a pin from
	133	* @index: index of a pin in the device tree
	134	* Context: non-atomic
	135	*
	136	* This function return qe_pin so that you could use it with the rest of
	137	* the QE Pin Multiplexing API.
	138	*/
	139	struct qe_pin qe_pin_request(struct device_node np, int index)
	140	{
	141	struct qe_pin *qe_pin;
a19e3da5 AV	142	struct device_node *gpio_np;
a19e3da5 AV	143	struct gpio_chip *gc;
1b9e8904 AV	144	struct of_mm_gpio_chip *mm_gc;
	145	struct qe_gpio_chip *qe_gc;
	146	int err;
	147	int size;
	148	const void *gpio_spec;
	149	const u32 *gpio_cells;
	150	unsigned long flags;
	151
	152	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
	153	if (!qe_pin) {
	154	pr_debug("%s: can't allocate memory\n", __func__);
	155	return ERR_PTR(-ENOMEM);
	156	}
	157
	158	err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
a19e3da5	159	&gpio_np, &gpio_spec);
1b9e8904 AV	160	if (err) {
	161	pr_debug("%s: can't parse gpios property\n", __func__);
	162	goto err0;
	163	}
	164
a19e3da5	165	if (!of_device_is_compatible(gpio_np, "fsl,mpc8323-qe-pario-bank")) {
1b9e8904 AV	166	pr_debug("%s: tried to get a non-qe pin\n", __func__);
	167	err = -EINVAL;
	168	goto err1;
	169	}
	170
594fa265	171	gc = of_node_to_gpiochip(gpio_np);
a19e3da5	172	if (!gc) {
1b9e8904	173	pr_debug("%s: gpio controller %s isn't registered\n",
a19e3da5	174	np->full_name, gpio_np->full_name);
1b9e8904 AV	175	err = -ENODEV;
	176	goto err1;
	177	}
	178
a19e3da5	179	gpio_cells = of_get_property(gpio_np, "#gpio-cells", &size);
1b9e8904	180	if (!gpio_cells \|\| size != sizeof(*gpio_cells) \|\|
a19e3da5	181	*gpio_cells != gc->of_gpio_n_cells) {
1b9e8904	182	pr_debug("%s: wrong #gpio-cells for %s\n",
a19e3da5	183	np->full_name, gpio_np->full_name);
1b9e8904 AV	184	err = -EINVAL;
	185	goto err1;
	186	}
	187
a19e3da5	188	err = gc->of_xlate(gc, np, gpio_spec, NULL);
1b9e8904 AV	189	if (err < 0)
	190	goto err1;
	191
a19e3da5	192	mm_gc = to_of_mm_gpio_chip(gc);
1b9e8904 AV	193	qe_gc = to_qe_gpio_chip(mm_gc);
	194
	195	spin_lock_irqsave(&qe_gc->lock, flags);
	196
	197	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
	198	qe_pin->controller = qe_gc;
	199	qe_pin->num = err;
	200	err = 0;
	201	} else {
	202	err = -EBUSY;
	203	}
	204
	205	spin_unlock_irqrestore(&qe_gc->lock, flags);
	206
	207	if (!err)
	208	return qe_pin;
	209	err1:
a19e3da5	210	of_node_put(gpio_np);
1b9e8904 AV	211	err0:
	212	kfree(qe_pin);
	213	pr_debug("%s failed with status %d\n", __func__, err);
	214	return ERR_PTR(err);
	215	}
	216	EXPORT_SYMBOL(qe_pin_request);
	217
	218	/**
	219	* qe_pin_free - Free a pin
	220	* @qe_pin: pointer to the qe_pin structure
	221	* Context: any
	222	*
	223	* This function frees the qe_pin structure and makes a pin available
	224	* for further qe_pin_request() calls.
	225	*/
	226	void qe_pin_free(struct qe_pin *qe_pin)
	227	{
	228	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	229	unsigned long flags;
	230	const int pin = qe_pin->num;
	231
	232	spin_lock_irqsave(&qe_gc->lock, flags);
	233	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
	234	spin_unlock_irqrestore(&qe_gc->lock, flags);
	235
	236	kfree(qe_pin);
	237	}
	238	EXPORT_SYMBOL(qe_pin_free);
	239
	240	/**
	241	* qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
	242	* @qe_pin: pointer to the qe_pin structure
	243	* Context: any
	244	*
	245	* This function resets a pin to a dedicated peripheral function that
	246	* has been set up by the firmware.
	247	*/
	248	void qe_pin_set_dedicated(struct qe_pin *qe_pin)
	249	{
	250	struct qe_gpio_chip *qe_gc = qe_pin->controller;
	251	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
	252	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
	253	int pin = qe_pin->num;
	254	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
	255	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
	256	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
	257	unsigned long flags;
	258
	259	spin_lock_irqsave(&qe_gc->lock, flags);
	260
	261	if (second_reg) {
	262	clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
	263	clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
	264	} else {
	265	clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
	266	clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
	267	}
	268
	269	if (sregs->cpdata & mask1)
	270	qe_gc->cpdata \|= mask1;
	271	else
	272	qe_gc->cpdata &= ~mask1;
	273
	274	out_be32(&regs->cpdata, qe_gc->cpdata);
275	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
276
277	spin_unlock_irqrestore(&qe_gc->lock, flags);
278	}
279	EXPORT_SYMBOL(qe_pin_set_dedicated);
280
281	/**
282	* qe_pin_set_gpio - Set a pin to the GPIO mode
283	* @qe_pin: pointer to the qe_pin structure
284	* Context: any
285	*
286	* This function sets a pin to the GPIO mode.
287	*/
288	void qe_pin_set_gpio(struct qe_pin *qe_pin)
289	{
290	struct qe_gpio_chip *qe_gc = qe_pin->controller;
291	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
292	unsigned long flags;
293
294	spin_lock_irqsave(&qe_gc->lock, flags);
295
296	/* Let's make it input by default, GPIO API is able to change that. */
297	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
298
299	spin_unlock_irqrestore(&qe_gc->lock, flags);
300	}
301	EXPORT_SYMBOL(qe_pin_set_gpio);
302
d14b3dd6	303	static int __init qe_add_gpiochips(void)
32def337 AV	304	{
	305	struct device_node *np;
	306
	307	for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
	308	int ret;
	309	struct qe_gpio_chip *qe_gc;
	310	struct of_mm_gpio_chip *mm_gc;
32def337 AV	311	struct gpio_chip *gc;
	312
	313	qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
	314	if (!qe_gc) {
	315	ret = -ENOMEM;
	316	goto err;
	317	}
	318
	319	spin_lock_init(&qe_gc->lock);
	320
	321	mm_gc = &qe_gc->mm_gc;
a19e3da5	322	gc = &mm_gc->gc;
32def337 AV	323
32def337 AV	324	mm_gc->save_regs = qe_gpio_save_regs;
32def337 AV	325	gc->ngpio = QE_PIO_PINS;
	326	gc->direction_input = qe_gpio_dir_in;
	327	gc->direction_output = qe_gpio_dir_out;
	328	gc->get = qe_gpio_get;
	329	gc->set = qe_gpio_set;
	330
	331	ret = of_mm_gpiochip_add(np, mm_gc);
	332	if (ret)
	333	goto err;
	334	continue;
	335	err:
	336	pr_err("%s: registration failed with status %d\n",
	337	np->full_name, ret);
	338	kfree(qe_gc);
	339	/* try others anyway */
	340	}
d14b3dd6	341	return 0;
32def337	342	}
d14b3dd6	343	arch_initcall(qe_add_gpiochips);