[linux-2.6-block.git] / arch / powerpc / sysdev / ppc4xx_soc.c

/*
 * IBM/AMCC PPC4xx SoC setup code
 *
 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
 *
 * L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
 *   Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
 *   Copyright (c) 2003 - 2006 Zultys Technologies
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/of_platform.h>

#include <asm/dcr.h>
#include <asm/dcr-regs.h>
#include <asm/reg.h>

static u32 dcrbase_l2c;

/*
 * L2-cache
 */

/* Issue L2C diagnostic command */
static inline u32 l2c_diag(u32 addr)
{
	mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
	while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
		;

	return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);
}

static irqreturn_t l2c_error_handler(int irq, void *dev)
{
	u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);

	if (sr & L2C_SR_CPE) {
		/* Read cache trapped address */
		u32 addr = l2c_diag(0x42000000);
		printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n",
		       addr);
	}
	if (sr & L2C_SR_TPE) {
		/* Read tag trapped address */
		u32 addr = l2c_diag(0x82000000) >> 16;
		printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n",
		       addr);
	}

	/* Clear parity errors */
	if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
		mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
		mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
	} else {
		printk(KERN_EMERG "L2C: LRU error\n");
	}

	return IRQ_HANDLED;
}

static int __init ppc4xx_l2c_probe(void)
{
	struct device_node *np;
	u32 r;
	unsigned long flags;
	int irq;
	const u32 *dcrreg;
	u32 dcrbase_isram;
	int len;
	const u32 *prop;
	u32 l2_size;

	np = of_find_compatible_node(NULL, NULL, "ibm,l2-cache");
	if (!np)
		return 0;

	/* Get l2 cache size */
	prop = of_get_property(np, "cache-size", NULL);
	if (prop == NULL) {
		printk(KERN_ERR "%s: Can't get cache-size!\n", np->full_name);
		of_node_put(np);
		return -ENODEV;
	}
	l2_size = prop[0];

	/* Map DCRs */
	dcrreg = of_get_property(np, "dcr-reg", &len);
	if (!dcrreg || (len != 4 * sizeof(u32))) {
		printk(KERN_ERR "%s: Can't get DCR register base !",
		       np->full_name);
		of_node_put(np);
		return -ENODEV;
	}
	dcrbase_isram = dcrreg[0];
	dcrbase_l2c = dcrreg[2];

	/* Get and map irq number from device tree */
	irq = irq_of_parse_and_map(np, 0);
	if (irq == NO_IRQ) {
		printk(KERN_ERR "irq_of_parse_and_map failed\n");
		of_node_put(np);
		return -ENODEV;
	}

	/* Install error handler */
	if (request_irq(irq, l2c_error_handler, 0, "L2C", 0) < 0) {
		printk(KERN_ERR "Cannot install L2C error handler"
		       ", cache is not enabled\n");
		of_node_put(np);
		return -ENODEV;
	}

	local_irq_save(flags);
	asm volatile ("sync" ::: "memory");

	/* Disable SRAM */
	mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
	      mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
	mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
	mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
	mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
	mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);

	/* Enable L2_MODE without ICU/DCU */
	r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &
		~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
	r |= L2C_CFG_L2M | L2C_CFG_SS_256;
	mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);

	mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);

	/* Hardware Clear Command */
	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
	while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
		;

	/* Clear Cache Parity and Tag Errors */
	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);

	/* Enable 64G snoop region starting at 0 */
	r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &
		~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
	r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
	mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);

	r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &
		~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
	r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
	mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);

	asm volatile ("sync" ::: "memory");

	/* Enable ICU/DCU ports */
	r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);
	r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM
	       | L2C_CFG_TPEI | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
	r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
		| L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;

	/* Check for 460EX/GT special handling */
	if (of_device_is_compatible(np, "ibm,l2-cache-460ex") ||
	    of_device_is_compatible(np, "ibm,l2-cache-460gt"))
		r |= L2C_CFG_RDBW;

	mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);

	asm volatile ("sync; isync" ::: "memory");
	local_irq_restore(flags);

	printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10);

	of_node_put(np);
	return 0;
}
arch_initcall(ppc4xx_l2c_probe);

/*
 * Apply a system reset. Alternatively a board specific value may be
 * provided via the "reset-type" property in the cpu node.
 */
void ppc4xx_reset_system(char *cmd)
{
	struct device_node *np;
	u32 reset_type = DBCR0_RST_SYSTEM;
	const u32 *prop;

	np = of_find_node_by_type(NULL, "cpu");
	if (np) {
		prop = of_get_property(np, "reset-type", NULL);

		/*
		 * Check if property exists and if it is in range:
		 * 1 - PPC4xx core reset
		 * 2 - PPC4xx chip reset
		 * 3 - PPC4xx system reset (default)
		 */
		if ((prop) && ((prop[0] >= 1) && (prop[0] <= 3)))
			reset_type = prop[0] << 28;
	}

	mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | reset_type);

	while (1)
		;	/* Just in case the reset doesn't work */
}
Commit	Line	Data
2a706919 SR	1	/*
	2	* IBM/AMCC PPC4xx SoC setup code
	3	*
	4	* Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
	5	*
	6	* L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
	7	* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
	8	* Copyright (c) 2003 - 2006 Zultys Technologies
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <linux/stddef.h>
	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/errno.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/irq.h>
	22	#include <linux/of_platform.h>
	23
	24	#include <asm/dcr.h>
	25	#include <asm/dcr-regs.h>
93173ce2	26	#include <asm/reg.h>
2a706919 SR	27
	28	static u32 dcrbase_l2c;
	29
	30	/*
	31	* L2-cache
	32	*/
	33
	34	/* Issue L2C diagnostic command */
	35	static inline u32 l2c_diag(u32 addr)
	36	{
	37	mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
	38	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
	39	while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
	40	;
	41
	42	return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);
	43	}
	44
	45	static irqreturn_t l2c_error_handler(int irq, void *dev)
	46	{
	47	u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);
	48
	49	if (sr & L2C_SR_CPE) {
	50	/* Read cache trapped address */
	51	u32 addr = l2c_diag(0x42000000);
	52	printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n",
	53	addr);
	54	}
	55	if (sr & L2C_SR_TPE) {
	56	/* Read tag trapped address */
	57	u32 addr = l2c_diag(0x82000000) >> 16;
	58	printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n",
	59	addr);
	60	}
	61
	62	/* Clear parity errors */
	63	if (sr & (L2C_SR_CPE \| L2C_SR_TPE)){
	64	mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
	65	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP \| L2C_CMD_CTE);
	66	} else {
	67	printk(KERN_EMERG "L2C: LRU error\n");
	68	}
	69
	70	return IRQ_HANDLED;
	71	}
	72
	73	static int __init ppc4xx_l2c_probe(void)
	74	{
	75	struct device_node *np;
	76	u32 r;
	77	unsigned long flags;
	78	int irq;
	79	const u32 *dcrreg;
	80	u32 dcrbase_isram;
	81	int len;
	82	const u32 *prop;
	83	u32 l2_size;
	84
	85	np = of_find_compatible_node(NULL, NULL, "ibm,l2-cache");
	86	if (!np)
	87	return 0;
	88
	89	/* Get l2 cache size */
	90	prop = of_get_property(np, "cache-size", NULL);
91	if (prop == NULL) {
92	printk(KERN_ERR "%s: Can't get cache-size!\n", np->full_name);
93	of_node_put(np);
94	return -ENODEV;
95	}
96	l2_size = prop[0];
97
98	/* Map DCRs */
99	dcrreg = of_get_property(np, "dcr-reg", &len);
100	if (!dcrreg \|\| (len != 4 * sizeof(u32))) {
101	printk(KERN_ERR "%s: Can't get DCR register base !",
102	np->full_name);
103	of_node_put(np);
104	return -ENODEV;
105	}
106	dcrbase_isram = dcrreg[0];
107	dcrbase_l2c = dcrreg[2];
108
109	/* Get and map irq number from device tree */
110	irq = irq_of_parse_and_map(np, 0);
111	if (irq == NO_IRQ) {
112	printk(KERN_ERR "irq_of_parse_and_map failed\n");
113	of_node_put(np);
114	return -ENODEV;
115	}
116
117	/* Install error handler */
a3a9f3b4	118	if (request_irq(irq, l2c_error_handler, 0, "L2C", 0) < 0) {
2a706919 SR	119	printk(KERN_ERR "Cannot install L2C error handler"
	120	", cache is not enabled\n");
	121	of_node_put(np);
	122	return -ENODEV;
	123	}
	124
	125	local_irq_save(flags);
	126	asm volatile ("sync" ::: "memory");
	127
	128	/* Disable SRAM */
	129	mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
	130	mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
	131	mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
	132	mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
	133	mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
	134	mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
	135	mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
	136	mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
	137	mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
	138	mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
	139
	140	/* Enable L2_MODE without ICU/DCU */
	141	r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &
	142	~(L2C_CFG_ICU \| L2C_CFG_DCU \| L2C_CFG_SS_MASK);
	143	r \|= L2C_CFG_L2M \| L2C_CFG_SS_256;
	144	mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
	145
	146	mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
	147
	148	/* Hardware Clear Command */
	149	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
	150	while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
	151	;
	152
	153	/* Clear Cache Parity and Tag Errors */
	154	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP \| L2C_CMD_CTE);
	155
	156	/* Enable 64G snoop region starting at 0 */
	157	r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &
	158	~(L2C_SNP_BA_MASK \| L2C_SNP_SSR_MASK);
	159	r \|= L2C_SNP_SSR_32G \| L2C_SNP_ESR;
	160	mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);
	161
	162	r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &
	163	~(L2C_SNP_BA_MASK \| L2C_SNP_SSR_MASK);
	164	r \|= 0x80000000 \| L2C_SNP_SSR_32G \| L2C_SNP_ESR;
	165	mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);
	166
	167	asm volatile ("sync" ::: "memory");
	168
	169	/* Enable ICU/DCU ports */
	170	r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);
	171	r &= ~(L2C_CFG_DCW_MASK \| L2C_CFG_PMUX_MASK \| L2C_CFG_PMIM
	172	\| L2C_CFG_TPEI \| L2C_CFG_CPEI \| L2C_CFG_NAM \| L2C_CFG_NBRM);
	173	r \|= L2C_CFG_ICU \| L2C_CFG_DCU \| L2C_CFG_TPC \| L2C_CFG_CPC \| L2C_CFG_FRAN
	174	\| L2C_CFG_CPIM \| L2C_CFG_TPIM \| L2C_CFG_LIM \| L2C_CFG_SMCM;
	175
	176	/* Check for 460EX/GT special handling */
28ef35eb SR	177	if (of_device_is_compatible(np, "ibm,l2-cache-460ex") \|\|
28ef35eb SR	178	of_device_is_compatible(np, "ibm,l2-cache-460gt"))
2a706919 SR	179	r \|= L2C_CFG_RDBW;
	180
	181	mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
	182
	183	asm volatile ("sync; isync" ::: "memory");
	184	local_irq_restore(flags);
	185
	186	printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10);
	187
	188	of_node_put(np);
	189	return 0;
	190	}
	191	arch_initcall(ppc4xx_l2c_probe);
93173ce2 SR	192
93173ce2 SR	193	/*
a32fe93d SR	194	* Apply a system reset. Alternatively a board specific value may be
a32fe93d SR	195	* provided via the "reset-type" property in the cpu node.
93173ce2 SR	196	*/
	197	void ppc4xx_reset_system(char *cmd)
	198	{
a32fe93d SR	199	struct device_node *np;
	200	u32 reset_type = DBCR0_RST_SYSTEM;
	201	const u32 *prop;
	202
	203	np = of_find_node_by_type(NULL, "cpu");
	204	if (np) {
	205	prop = of_get_property(np, "reset-type", NULL);
	206
	207	/*
	208	* Check if property exists and if it is in range:
	209	* 1 - PPC4xx core reset
	210	* 2 - PPC4xx chip reset
	211	* 3 - PPC4xx system reset (default)
	212	*/
	213	if ((prop) && ((prop[0] >= 1) && (prop[0] <= 3)))
	214	reset_type = prop[0] << 28;
	215	}
	216
	217	mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) \| reset_type);
	218
93173ce2 SR	219	while (1)
	220	; /* Just in case the reset doesn't work */
	221	}