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5738ec6d BH |
1 | /* |
2 | * PCI / PCI-X / PCI-Express support for 4xx parts | |
3 | * | |
4 | * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. | |
5 | * | |
a2d2e1ec BH |
6 | * Most PCI Express code is coming from Stefan Roese implementation for |
7 | * arch/ppc in the Denx tree, slightly reworked by me. | |
8 | * | |
9 | * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> | |
10 | * | |
11 | * Some of that comes itself from a previous implementation for 440SPE only | |
12 | * by Roland Dreier: | |
13 | * | |
14 | * Copyright (c) 2005 Cisco Systems. All rights reserved. | |
15 | * Roland Dreier <rolandd@cisco.com> | |
16 | * | |
5738ec6d BH |
17 | */ |
18 | ||
035ee428 BH |
19 | #undef DEBUG |
20 | ||
5738ec6d BH |
21 | #include <linux/kernel.h> |
22 | #include <linux/pci.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/of.h> | |
a2d2e1ec BH |
25 | #include <linux/bootmem.h> |
26 | #include <linux/delay.h> | |
5738ec6d BH |
27 | |
28 | #include <asm/io.h> | |
29 | #include <asm/pci-bridge.h> | |
30 | #include <asm/machdep.h> | |
a2d2e1ec BH |
31 | #include <asm/dcr.h> |
32 | #include <asm/dcr-regs.h> | |
cc2e113b | 33 | #include <mm/mmu_decl.h> |
5738ec6d BH |
34 | |
35 | #include "ppc4xx_pci.h" | |
36 | ||
37 | static int dma_offset_set; | |
38 | ||
a2d2e1ec BH |
39 | #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) |
40 | #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) | |
41 | ||
8308c54d JF |
42 | #define RES_TO_U32_LOW(val) \ |
43 | ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val)) | |
44 | #define RES_TO_U32_HIGH(val) \ | |
45 | ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0)) | |
a2d2e1ec | 46 | |
accf5ef2 SR |
47 | static inline int ppc440spe_revA(void) |
48 | { | |
49 | /* Catch both 440SPe variants, with and without RAID6 support */ | |
50 | if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890) | |
51 | return 1; | |
52 | else | |
53 | return 0; | |
54 | } | |
55 | ||
c839e0ef BH |
56 | static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev) |
57 | { | |
58 | struct pci_controller *hose; | |
59 | int i; | |
60 | ||
61 | if (dev->devfn != 0 || dev->bus->self != NULL) | |
62 | return; | |
63 | ||
64 | hose = pci_bus_to_host(dev->bus); | |
65 | if (hose == NULL) | |
66 | return; | |
67 | ||
68 | if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") && | |
69 | !of_device_is_compatible(hose->dn, "ibm,plb-pcix") && | |
70 | !of_device_is_compatible(hose->dn, "ibm,plb-pci")) | |
71 | return; | |
72 | ||
5ce4b596 JB |
73 | if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") || |
74 | of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) { | |
75 | hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM; | |
76 | } | |
77 | ||
c839e0ef BH |
78 | /* Hide the PCI host BARs from the kernel as their content doesn't |
79 | * fit well in the resource management | |
80 | */ | |
81 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
82 | dev->resource[i].start = dev->resource[i].end = 0; | |
83 | dev->resource[i].flags = 0; | |
84 | } | |
85 | ||
86 | printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n", | |
87 | pci_name(dev)); | |
88 | } | |
89 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge); | |
90 | ||
5738ec6d BH |
91 | static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose, |
92 | void __iomem *reg, | |
93 | struct resource *res) | |
94 | { | |
95 | u64 size; | |
96 | const u32 *ranges; | |
97 | int rlen; | |
98 | int pna = of_n_addr_cells(hose->dn); | |
99 | int np = pna + 5; | |
100 | ||
101 | /* Default */ | |
102 | res->start = 0; | |
cc2e113b IY |
103 | size = 0x80000000; |
104 | res->end = size - 1; | |
5738ec6d BH |
105 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
106 | ||
107 | /* Get dma-ranges property */ | |
108 | ranges = of_get_property(hose->dn, "dma-ranges", &rlen); | |
109 | if (ranges == NULL) | |
110 | goto out; | |
111 | ||
112 | /* Walk it */ | |
113 | while ((rlen -= np * 4) >= 0) { | |
114 | u32 pci_space = ranges[0]; | |
115 | u64 pci_addr = of_read_number(ranges + 1, 2); | |
116 | u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3); | |
117 | size = of_read_number(ranges + pna + 3, 2); | |
118 | ranges += np; | |
119 | if (cpu_addr == OF_BAD_ADDR || size == 0) | |
120 | continue; | |
121 | ||
122 | /* We only care about memory */ | |
123 | if ((pci_space & 0x03000000) != 0x02000000) | |
124 | continue; | |
125 | ||
126 | /* We currently only support memory at 0, and pci_addr | |
127 | * within 32 bits space | |
128 | */ | |
129 | if (cpu_addr != 0 || pci_addr > 0xffffffff) { | |
130 | printk(KERN_WARNING "%s: Ignored unsupported dma range" | |
131 | " 0x%016llx...0x%016llx -> 0x%016llx\n", | |
132 | hose->dn->full_name, | |
133 | pci_addr, pci_addr + size - 1, cpu_addr); | |
134 | continue; | |
135 | } | |
136 | ||
137 | /* Check if not prefetchable */ | |
138 | if (!(pci_space & 0x40000000)) | |
139 | res->flags &= ~IORESOURCE_PREFETCH; | |
140 | ||
141 | ||
142 | /* Use that */ | |
143 | res->start = pci_addr; | |
5738ec6d | 144 | /* Beware of 32 bits resources */ |
8308c54d JF |
145 | if (sizeof(resource_size_t) == sizeof(u32) && |
146 | (pci_addr + size) > 0x100000000ull) | |
5738ec6d BH |
147 | res->end = 0xffffffff; |
148 | else | |
5738ec6d BH |
149 | res->end = res->start + size - 1; |
150 | break; | |
151 | } | |
152 | ||
153 | /* We only support one global DMA offset */ | |
154 | if (dma_offset_set && pci_dram_offset != res->start) { | |
155 | printk(KERN_ERR "%s: dma-ranges(s) mismatch\n", | |
156 | hose->dn->full_name); | |
157 | return -ENXIO; | |
158 | } | |
159 | ||
160 | /* Check that we can fit all of memory as we don't support | |
161 | * DMA bounce buffers | |
162 | */ | |
163 | if (size < total_memory) { | |
164 | printk(KERN_ERR "%s: dma-ranges too small " | |
cc2e113b IY |
165 | "(size=%llx total_memory=%llx)\n", |
166 | hose->dn->full_name, size, (u64)total_memory); | |
5738ec6d BH |
167 | return -ENXIO; |
168 | } | |
169 | ||
170 | /* Check we are a power of 2 size and that base is a multiple of size*/ | |
cc2e113b | 171 | if ((size & (size - 1)) != 0 || |
5738ec6d BH |
172 | (res->start & (size - 1)) != 0) { |
173 | printk(KERN_ERR "%s: dma-ranges unaligned\n", | |
174 | hose->dn->full_name); | |
175 | return -ENXIO; | |
176 | } | |
177 | ||
178 | /* Check that we are fully contained within 32 bits space */ | |
179 | if (res->end > 0xffffffff) { | |
180 | printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n", | |
181 | hose->dn->full_name); | |
182 | return -ENXIO; | |
183 | } | |
184 | out: | |
185 | dma_offset_set = 1; | |
186 | pci_dram_offset = res->start; | |
187 | ||
188 | printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n", | |
189 | pci_dram_offset); | |
190 | return 0; | |
191 | } | |
192 | ||
193 | /* | |
194 | * 4xx PCI 2.x part | |
195 | */ | |
c839e0ef | 196 | |
84d727a1 BH |
197 | static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose, |
198 | void __iomem *reg, | |
199 | u64 plb_addr, | |
200 | u64 pci_addr, | |
201 | u64 size, | |
202 | unsigned int flags, | |
203 | int index) | |
204 | { | |
205 | u32 ma, pcila, pciha; | |
206 | ||
1ac00cc2 BH |
207 | /* Hack warning ! The "old" PCI 2.x cell only let us configure the low |
208 | * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit | |
209 | * address are actually hard wired to a value that appears to depend | |
210 | * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx. | |
211 | * | |
212 | * The trick here is we just crop those top bits and ignore them when | |
213 | * programming the chip. That means the device-tree has to be right | |
214 | * for the specific part used (we don't print a warning if it's wrong | |
215 | * but on the other hand, you'll crash quickly enough), but at least | |
216 | * this code should work whatever the hard coded value is | |
217 | */ | |
218 | plb_addr &= 0xffffffffull; | |
219 | ||
220 | /* Note: Due to the above hack, the test below doesn't actually test | |
221 | * if you address is above 4G, but it tests that address and | |
222 | * (address + size) are both contained in the same 4G | |
223 | */ | |
84d727a1 BH |
224 | if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) || |
225 | size < 0x1000 || (plb_addr & (size - 1)) != 0) { | |
226 | printk(KERN_WARNING "%s: Resource out of range\n", | |
227 | hose->dn->full_name); | |
228 | return -1; | |
229 | } | |
230 | ma = (0xffffffffu << ilog2(size)) | 1; | |
231 | if (flags & IORESOURCE_PREFETCH) | |
232 | ma |= 2; | |
233 | ||
234 | pciha = RES_TO_U32_HIGH(pci_addr); | |
235 | pcila = RES_TO_U32_LOW(pci_addr); | |
236 | ||
237 | writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index)); | |
238 | writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index)); | |
239 | writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index)); | |
240 | writel(ma, reg + PCIL0_PMM0MA + (0x10 * index)); | |
241 | ||
242 | return 0; | |
243 | } | |
244 | ||
c839e0ef BH |
245 | static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose, |
246 | void __iomem *reg) | |
247 | { | |
84d727a1 | 248 | int i, j, found_isa_hole = 0; |
c839e0ef BH |
249 | |
250 | /* Setup outbound memory windows */ | |
251 | for (i = j = 0; i < 3; i++) { | |
252 | struct resource *res = &hose->mem_resources[i]; | |
253 | ||
254 | /* we only care about memory windows */ | |
255 | if (!(res->flags & IORESOURCE_MEM)) | |
256 | continue; | |
257 | if (j > 2) { | |
258 | printk(KERN_WARNING "%s: Too many ranges\n", | |
259 | hose->dn->full_name); | |
260 | break; | |
261 | } | |
262 | ||
84d727a1 BH |
263 | /* Configure the resource */ |
264 | if (ppc4xx_setup_one_pci_PMM(hose, reg, | |
265 | res->start, | |
266 | res->start - hose->pci_mem_offset, | |
267 | res->end + 1 - res->start, | |
268 | res->flags, | |
269 | j) == 0) { | |
270 | j++; | |
271 | ||
272 | /* If the resource PCI address is 0 then we have our | |
273 | * ISA memory hole | |
274 | */ | |
275 | if (res->start == hose->pci_mem_offset) | |
276 | found_isa_hole = 1; | |
c839e0ef | 277 | } |
c839e0ef | 278 | } |
84d727a1 BH |
279 | |
280 | /* Handle ISA memory hole if not already covered */ | |
281 | if (j <= 2 && !found_isa_hole && hose->isa_mem_size) | |
282 | if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0, | |
283 | hose->isa_mem_size, 0, j) == 0) | |
284 | printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", | |
285 | hose->dn->full_name); | |
c839e0ef BH |
286 | } |
287 | ||
288 | static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose, | |
289 | void __iomem *reg, | |
290 | const struct resource *res) | |
291 | { | |
292 | resource_size_t size = res->end - res->start + 1; | |
293 | u32 sa; | |
294 | ||
295 | /* Calculate window size */ | |
296 | sa = (0xffffffffu << ilog2(size)) | 1; | |
297 | sa |= 0x1; | |
298 | ||
299 | /* RAM is always at 0 local for now */ | |
300 | writel(0, reg + PCIL0_PTM1LA); | |
301 | writel(sa, reg + PCIL0_PTM1MS); | |
302 | ||
303 | /* Map on PCI side */ | |
304 | early_write_config_dword(hose, hose->first_busno, 0, | |
305 | PCI_BASE_ADDRESS_1, res->start); | |
306 | early_write_config_dword(hose, hose->first_busno, 0, | |
307 | PCI_BASE_ADDRESS_2, 0x00000000); | |
308 | early_write_config_word(hose, hose->first_busno, 0, | |
309 | PCI_COMMAND, 0x0006); | |
310 | } | |
311 | ||
5738ec6d BH |
312 | static void __init ppc4xx_probe_pci_bridge(struct device_node *np) |
313 | { | |
314 | /* NYI */ | |
c839e0ef BH |
315 | struct resource rsrc_cfg; |
316 | struct resource rsrc_reg; | |
317 | struct resource dma_window; | |
318 | struct pci_controller *hose = NULL; | |
319 | void __iomem *reg = NULL; | |
320 | const int *bus_range; | |
321 | int primary = 0; | |
322 | ||
5a013fc7 MF |
323 | /* Check if device is enabled */ |
324 | if (!of_device_is_available(np)) { | |
325 | printk(KERN_INFO "%s: Port disabled via device-tree\n", | |
326 | np->full_name); | |
327 | return; | |
328 | } | |
329 | ||
c839e0ef BH |
330 | /* Fetch config space registers address */ |
331 | if (of_address_to_resource(np, 0, &rsrc_cfg)) { | |
5a013fc7 | 332 | printk(KERN_ERR "%s: Can't get PCI config register base !", |
c839e0ef BH |
333 | np->full_name); |
334 | return; | |
335 | } | |
336 | /* Fetch host bridge internal registers address */ | |
337 | if (of_address_to_resource(np, 3, &rsrc_reg)) { | |
338 | printk(KERN_ERR "%s: Can't get PCI internal register base !", | |
339 | np->full_name); | |
340 | return; | |
341 | } | |
342 | ||
343 | /* Check if primary bridge */ | |
344 | if (of_get_property(np, "primary", NULL)) | |
345 | primary = 1; | |
346 | ||
347 | /* Get bus range if any */ | |
348 | bus_range = of_get_property(np, "bus-range", NULL); | |
349 | ||
350 | /* Map registers */ | |
351 | reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start); | |
352 | if (reg == NULL) { | |
353 | printk(KERN_ERR "%s: Can't map registers !", np->full_name); | |
354 | goto fail; | |
355 | } | |
356 | ||
357 | /* Allocate the host controller data structure */ | |
358 | hose = pcibios_alloc_controller(np); | |
359 | if (!hose) | |
360 | goto fail; | |
361 | ||
362 | hose->first_busno = bus_range ? bus_range[0] : 0x0; | |
363 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
364 | ||
365 | /* Setup config space */ | |
366 | setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0); | |
367 | ||
368 | /* Disable all windows */ | |
369 | writel(0, reg + PCIL0_PMM0MA); | |
370 | writel(0, reg + PCIL0_PMM1MA); | |
371 | writel(0, reg + PCIL0_PMM2MA); | |
372 | writel(0, reg + PCIL0_PTM1MS); | |
373 | writel(0, reg + PCIL0_PTM2MS); | |
374 | ||
375 | /* Parse outbound mapping resources */ | |
376 | pci_process_bridge_OF_ranges(hose, np, primary); | |
377 | ||
378 | /* Parse inbound mapping resources */ | |
379 | if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) | |
380 | goto fail; | |
381 | ||
382 | /* Configure outbound ranges POMs */ | |
383 | ppc4xx_configure_pci_PMMs(hose, reg); | |
384 | ||
385 | /* Configure inbound ranges PIMs */ | |
386 | ppc4xx_configure_pci_PTMs(hose, reg, &dma_window); | |
387 | ||
388 | /* We don't need the registers anymore */ | |
389 | iounmap(reg); | |
390 | return; | |
391 | ||
392 | fail: | |
393 | if (hose) | |
394 | pcibios_free_controller(hose); | |
395 | if (reg) | |
396 | iounmap(reg); | |
5738ec6d BH |
397 | } |
398 | ||
399 | /* | |
400 | * 4xx PCI-X part | |
401 | */ | |
402 | ||
84d727a1 BH |
403 | static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller *hose, |
404 | void __iomem *reg, | |
405 | u64 plb_addr, | |
406 | u64 pci_addr, | |
407 | u64 size, | |
408 | unsigned int flags, | |
409 | int index) | |
410 | { | |
411 | u32 lah, lal, pciah, pcial, sa; | |
412 | ||
413 | if (!is_power_of_2(size) || size < 0x1000 || | |
414 | (plb_addr & (size - 1)) != 0) { | |
415 | printk(KERN_WARNING "%s: Resource out of range\n", | |
416 | hose->dn->full_name); | |
417 | return -1; | |
418 | } | |
419 | ||
420 | /* Calculate register values */ | |
421 | lah = RES_TO_U32_HIGH(plb_addr); | |
422 | lal = RES_TO_U32_LOW(plb_addr); | |
423 | pciah = RES_TO_U32_HIGH(pci_addr); | |
424 | pcial = RES_TO_U32_LOW(pci_addr); | |
425 | sa = (0xffffffffu << ilog2(size)) | 0x1; | |
426 | ||
427 | /* Program register values */ | |
428 | if (index == 0) { | |
429 | writel(lah, reg + PCIX0_POM0LAH); | |
430 | writel(lal, reg + PCIX0_POM0LAL); | |
431 | writel(pciah, reg + PCIX0_POM0PCIAH); | |
432 | writel(pcial, reg + PCIX0_POM0PCIAL); | |
433 | writel(sa, reg + PCIX0_POM0SA); | |
434 | } else { | |
435 | writel(lah, reg + PCIX0_POM1LAH); | |
436 | writel(lal, reg + PCIX0_POM1LAL); | |
437 | writel(pciah, reg + PCIX0_POM1PCIAH); | |
438 | writel(pcial, reg + PCIX0_POM1PCIAL); | |
439 | writel(sa, reg + PCIX0_POM1SA); | |
440 | } | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
5738ec6d BH |
445 | static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose, |
446 | void __iomem *reg) | |
447 | { | |
84d727a1 | 448 | int i, j, found_isa_hole = 0; |
5738ec6d BH |
449 | |
450 | /* Setup outbound memory windows */ | |
451 | for (i = j = 0; i < 3; i++) { | |
452 | struct resource *res = &hose->mem_resources[i]; | |
453 | ||
454 | /* we only care about memory windows */ | |
455 | if (!(res->flags & IORESOURCE_MEM)) | |
456 | continue; | |
457 | if (j > 1) { | |
458 | printk(KERN_WARNING "%s: Too many ranges\n", | |
459 | hose->dn->full_name); | |
460 | break; | |
461 | } | |
462 | ||
84d727a1 BH |
463 | /* Configure the resource */ |
464 | if (ppc4xx_setup_one_pcix_POM(hose, reg, | |
465 | res->start, | |
466 | res->start - hose->pci_mem_offset, | |
467 | res->end + 1 - res->start, | |
468 | res->flags, | |
469 | j) == 0) { | |
470 | j++; | |
471 | ||
472 | /* If the resource PCI address is 0 then we have our | |
473 | * ISA memory hole | |
474 | */ | |
475 | if (res->start == hose->pci_mem_offset) | |
476 | found_isa_hole = 1; | |
5738ec6d | 477 | } |
5738ec6d | 478 | } |
84d727a1 BH |
479 | |
480 | /* Handle ISA memory hole if not already covered */ | |
481 | if (j <= 1 && !found_isa_hole && hose->isa_mem_size) | |
482 | if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0, | |
483 | hose->isa_mem_size, 0, j) == 0) | |
484 | printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", | |
485 | hose->dn->full_name); | |
5738ec6d BH |
486 | } |
487 | ||
488 | static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose, | |
489 | void __iomem *reg, | |
490 | const struct resource *res, | |
491 | int big_pim, | |
492 | int enable_msi_hole) | |
493 | { | |
494 | resource_size_t size = res->end - res->start + 1; | |
495 | u32 sa; | |
496 | ||
497 | /* RAM is always at 0 */ | |
498 | writel(0x00000000, reg + PCIX0_PIM0LAH); | |
499 | writel(0x00000000, reg + PCIX0_PIM0LAL); | |
500 | ||
501 | /* Calculate window size */ | |
502 | sa = (0xffffffffu << ilog2(size)) | 1; | |
503 | sa |= 0x1; | |
504 | if (res->flags & IORESOURCE_PREFETCH) | |
505 | sa |= 0x2; | |
506 | if (enable_msi_hole) | |
507 | sa |= 0x4; | |
508 | writel(sa, reg + PCIX0_PIM0SA); | |
509 | if (big_pim) | |
510 | writel(0xffffffff, reg + PCIX0_PIM0SAH); | |
511 | ||
512 | /* Map on PCI side */ | |
513 | writel(0x00000000, reg + PCIX0_BAR0H); | |
514 | writel(res->start, reg + PCIX0_BAR0L); | |
515 | writew(0x0006, reg + PCIX0_COMMAND); | |
516 | } | |
517 | ||
518 | static void __init ppc4xx_probe_pcix_bridge(struct device_node *np) | |
519 | { | |
520 | struct resource rsrc_cfg; | |
521 | struct resource rsrc_reg; | |
522 | struct resource dma_window; | |
523 | struct pci_controller *hose = NULL; | |
524 | void __iomem *reg = NULL; | |
525 | const int *bus_range; | |
526 | int big_pim = 0, msi = 0, primary = 0; | |
527 | ||
528 | /* Fetch config space registers address */ | |
529 | if (of_address_to_resource(np, 0, &rsrc_cfg)) { | |
530 | printk(KERN_ERR "%s:Can't get PCI-X config register base !", | |
531 | np->full_name); | |
532 | return; | |
533 | } | |
534 | /* Fetch host bridge internal registers address */ | |
535 | if (of_address_to_resource(np, 3, &rsrc_reg)) { | |
536 | printk(KERN_ERR "%s: Can't get PCI-X internal register base !", | |
537 | np->full_name); | |
538 | return; | |
539 | } | |
540 | ||
541 | /* Check if it supports large PIMs (440GX) */ | |
542 | if (of_get_property(np, "large-inbound-windows", NULL)) | |
543 | big_pim = 1; | |
544 | ||
545 | /* Check if we should enable MSIs inbound hole */ | |
546 | if (of_get_property(np, "enable-msi-hole", NULL)) | |
547 | msi = 1; | |
548 | ||
549 | /* Check if primary bridge */ | |
550 | if (of_get_property(np, "primary", NULL)) | |
551 | primary = 1; | |
552 | ||
553 | /* Get bus range if any */ | |
554 | bus_range = of_get_property(np, "bus-range", NULL); | |
555 | ||
556 | /* Map registers */ | |
557 | reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start); | |
558 | if (reg == NULL) { | |
559 | printk(KERN_ERR "%s: Can't map registers !", np->full_name); | |
560 | goto fail; | |
561 | } | |
562 | ||
563 | /* Allocate the host controller data structure */ | |
564 | hose = pcibios_alloc_controller(np); | |
565 | if (!hose) | |
566 | goto fail; | |
567 | ||
568 | hose->first_busno = bus_range ? bus_range[0] : 0x0; | |
569 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
570 | ||
571 | /* Setup config space */ | |
d234b3c3 SO |
572 | setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, |
573 | PPC_INDIRECT_TYPE_SET_CFG_TYPE); | |
5738ec6d BH |
574 | |
575 | /* Disable all windows */ | |
576 | writel(0, reg + PCIX0_POM0SA); | |
577 | writel(0, reg + PCIX0_POM1SA); | |
578 | writel(0, reg + PCIX0_POM2SA); | |
579 | writel(0, reg + PCIX0_PIM0SA); | |
580 | writel(0, reg + PCIX0_PIM1SA); | |
581 | writel(0, reg + PCIX0_PIM2SA); | |
582 | if (big_pim) { | |
583 | writel(0, reg + PCIX0_PIM0SAH); | |
584 | writel(0, reg + PCIX0_PIM2SAH); | |
585 | } | |
586 | ||
587 | /* Parse outbound mapping resources */ | |
588 | pci_process_bridge_OF_ranges(hose, np, primary); | |
589 | ||
590 | /* Parse inbound mapping resources */ | |
591 | if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) | |
592 | goto fail; | |
593 | ||
594 | /* Configure outbound ranges POMs */ | |
595 | ppc4xx_configure_pcix_POMs(hose, reg); | |
596 | ||
597 | /* Configure inbound ranges PIMs */ | |
598 | ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi); | |
599 | ||
600 | /* We don't need the registers anymore */ | |
601 | iounmap(reg); | |
602 | return; | |
603 | ||
604 | fail: | |
605 | if (hose) | |
606 | pcibios_free_controller(hose); | |
607 | if (reg) | |
608 | iounmap(reg); | |
609 | } | |
610 | ||
a2d2e1ec BH |
611 | #ifdef CONFIG_PPC4xx_PCI_EXPRESS |
612 | ||
5738ec6d BH |
613 | /* |
614 | * 4xx PCI-Express part | |
a2d2e1ec BH |
615 | * |
616 | * We support 3 parts currently based on the compatible property: | |
617 | * | |
accf5ef2 | 618 | * ibm,plb-pciex-440spe |
a2d2e1ec | 619 | * ibm,plb-pciex-405ex |
66b7e504 | 620 | * ibm,plb-pciex-460ex |
a2d2e1ec BH |
621 | * |
622 | * Anything else will be rejected for now as they are all subtly | |
623 | * different unfortunately. | |
624 | * | |
5738ec6d | 625 | */ |
a2d2e1ec | 626 | |
78994e24 | 627 | #define MAX_PCIE_BUS_MAPPED 0x40 |
a2d2e1ec BH |
628 | |
629 | struct ppc4xx_pciex_port | |
630 | { | |
631 | struct pci_controller *hose; | |
632 | struct device_node *node; | |
633 | unsigned int index; | |
634 | int endpoint; | |
035ee428 BH |
635 | int link; |
636 | int has_ibpre; | |
a2d2e1ec BH |
637 | unsigned int sdr_base; |
638 | dcr_host_t dcrs; | |
639 | struct resource cfg_space; | |
640 | struct resource utl_regs; | |
035ee428 | 641 | void __iomem *utl_base; |
a2d2e1ec BH |
642 | }; |
643 | ||
644 | static struct ppc4xx_pciex_port *ppc4xx_pciex_ports; | |
645 | static unsigned int ppc4xx_pciex_port_count; | |
646 | ||
647 | struct ppc4xx_pciex_hwops | |
648 | { | |
649 | int (*core_init)(struct device_node *np); | |
650 | int (*port_init_hw)(struct ppc4xx_pciex_port *port); | |
651 | int (*setup_utl)(struct ppc4xx_pciex_port *port); | |
652 | }; | |
653 | ||
654 | static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops; | |
655 | ||
656 | #ifdef CONFIG_44x | |
657 | ||
658 | /* Check various reset bits of the 440SPe PCIe core */ | |
659 | static int __init ppc440spe_pciex_check_reset(struct device_node *np) | |
660 | { | |
661 | u32 valPE0, valPE1, valPE2; | |
662 | int err = 0; | |
663 | ||
664 | /* SDR0_PEGPLLLCT1 reset */ | |
665 | if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) { | |
666 | /* | |
667 | * the PCIe core was probably already initialised | |
668 | * by firmware - let's re-reset RCSSET regs | |
669 | * | |
670 | * -- Shouldn't we also re-reset the whole thing ? -- BenH | |
671 | */ | |
672 | pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n"); | |
673 | mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000); | |
674 | mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000); | |
675 | mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000); | |
676 | } | |
677 | ||
678 | valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET); | |
679 | valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET); | |
680 | valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET); | |
681 | ||
682 | /* SDR0_PExRCSSET rstgu */ | |
683 | if (!(valPE0 & 0x01000000) || | |
684 | !(valPE1 & 0x01000000) || | |
685 | !(valPE2 & 0x01000000)) { | |
686 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n"); | |
687 | err = -1; | |
688 | } | |
689 | ||
690 | /* SDR0_PExRCSSET rstdl */ | |
691 | if (!(valPE0 & 0x00010000) || | |
692 | !(valPE1 & 0x00010000) || | |
693 | !(valPE2 & 0x00010000)) { | |
694 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n"); | |
695 | err = -1; | |
696 | } | |
697 | ||
698 | /* SDR0_PExRCSSET rstpyn */ | |
699 | if ((valPE0 & 0x00001000) || | |
700 | (valPE1 & 0x00001000) || | |
701 | (valPE2 & 0x00001000)) { | |
702 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n"); | |
703 | err = -1; | |
704 | } | |
705 | ||
706 | /* SDR0_PExRCSSET hldplb */ | |
707 | if ((valPE0 & 0x10000000) || | |
708 | (valPE1 & 0x10000000) || | |
709 | (valPE2 & 0x10000000)) { | |
710 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n"); | |
711 | err = -1; | |
712 | } | |
713 | ||
714 | /* SDR0_PExRCSSET rdy */ | |
715 | if ((valPE0 & 0x00100000) || | |
716 | (valPE1 & 0x00100000) || | |
717 | (valPE2 & 0x00100000)) { | |
718 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n"); | |
719 | err = -1; | |
720 | } | |
721 | ||
722 | /* SDR0_PExRCSSET shutdown */ | |
723 | if ((valPE0 & 0x00000100) || | |
724 | (valPE1 & 0x00000100) || | |
725 | (valPE2 & 0x00000100)) { | |
726 | printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n"); | |
727 | err = -1; | |
728 | } | |
729 | ||
730 | return err; | |
731 | } | |
732 | ||
733 | /* Global PCIe core initializations for 440SPe core */ | |
734 | static int __init ppc440spe_pciex_core_init(struct device_node *np) | |
735 | { | |
736 | int time_out = 20; | |
737 | ||
738 | /* Set PLL clock receiver to LVPECL */ | |
6e42b21b | 739 | dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); |
a2d2e1ec BH |
740 | |
741 | /* Shouldn't we do all the calibration stuff etc... here ? */ | |
742 | if (ppc440spe_pciex_check_reset(np)) | |
743 | return -ENXIO; | |
744 | ||
745 | if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) { | |
746 | printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration " | |
747 | "failed (0x%08x)\n", | |
748 | mfdcri(SDR0, PESDR0_PLLLCT2)); | |
749 | return -1; | |
750 | } | |
751 | ||
752 | /* De-assert reset of PCIe PLL, wait for lock */ | |
6e42b21b | 753 | dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); |
a2d2e1ec BH |
754 | udelay(3); |
755 | ||
756 | while (time_out) { | |
757 | if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) { | |
758 | time_out--; | |
759 | udelay(1); | |
760 | } else | |
761 | break; | |
762 | } | |
763 | if (!time_out) { | |
764 | printk(KERN_INFO "PCIE: VCO output not locked\n"); | |
765 | return -1; | |
766 | } | |
767 | ||
768 | pr_debug("PCIE initialization OK\n"); | |
769 | ||
770 | return 3; | |
771 | } | |
772 | ||
773 | static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
774 | { | |
775 | u32 val = 1 << 24; | |
776 | ||
777 | if (port->endpoint) | |
778 | val = PTYPE_LEGACY_ENDPOINT << 20; | |
779 | else | |
780 | val = PTYPE_ROOT_PORT << 20; | |
781 | ||
782 | if (port->index == 0) | |
783 | val |= LNKW_X8 << 12; | |
784 | else | |
785 | val |= LNKW_X4 << 12; | |
786 | ||
787 | mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); | |
788 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); | |
accf5ef2 | 789 | if (ppc440spe_revA()) |
a2d2e1ec BH |
790 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); |
791 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); | |
792 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); | |
793 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); | |
794 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); | |
795 | if (port->index == 0) { | |
796 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, | |
797 | 0x35000000); | |
798 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1, | |
799 | 0x35000000); | |
800 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1, | |
801 | 0x35000000); | |
802 | mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, | |
803 | 0x35000000); | |
804 | } | |
6e42b21b VB |
805 | dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, |
806 | (1 << 24) | (1 << 16), 1 << 12); | |
a2d2e1ec BH |
807 | |
808 | return 0; | |
809 | } | |
810 | ||
035ee428 BH |
811 | static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port) |
812 | { | |
813 | return ppc440spe_pciex_init_port_hw(port); | |
814 | } | |
815 | ||
816 | static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
a2d2e1ec | 817 | { |
035ee428 BH |
818 | int rc = ppc440spe_pciex_init_port_hw(port); |
819 | ||
820 | port->has_ibpre = 1; | |
821 | ||
822 | return rc; | |
823 | } | |
a2d2e1ec | 824 | |
035ee428 BH |
825 | static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port) |
826 | { | |
a2d2e1ec BH |
827 | /* XXX Check what that value means... I hate magic */ |
828 | dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); | |
829 | ||
a2d2e1ec BH |
830 | /* |
831 | * Set buffer allocations and then assert VRB and TXE. | |
832 | */ | |
035ee428 BH |
833 | out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); |
834 | out_be32(port->utl_base + PEUTL_INTR, 0x02000000); | |
835 | out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000); | |
836 | out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000); | |
837 | out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000); | |
838 | out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000); | |
839 | out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); | |
840 | out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); | |
a2d2e1ec | 841 | |
035ee428 BH |
842 | return 0; |
843 | } | |
844 | ||
845 | static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port) | |
846 | { | |
847 | /* Report CRS to the operating system */ | |
848 | out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); | |
a2d2e1ec BH |
849 | |
850 | return 0; | |
851 | } | |
852 | ||
853 | static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata = | |
854 | { | |
855 | .core_init = ppc440spe_pciex_core_init, | |
035ee428 | 856 | .port_init_hw = ppc440speA_pciex_init_port_hw, |
a2d2e1ec BH |
857 | .setup_utl = ppc440speA_pciex_init_utl, |
858 | }; | |
859 | ||
860 | static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata = | |
861 | { | |
862 | .core_init = ppc440spe_pciex_core_init, | |
035ee428 BH |
863 | .port_init_hw = ppc440speB_pciex_init_port_hw, |
864 | .setup_utl = ppc440speB_pciex_init_utl, | |
a2d2e1ec BH |
865 | }; |
866 | ||
66b7e504 SR |
867 | static int __init ppc460ex_pciex_core_init(struct device_node *np) |
868 | { | |
869 | /* Nothing to do, return 2 ports */ | |
870 | return 2; | |
871 | } | |
872 | ||
873 | static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
874 | { | |
875 | u32 val; | |
876 | u32 utlset1; | |
877 | ||
5f91925c | 878 | if (port->endpoint) |
66b7e504 | 879 | val = PTYPE_LEGACY_ENDPOINT << 20; |
5f91925c | 880 | else |
66b7e504 | 881 | val = PTYPE_ROOT_PORT << 20; |
66b7e504 SR |
882 | |
883 | if (port->index == 0) { | |
884 | val |= LNKW_X1 << 12; | |
5f91925c | 885 | utlset1 = 0x20000000; |
66b7e504 SR |
886 | } else { |
887 | val |= LNKW_X4 << 12; | |
5f91925c | 888 | utlset1 = 0x20101101; |
66b7e504 SR |
889 | } |
890 | ||
891 | mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); | |
892 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1); | |
893 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); | |
894 | ||
895 | switch (port->index) { | |
896 | case 0: | |
897 | mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); | |
e30c9875 | 898 | mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); |
66b7e504 SR |
899 | mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); |
900 | ||
901 | mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000); | |
902 | break; | |
903 | ||
904 | case 1: | |
905 | mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230); | |
906 | mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230); | |
907 | mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230); | |
908 | mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230); | |
e30c9875 TM |
909 | mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130); |
910 | mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130); | |
911 | mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130); | |
912 | mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130); | |
66b7e504 SR |
913 | mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006); |
914 | mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006); | |
915 | mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006); | |
916 | mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006); | |
917 | ||
918 | mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000); | |
919 | break; | |
920 | } | |
921 | ||
922 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, | |
923 | mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | | |
924 | (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN)); | |
925 | ||
926 | /* Poll for PHY reset */ | |
927 | /* XXX FIXME add timeout */ | |
928 | switch (port->index) { | |
929 | case 0: | |
930 | while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1)) | |
931 | udelay(10); | |
932 | break; | |
933 | case 1: | |
934 | while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1)) | |
935 | udelay(10); | |
936 | break; | |
937 | } | |
938 | ||
939 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, | |
940 | (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & | |
941 | ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) | | |
942 | PESDRx_RCSSET_RSTPYN); | |
943 | ||
944 | port->has_ibpre = 1; | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
949 | static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port) | |
950 | { | |
951 | dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); | |
952 | ||
953 | /* | |
954 | * Set buffer allocations and then assert VRB and TXE. | |
955 | */ | |
956 | out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c); | |
957 | out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); | |
958 | out_be32(port->utl_base + PEUTL_INTR, 0x02000000); | |
959 | out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); | |
960 | out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000); | |
961 | out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); | |
962 | out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); | |
963 | out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000); | |
964 | out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); | |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
969 | static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata = | |
970 | { | |
971 | .core_init = ppc460ex_pciex_core_init, | |
972 | .port_init_hw = ppc460ex_pciex_init_port_hw, | |
973 | .setup_utl = ppc460ex_pciex_init_utl, | |
974 | }; | |
975 | ||
a2d2e1ec BH |
976 | #endif /* CONFIG_44x */ |
977 | ||
978 | #ifdef CONFIG_40x | |
979 | ||
980 | static int __init ppc405ex_pciex_core_init(struct device_node *np) | |
981 | { | |
982 | /* Nothing to do, return 2 ports */ | |
983 | return 2; | |
984 | } | |
985 | ||
986 | static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port) | |
987 | { | |
988 | /* Assert the PE0_PHY reset */ | |
989 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000); | |
990 | msleep(1); | |
991 | ||
992 | /* deassert the PE0_hotreset */ | |
993 | if (port->endpoint) | |
994 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000); | |
995 | else | |
996 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000); | |
997 | ||
998 | /* poll for phy !reset */ | |
999 | /* XXX FIXME add timeout */ | |
1000 | while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000)) | |
1001 | ; | |
1002 | ||
1003 | /* deassert the PE0_gpl_utl_reset */ | |
1004 | mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000); | |
1005 | } | |
1006 | ||
1007 | static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port) | |
1008 | { | |
1009 | u32 val; | |
1010 | ||
1011 | if (port->endpoint) | |
1012 | val = PTYPE_LEGACY_ENDPOINT; | |
1013 | else | |
1014 | val = PTYPE_ROOT_PORT; | |
1015 | ||
1016 | mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, | |
1017 | 1 << 24 | val << 20 | LNKW_X1 << 12); | |
1018 | ||
1019 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); | |
1020 | mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); | |
1021 | mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000); | |
1022 | mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003); | |
1023 | ||
1024 | /* | |
1025 | * Only reset the PHY when no link is currently established. | |
1026 | * This is for the Atheros PCIe board which has problems to establish | |
1027 | * the link (again) after this PHY reset. All other currently tested | |
1028 | * PCIe boards don't show this problem. | |
1029 | * This has to be re-tested and fixed in a later release! | |
1030 | */ | |
a2d2e1ec BH |
1031 | val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); |
1032 | if (!(val & 0x00001000)) | |
1033 | ppc405ex_pcie_phy_reset(port); | |
a2d2e1ec BH |
1034 | |
1035 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ | |
1036 | ||
55aaf6ec SR |
1037 | port->has_ibpre = 1; |
1038 | ||
a2d2e1ec BH |
1039 | return 0; |
1040 | } | |
1041 | ||
1042 | static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port) | |
1043 | { | |
a2d2e1ec BH |
1044 | dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); |
1045 | ||
a2d2e1ec BH |
1046 | /* |
1047 | * Set buffer allocations and then assert VRB and TXE. | |
1048 | */ | |
035ee428 BH |
1049 | out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000); |
1050 | out_be32(port->utl_base + PEUTL_INTR, 0x02000000); | |
1051 | out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); | |
1052 | out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000); | |
1053 | out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); | |
1054 | out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); | |
1055 | out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); | |
1056 | out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); | |
a2d2e1ec | 1057 | |
035ee428 | 1058 | out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); |
a2d2e1ec BH |
1059 | |
1060 | return 0; | |
1061 | } | |
1062 | ||
1063 | static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata = | |
1064 | { | |
1065 | .core_init = ppc405ex_pciex_core_init, | |
1066 | .port_init_hw = ppc405ex_pciex_init_port_hw, | |
1067 | .setup_utl = ppc405ex_pciex_init_utl, | |
1068 | }; | |
1069 | ||
1070 | #endif /* CONFIG_40x */ | |
1071 | ||
1072 | ||
1073 | /* Check that the core has been initied and if not, do it */ | |
1074 | static int __init ppc4xx_pciex_check_core_init(struct device_node *np) | |
1075 | { | |
1076 | static int core_init; | |
1077 | int count = -ENODEV; | |
1078 | ||
1079 | if (core_init++) | |
1080 | return 0; | |
1081 | ||
1082 | #ifdef CONFIG_44x | |
accf5ef2 SR |
1083 | if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) { |
1084 | if (ppc440spe_revA()) | |
1085 | ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops; | |
1086 | else | |
1087 | ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops; | |
1088 | } | |
66b7e504 SR |
1089 | if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) |
1090 | ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops; | |
a2d2e1ec BH |
1091 | #endif /* CONFIG_44x */ |
1092 | #ifdef CONFIG_40x | |
1093 | if (of_device_is_compatible(np, "ibm,plb-pciex-405ex")) | |
1094 | ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops; | |
1095 | #endif | |
1096 | if (ppc4xx_pciex_hwops == NULL) { | |
1097 | printk(KERN_WARNING "PCIE: unknown host type %s\n", | |
1098 | np->full_name); | |
1099 | return -ENODEV; | |
1100 | } | |
1101 | ||
1102 | count = ppc4xx_pciex_hwops->core_init(np); | |
1103 | if (count > 0) { | |
1104 | ppc4xx_pciex_ports = | |
1105 | kzalloc(count * sizeof(struct ppc4xx_pciex_port), | |
1106 | GFP_KERNEL); | |
1107 | if (ppc4xx_pciex_ports) { | |
1108 | ppc4xx_pciex_port_count = count; | |
1109 | return 0; | |
1110 | } | |
1111 | printk(KERN_WARNING "PCIE: failed to allocate ports array\n"); | |
1112 | return -ENOMEM; | |
1113 | } | |
1114 | return -ENODEV; | |
1115 | } | |
1116 | ||
1117 | static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port) | |
1118 | { | |
1119 | /* We map PCI Express configuration based on the reg property */ | |
1120 | dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH, | |
1121 | RES_TO_U32_HIGH(port->cfg_space.start)); | |
1122 | dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL, | |
1123 | RES_TO_U32_LOW(port->cfg_space.start)); | |
1124 | ||
1125 | /* XXX FIXME: Use size from reg property. For now, map 512M */ | |
1126 | dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); | |
1127 | ||
1128 | /* We map UTL registers based on the reg property */ | |
1129 | dcr_write(port->dcrs, DCRO_PEGPL_REGBAH, | |
1130 | RES_TO_U32_HIGH(port->utl_regs.start)); | |
1131 | dcr_write(port->dcrs, DCRO_PEGPL_REGBAL, | |
1132 | RES_TO_U32_LOW(port->utl_regs.start)); | |
1133 | ||
1134 | /* XXX FIXME: Use size from reg property */ | |
1135 | dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); | |
1136 | ||
1137 | /* Disable all other outbound windows */ | |
1138 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0); | |
1139 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0); | |
1140 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0); | |
1141 | dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); | |
1142 | } | |
1143 | ||
035ee428 BH |
1144 | static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port, |
1145 | unsigned int sdr_offset, | |
1146 | unsigned int mask, | |
1147 | unsigned int value, | |
1148 | int timeout_ms) | |
a2d2e1ec | 1149 | { |
a2d2e1ec BH |
1150 | u32 val; |
1151 | ||
035ee428 BH |
1152 | while(timeout_ms--) { |
1153 | val = mfdcri(SDR0, port->sdr_base + sdr_offset); | |
1154 | if ((val & mask) == value) { | |
1155 | pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n", | |
1156 | port->index, sdr_offset, timeout_ms, val); | |
1157 | return 0; | |
1158 | } | |
1159 | msleep(1); | |
1160 | } | |
1161 | return -1; | |
1162 | } | |
1163 | ||
1164 | static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port) | |
1165 | { | |
1166 | int rc = 0; | |
a2d2e1ec BH |
1167 | |
1168 | /* Init HW */ | |
1169 | if (ppc4xx_pciex_hwops->port_init_hw) | |
1170 | rc = ppc4xx_pciex_hwops->port_init_hw(port); | |
1171 | if (rc != 0) | |
1172 | return rc; | |
1173 | ||
035ee428 | 1174 | printk(KERN_INFO "PCIE%d: Checking link...\n", |
a2d2e1ec | 1175 | port->index); |
a2d2e1ec | 1176 | |
035ee428 BH |
1177 | /* Wait for reset to complete */ |
1178 | if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) { | |
1179 | printk(KERN_WARNING "PCIE%d: PGRST failed\n", | |
1180 | port->index); | |
a2d2e1ec BH |
1181 | return -1; |
1182 | } | |
1183 | ||
035ee428 BH |
1184 | /* Check for card presence detect if supported, if not, just wait for |
1185 | * link unconditionally. | |
1186 | * | |
1187 | * note that we don't fail if there is no link, we just filter out | |
1188 | * config space accesses. That way, it will be easier to implement | |
1189 | * hotplug later on. | |
a2d2e1ec | 1190 | */ |
035ee428 BH |
1191 | if (!port->has_ibpre || |
1192 | !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, | |
1193 | 1 << 28, 1 << 28, 100)) { | |
1194 | printk(KERN_INFO | |
1195 | "PCIE%d: Device detected, waiting for link...\n", | |
a2d2e1ec | 1196 | port->index); |
035ee428 BH |
1197 | if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP, |
1198 | 0x1000, 0x1000, 2000)) | |
1199 | printk(KERN_WARNING | |
1200 | "PCIE%d: Link up failed\n", port->index); | |
1201 | else { | |
1202 | printk(KERN_INFO | |
1203 | "PCIE%d: link is up !\n", port->index); | |
1204 | port->link = 1; | |
1205 | } | |
1206 | } else | |
1207 | printk(KERN_INFO "PCIE%d: No device detected.\n", port->index); | |
a2d2e1ec BH |
1208 | |
1209 | /* | |
1210 | * Initialize mapping: disable all regions and configure | |
1211 | * CFG and REG regions based on resources in the device tree | |
1212 | */ | |
1213 | ppc4xx_pciex_port_init_mapping(port); | |
1214 | ||
1215 | /* | |
035ee428 BH |
1216 | * Map UTL |
1217 | */ | |
1218 | port->utl_base = ioremap(port->utl_regs.start, 0x100); | |
1219 | BUG_ON(port->utl_base == NULL); | |
1220 | ||
1221 | /* | |
1222 | * Setup UTL registers --BenH. | |
a2d2e1ec BH |
1223 | */ |
1224 | if (ppc4xx_pciex_hwops->setup_utl) | |
1225 | ppc4xx_pciex_hwops->setup_utl(port); | |
1226 | ||
1227 | /* | |
1228 | * Check for VC0 active and assert RDY. | |
1229 | */ | |
035ee428 BH |
1230 | if (port->link && |
1231 | ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, | |
1232 | 1 << 16, 1 << 16, 5000)) { | |
1233 | printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index); | |
1234 | port->link = 0; | |
a2d2e1ec | 1235 | } |
035ee428 | 1236 | |
6e42b21b | 1237 | dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); |
a2d2e1ec BH |
1238 | msleep(100); |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port, | |
1244 | struct pci_bus *bus, | |
1245 | unsigned int devfn) | |
1246 | { | |
1247 | static int message; | |
1248 | ||
1249 | /* Endpoint can not generate upstream(remote) config cycles */ | |
1250 | if (port->endpoint && bus->number != port->hose->first_busno) | |
1251 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1252 | ||
1253 | /* Check we are within the mapped range */ | |
1254 | if (bus->number > port->hose->last_busno) { | |
1255 | if (!message) { | |
1256 | printk(KERN_WARNING "Warning! Probing bus %u" | |
1257 | " out of range !\n", bus->number); | |
1258 | message++; | |
1259 | } | |
1260 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1261 | } | |
1262 | ||
1263 | /* The root complex has only one device / function */ | |
1264 | if (bus->number == port->hose->first_busno && devfn != 0) | |
1265 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1266 | ||
1267 | /* The other side of the RC has only one device as well */ | |
1268 | if (bus->number == (port->hose->first_busno + 1) && | |
1269 | PCI_SLOT(devfn) != 0) | |
1270 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1271 | ||
035ee428 BH |
1272 | /* Check if we have a link */ |
1273 | if ((bus->number != port->hose->first_busno) && !port->link) | |
1274 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1275 | ||
a2d2e1ec BH |
1276 | return 0; |
1277 | } | |
1278 | ||
1279 | static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port, | |
1280 | struct pci_bus *bus, | |
1281 | unsigned int devfn) | |
1282 | { | |
1283 | int relbus; | |
1284 | ||
1285 | /* Remove the casts when we finally remove the stupid volatile | |
1286 | * in struct pci_controller | |
1287 | */ | |
1288 | if (bus->number == port->hose->first_busno) | |
1289 | return (void __iomem *)port->hose->cfg_addr; | |
1290 | ||
1291 | relbus = bus->number - (port->hose->first_busno + 1); | |
1292 | return (void __iomem *)port->hose->cfg_data + | |
1293 | ((relbus << 20) | (devfn << 12)); | |
1294 | } | |
1295 | ||
1296 | static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn, | |
1297 | int offset, int len, u32 *val) | |
1298 | { | |
f159edae | 1299 | struct pci_controller *hose = pci_bus_to_host(bus); |
a2d2e1ec BH |
1300 | struct ppc4xx_pciex_port *port = |
1301 | &ppc4xx_pciex_ports[hose->indirect_type]; | |
1302 | void __iomem *addr; | |
1303 | u32 gpl_cfg; | |
1304 | ||
1305 | BUG_ON(hose != port->hose); | |
1306 | ||
1307 | if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) | |
1308 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1309 | ||
1310 | addr = ppc4xx_pciex_get_config_base(port, bus, devfn); | |
1311 | ||
1312 | /* | |
1313 | * Reading from configuration space of non-existing device can | |
1314 | * generate transaction errors. For the read duration we suppress | |
1315 | * assertion of machine check exceptions to avoid those. | |
1316 | */ | |
1317 | gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); | |
1318 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); | |
1319 | ||
035ee428 BH |
1320 | /* Make sure no CRS is recorded */ |
1321 | out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); | |
1322 | ||
a2d2e1ec BH |
1323 | switch (len) { |
1324 | case 1: | |
1325 | *val = in_8((u8 *)(addr + offset)); | |
1326 | break; | |
1327 | case 2: | |
1328 | *val = in_le16((u16 *)(addr + offset)); | |
1329 | break; | |
1330 | default: | |
1331 | *val = in_le32((u32 *)(addr + offset)); | |
1332 | break; | |
1333 | } | |
1334 | ||
1335 | pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" | |
1336 | " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", | |
1337 | bus->number, hose->first_busno, hose->last_busno, | |
1338 | devfn, offset, len, addr + offset, *val); | |
1339 | ||
035ee428 BH |
1340 | /* Check for CRS (440SPe rev B does that for us but heh ..) */ |
1341 | if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { | |
1342 | pr_debug("Got CRS !\n"); | |
1343 | if (len != 4 || offset != 0) | |
1344 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1345 | *val = 0xffff0001; | |
1346 | } | |
1347 | ||
a2d2e1ec BH |
1348 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); |
1349 | ||
1350 | return PCIBIOS_SUCCESSFUL; | |
1351 | } | |
1352 | ||
1353 | static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn, | |
1354 | int offset, int len, u32 val) | |
1355 | { | |
f159edae | 1356 | struct pci_controller *hose = pci_bus_to_host(bus); |
a2d2e1ec BH |
1357 | struct ppc4xx_pciex_port *port = |
1358 | &ppc4xx_pciex_ports[hose->indirect_type]; | |
1359 | void __iomem *addr; | |
1360 | u32 gpl_cfg; | |
1361 | ||
1362 | if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) | |
1363 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1364 | ||
1365 | addr = ppc4xx_pciex_get_config_base(port, bus, devfn); | |
1366 | ||
1367 | /* | |
1368 | * Reading from configuration space of non-existing device can | |
1369 | * generate transaction errors. For the read duration we suppress | |
1370 | * assertion of machine check exceptions to avoid those. | |
1371 | */ | |
1372 | gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); | |
1373 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); | |
1374 | ||
1375 | pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x" | |
1376 | " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", | |
1377 | bus->number, hose->first_busno, hose->last_busno, | |
1378 | devfn, offset, len, addr + offset, val); | |
1379 | ||
1380 | switch (len) { | |
1381 | case 1: | |
1382 | out_8((u8 *)(addr + offset), val); | |
1383 | break; | |
1384 | case 2: | |
1385 | out_le16((u16 *)(addr + offset), val); | |
1386 | break; | |
1387 | default: | |
1388 | out_le32((u32 *)(addr + offset), val); | |
1389 | break; | |
1390 | } | |
1391 | ||
1392 | dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); | |
1393 | ||
1394 | return PCIBIOS_SUCCESSFUL; | |
1395 | } | |
1396 | ||
1397 | static struct pci_ops ppc4xx_pciex_pci_ops = | |
1398 | { | |
1399 | .read = ppc4xx_pciex_read_config, | |
1400 | .write = ppc4xx_pciex_write_config, | |
1401 | }; | |
1402 | ||
84d727a1 BH |
1403 | static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port, |
1404 | struct pci_controller *hose, | |
1405 | void __iomem *mbase, | |
1406 | u64 plb_addr, | |
1407 | u64 pci_addr, | |
1408 | u64 size, | |
1409 | unsigned int flags, | |
1410 | int index) | |
1411 | { | |
1412 | u32 lah, lal, pciah, pcial, sa; | |
1413 | ||
1414 | if (!is_power_of_2(size) || | |
1415 | (index < 2 && size < 0x100000) || | |
1416 | (index == 2 && size < 0x100) || | |
1417 | (plb_addr & (size - 1)) != 0) { | |
1418 | printk(KERN_WARNING "%s: Resource out of range\n", | |
1419 | hose->dn->full_name); | |
1420 | return -1; | |
1421 | } | |
1422 | ||
1423 | /* Calculate register values */ | |
1424 | lah = RES_TO_U32_HIGH(plb_addr); | |
1425 | lal = RES_TO_U32_LOW(plb_addr); | |
1426 | pciah = RES_TO_U32_HIGH(pci_addr); | |
1427 | pcial = RES_TO_U32_LOW(pci_addr); | |
1428 | sa = (0xffffffffu << ilog2(size)) | 0x1; | |
1429 | ||
1430 | /* Program register values */ | |
1431 | switch (index) { | |
1432 | case 0: | |
1433 | out_le32(mbase + PECFG_POM0LAH, pciah); | |
1434 | out_le32(mbase + PECFG_POM0LAL, pcial); | |
1435 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah); | |
1436 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal); | |
1437 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff); | |
1438 | /* Note that 3 here means enabled | single region */ | |
1439 | dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3); | |
1440 | break; | |
1441 | case 1: | |
1442 | out_le32(mbase + PECFG_POM1LAH, pciah); | |
1443 | out_le32(mbase + PECFG_POM1LAL, pcial); | |
1444 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); | |
1445 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal); | |
1446 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); | |
1447 | /* Note that 3 here means enabled | single region */ | |
1448 | dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3); | |
1449 | break; | |
1450 | case 2: | |
1451 | out_le32(mbase + PECFG_POM2LAH, pciah); | |
1452 | out_le32(mbase + PECFG_POM2LAL, pcial); | |
1453 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah); | |
1454 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal); | |
1455 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff); | |
1456 | /* Note that 3 here means enabled | IO space !!! */ | |
1457 | dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, sa | 3); | |
1458 | break; | |
1459 | } | |
1460 | ||
1461 | return 0; | |
1462 | } | |
1463 | ||
a2d2e1ec BH |
1464 | static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port, |
1465 | struct pci_controller *hose, | |
1466 | void __iomem *mbase) | |
1467 | { | |
84d727a1 | 1468 | int i, j, found_isa_hole = 0; |
a2d2e1ec BH |
1469 | |
1470 | /* Setup outbound memory windows */ | |
1471 | for (i = j = 0; i < 3; i++) { | |
1472 | struct resource *res = &hose->mem_resources[i]; | |
1473 | ||
1474 | /* we only care about memory windows */ | |
1475 | if (!(res->flags & IORESOURCE_MEM)) | |
1476 | continue; | |
1477 | if (j > 1) { | |
1478 | printk(KERN_WARNING "%s: Too many ranges\n", | |
1479 | port->node->full_name); | |
1480 | break; | |
1481 | } | |
1482 | ||
84d727a1 BH |
1483 | /* Configure the resource */ |
1484 | if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, | |
1485 | res->start, | |
1486 | res->start - hose->pci_mem_offset, | |
1487 | res->end + 1 - res->start, | |
1488 | res->flags, | |
1489 | j) == 0) { | |
1490 | j++; | |
1491 | ||
1492 | /* If the resource PCI address is 0 then we have our | |
1493 | * ISA memory hole | |
1494 | */ | |
1495 | if (res->start == hose->pci_mem_offset) | |
1496 | found_isa_hole = 1; | |
a2d2e1ec | 1497 | } |
a2d2e1ec BH |
1498 | } |
1499 | ||
84d727a1 BH |
1500 | /* Handle ISA memory hole if not already covered */ |
1501 | if (j <= 1 && !found_isa_hole && hose->isa_mem_size) | |
1502 | if (ppc4xx_setup_one_pciex_POM(port, hose, mbase, | |
1503 | hose->isa_mem_phys, 0, | |
1504 | hose->isa_mem_size, 0, j) == 0) | |
1505 | printk(KERN_INFO "%s: Legacy ISA memory support enabled\n", | |
1506 | hose->dn->full_name); | |
1507 | ||
1508 | /* Configure IO, always 64K starting at 0. We hard wire it to 64K ! | |
1509 | * Note also that it -has- to be region index 2 on this HW | |
1510 | */ | |
1511 | if (hose->io_resource.flags & IORESOURCE_IO) | |
1512 | ppc4xx_setup_one_pciex_POM(port, hose, mbase, | |
1513 | hose->io_base_phys, 0, | |
1514 | 0x10000, IORESOURCE_IO, 2); | |
a2d2e1ec BH |
1515 | } |
1516 | ||
1517 | static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port, | |
1518 | struct pci_controller *hose, | |
1519 | void __iomem *mbase, | |
1520 | struct resource *res) | |
1521 | { | |
1522 | resource_size_t size = res->end - res->start + 1; | |
1523 | u64 sa; | |
1524 | ||
80daac3f SR |
1525 | if (port->endpoint) { |
1526 | resource_size_t ep_addr = 0; | |
1527 | resource_size_t ep_size = 32 << 20; | |
1528 | ||
1529 | /* Currently we map a fixed 64MByte window to PLB address | |
1530 | * 0 (SDRAM). This should probably be configurable via a dts | |
1531 | * property. | |
1532 | */ | |
1533 | ||
1534 | /* Calculate window size */ | |
d258e64e | 1535 | sa = (0xffffffffffffffffull << ilog2(ep_size)); |
80daac3f SR |
1536 | |
1537 | /* Setup BAR0 */ | |
1538 | out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); | |
1539 | out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) | | |
1540 | PCI_BASE_ADDRESS_MEM_TYPE_64); | |
a2d2e1ec | 1541 | |
80daac3f SR |
1542 | /* Disable BAR1 & BAR2 */ |
1543 | out_le32(mbase + PECFG_BAR1MPA, 0); | |
1544 | out_le32(mbase + PECFG_BAR2HMPA, 0); | |
1545 | out_le32(mbase + PECFG_BAR2LMPA, 0); | |
a2d2e1ec | 1546 | |
80daac3f SR |
1547 | out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa)); |
1548 | out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa)); | |
1549 | ||
1550 | out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr)); | |
1551 | out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr)); | |
1552 | } else { | |
1553 | /* Calculate window size */ | |
d258e64e | 1554 | sa = (0xffffffffffffffffull << ilog2(size)); |
80daac3f SR |
1555 | if (res->flags & IORESOURCE_PREFETCH) |
1556 | sa |= 0x8; | |
1557 | ||
1558 | out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); | |
1559 | out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa)); | |
1560 | ||
1561 | /* The setup of the split looks weird to me ... let's see | |
1562 | * if it works | |
1563 | */ | |
1564 | out_le32(mbase + PECFG_PIM0LAL, 0x00000000); | |
1565 | out_le32(mbase + PECFG_PIM0LAH, 0x00000000); | |
1566 | out_le32(mbase + PECFG_PIM1LAL, 0x00000000); | |
1567 | out_le32(mbase + PECFG_PIM1LAH, 0x00000000); | |
1568 | out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); | |
1569 | out_le32(mbase + PECFG_PIM01SAL, 0x00000000); | |
1570 | ||
1571 | out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start)); | |
1572 | out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start)); | |
1573 | } | |
a2d2e1ec BH |
1574 | |
1575 | /* Enable inbound mapping */ | |
1576 | out_le32(mbase + PECFG_PIMEN, 0x1); | |
1577 | ||
a2d2e1ec BH |
1578 | /* Enable I/O, Mem, and Busmaster cycles */ |
1579 | out_le16(mbase + PCI_COMMAND, | |
1580 | in_le16(mbase + PCI_COMMAND) | | |
1581 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
1582 | } | |
1583 | ||
1584 | static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port) | |
1585 | { | |
1586 | struct resource dma_window; | |
1587 | struct pci_controller *hose = NULL; | |
1588 | const int *bus_range; | |
1589 | int primary = 0, busses; | |
1590 | void __iomem *mbase = NULL, *cfg_data = NULL; | |
80daac3f SR |
1591 | const u32 *pval; |
1592 | u32 val; | |
a2d2e1ec BH |
1593 | |
1594 | /* Check if primary bridge */ | |
1595 | if (of_get_property(port->node, "primary", NULL)) | |
1596 | primary = 1; | |
1597 | ||
1598 | /* Get bus range if any */ | |
1599 | bus_range = of_get_property(port->node, "bus-range", NULL); | |
1600 | ||
1601 | /* Allocate the host controller data structure */ | |
1602 | hose = pcibios_alloc_controller(port->node); | |
1603 | if (!hose) | |
1604 | goto fail; | |
1605 | ||
1606 | /* We stick the port number in "indirect_type" so the config space | |
1607 | * ops can retrieve the port data structure easily | |
1608 | */ | |
1609 | hose->indirect_type = port->index; | |
1610 | ||
1611 | /* Get bus range */ | |
1612 | hose->first_busno = bus_range ? bus_range[0] : 0x0; | |
1613 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
1614 | ||
1615 | /* Because of how big mapping the config space is (1M per bus), we | |
1616 | * limit how many busses we support. In the long run, we could replace | |
1617 | * that with something akin to kmap_atomic instead. We set aside 1 bus | |
1618 | * for the host itself too. | |
1619 | */ | |
1620 | busses = hose->last_busno - hose->first_busno; /* This is off by 1 */ | |
1621 | if (busses > MAX_PCIE_BUS_MAPPED) { | |
1622 | busses = MAX_PCIE_BUS_MAPPED; | |
1623 | hose->last_busno = hose->first_busno + busses; | |
1624 | } | |
1625 | ||
80daac3f SR |
1626 | if (!port->endpoint) { |
1627 | /* Only map the external config space in cfg_data for | |
1628 | * PCIe root-complexes. External space is 1M per bus | |
1629 | */ | |
1630 | cfg_data = ioremap(port->cfg_space.start + | |
1631 | (hose->first_busno + 1) * 0x100000, | |
1632 | busses * 0x100000); | |
1633 | if (cfg_data == NULL) { | |
1634 | printk(KERN_ERR "%s: Can't map external config space !", | |
1635 | port->node->full_name); | |
1636 | goto fail; | |
1637 | } | |
1638 | hose->cfg_data = cfg_data; | |
1639 | } | |
1640 | ||
1641 | /* Always map the host config space in cfg_addr. | |
1642 | * Internal space is 4K | |
a2d2e1ec | 1643 | */ |
a2d2e1ec | 1644 | mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); |
80daac3f SR |
1645 | if (mbase == NULL) { |
1646 | printk(KERN_ERR "%s: Can't map internal config space !", | |
a2d2e1ec BH |
1647 | port->node->full_name); |
1648 | goto fail; | |
1649 | } | |
a2d2e1ec BH |
1650 | hose->cfg_addr = mbase; |
1651 | ||
1652 | pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name, | |
1653 | hose->first_busno, hose->last_busno); | |
1654 | pr_debug(" config space mapped at: root @0x%p, other @0x%p\n", | |
1655 | hose->cfg_addr, hose->cfg_data); | |
1656 | ||
1657 | /* Setup config space */ | |
1658 | hose->ops = &ppc4xx_pciex_pci_ops; | |
1659 | port->hose = hose; | |
1660 | mbase = (void __iomem *)hose->cfg_addr; | |
1661 | ||
80daac3f SR |
1662 | if (!port->endpoint) { |
1663 | /* | |
1664 | * Set bus numbers on our root port | |
1665 | */ | |
1666 | out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno); | |
1667 | out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1); | |
1668 | out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno); | |
1669 | } | |
a2d2e1ec BH |
1670 | |
1671 | /* | |
1672 | * OMRs are already reset, also disable PIMs | |
1673 | */ | |
1674 | out_le32(mbase + PECFG_PIMEN, 0); | |
1675 | ||
1676 | /* Parse outbound mapping resources */ | |
1677 | pci_process_bridge_OF_ranges(hose, port->node, primary); | |
1678 | ||
1679 | /* Parse inbound mapping resources */ | |
1680 | if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0) | |
1681 | goto fail; | |
1682 | ||
1683 | /* Configure outbound ranges POMs */ | |
1684 | ppc4xx_configure_pciex_POMs(port, hose, mbase); | |
1685 | ||
1686 | /* Configure inbound ranges PIMs */ | |
1687 | ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window); | |
1688 | ||
1689 | /* The root complex doesn't show up if we don't set some vendor | |
80daac3f SR |
1690 | * and device IDs into it. The defaults below are the same bogus |
1691 | * one that the initial code in arch/ppc had. This can be | |
1692 | * overwritten by setting the "vendor-id/device-id" properties | |
1693 | * in the pciex node. | |
a2d2e1ec | 1694 | */ |
a2d2e1ec | 1695 | |
80daac3f SR |
1696 | /* Get the (optional) vendor-/device-id from the device-tree */ |
1697 | pval = of_get_property(port->node, "vendor-id", NULL); | |
1698 | if (pval) { | |
1699 | val = *pval; | |
1700 | } else { | |
1701 | if (!port->endpoint) | |
1702 | val = 0xaaa0 + port->index; | |
1703 | else | |
1704 | val = 0xeee0 + port->index; | |
1705 | } | |
1706 | out_le16(mbase + 0x200, val); | |
1707 | ||
1708 | pval = of_get_property(port->node, "device-id", NULL); | |
1709 | if (pval) { | |
1710 | val = *pval; | |
1711 | } else { | |
1712 | if (!port->endpoint) | |
1713 | val = 0xbed0 + port->index; | |
1714 | else | |
1715 | val = 0xfed0 + port->index; | |
1716 | } | |
1717 | out_le16(mbase + 0x202, val); | |
1718 | ||
1719 | if (!port->endpoint) { | |
1720 | /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ | |
1721 | out_le32(mbase + 0x208, 0x06040001); | |
1722 | ||
1723 | printk(KERN_INFO "PCIE%d: successfully set as root-complex\n", | |
1724 | port->index); | |
1725 | } else { | |
1726 | /* Set Class Code to Processor/PPC */ | |
1727 | out_le32(mbase + 0x208, 0x0b200001); | |
1728 | ||
1729 | printk(KERN_INFO "PCIE%d: successfully set as endpoint\n", | |
1730 | port->index); | |
1731 | } | |
a2d2e1ec | 1732 | |
a2d2e1ec BH |
1733 | return; |
1734 | fail: | |
1735 | if (hose) | |
1736 | pcibios_free_controller(hose); | |
1737 | if (cfg_data) | |
1738 | iounmap(cfg_data); | |
1739 | if (mbase) | |
1740 | iounmap(mbase); | |
1741 | } | |
1742 | ||
5738ec6d BH |
1743 | static void __init ppc4xx_probe_pciex_bridge(struct device_node *np) |
1744 | { | |
a2d2e1ec BH |
1745 | struct ppc4xx_pciex_port *port; |
1746 | const u32 *pval; | |
1747 | int portno; | |
1748 | unsigned int dcrs; | |
80daac3f | 1749 | const char *val; |
a2d2e1ec BH |
1750 | |
1751 | /* First, proceed to core initialization as we assume there's | |
1752 | * only one PCIe core in the system | |
1753 | */ | |
1754 | if (ppc4xx_pciex_check_core_init(np)) | |
1755 | return; | |
1756 | ||
1757 | /* Get the port number from the device-tree */ | |
1758 | pval = of_get_property(np, "port", NULL); | |
1759 | if (pval == NULL) { | |
1760 | printk(KERN_ERR "PCIE: Can't find port number for %s\n", | |
1761 | np->full_name); | |
1762 | return; | |
1763 | } | |
1764 | portno = *pval; | |
1765 | if (portno >= ppc4xx_pciex_port_count) { | |
1766 | printk(KERN_ERR "PCIE: port number out of range for %s\n", | |
1767 | np->full_name); | |
1768 | return; | |
1769 | } | |
1770 | port = &ppc4xx_pciex_ports[portno]; | |
1771 | port->index = portno; | |
995ada8d SR |
1772 | |
1773 | /* | |
1774 | * Check if device is enabled | |
1775 | */ | |
1776 | if (!of_device_is_available(np)) { | |
1777 | printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index); | |
1778 | return; | |
1779 | } | |
1780 | ||
a2d2e1ec BH |
1781 | port->node = of_node_get(np); |
1782 | pval = of_get_property(np, "sdr-base", NULL); | |
1783 | if (pval == NULL) { | |
1784 | printk(KERN_ERR "PCIE: missing sdr-base for %s\n", | |
1785 | np->full_name); | |
1786 | return; | |
1787 | } | |
1788 | port->sdr_base = *pval; | |
1789 | ||
80daac3f SR |
1790 | /* Check if device_type property is set to "pci" or "pci-endpoint". |
1791 | * Resulting from this setup this PCIe port will be configured | |
1792 | * as root-complex or as endpoint. | |
1793 | */ | |
1794 | val = of_get_property(port->node, "device_type", NULL); | |
1795 | if (!strcmp(val, "pci-endpoint")) { | |
1796 | port->endpoint = 1; | |
1797 | } else if (!strcmp(val, "pci")) { | |
1798 | port->endpoint = 0; | |
1799 | } else { | |
1800 | printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n", | |
1801 | np->full_name); | |
1802 | return; | |
1803 | } | |
035ee428 | 1804 | |
a2d2e1ec BH |
1805 | /* Fetch config space registers address */ |
1806 | if (of_address_to_resource(np, 0, &port->cfg_space)) { | |
1807 | printk(KERN_ERR "%s: Can't get PCI-E config space !", | |
1808 | np->full_name); | |
1809 | return; | |
1810 | } | |
1811 | /* Fetch host bridge internal registers address */ | |
1812 | if (of_address_to_resource(np, 1, &port->utl_regs)) { | |
1813 | printk(KERN_ERR "%s: Can't get UTL register base !", | |
1814 | np->full_name); | |
1815 | return; | |
1816 | } | |
1817 | ||
1818 | /* Map DCRs */ | |
1819 | dcrs = dcr_resource_start(np, 0); | |
1820 | if (dcrs == 0) { | |
1821 | printk(KERN_ERR "%s: Can't get DCR register base !", | |
1822 | np->full_name); | |
1823 | return; | |
1824 | } | |
1825 | port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); | |
1826 | ||
1827 | /* Initialize the port specific registers */ | |
035ee428 BH |
1828 | if (ppc4xx_pciex_port_init(port)) { |
1829 | printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index); | |
a2d2e1ec | 1830 | return; |
035ee428 | 1831 | } |
a2d2e1ec BH |
1832 | |
1833 | /* Setup the linux hose data structure */ | |
1834 | ppc4xx_pciex_port_setup_hose(port); | |
5738ec6d BH |
1835 | } |
1836 | ||
a2d2e1ec BH |
1837 | #endif /* CONFIG_PPC4xx_PCI_EXPRESS */ |
1838 | ||
5738ec6d BH |
1839 | static int __init ppc4xx_pci_find_bridges(void) |
1840 | { | |
1841 | struct device_node *np; | |
1842 | ||
41b6a085 BH |
1843 | ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0; |
1844 | ||
a2d2e1ec | 1845 | #ifdef CONFIG_PPC4xx_PCI_EXPRESS |
5738ec6d BH |
1846 | for_each_compatible_node(np, NULL, "ibm,plb-pciex") |
1847 | ppc4xx_probe_pciex_bridge(np); | |
a2d2e1ec | 1848 | #endif |
5738ec6d BH |
1849 | for_each_compatible_node(np, NULL, "ibm,plb-pcix") |
1850 | ppc4xx_probe_pcix_bridge(np); | |
1851 | for_each_compatible_node(np, NULL, "ibm,plb-pci") | |
1852 | ppc4xx_probe_pci_bridge(np); | |
1853 | ||
1854 | return 0; | |
1855 | } | |
1856 | arch_initcall(ppc4xx_pci_find_bridges); | |
1857 |