[linux-2.6-block.git] / arch / powerpc / sysdev / mv64x60_pic.c

/*
 * Interrupt handling for Marvell mv64360/mv64460 host bridges (Discovery)
 *
 * Author: Dale Farnsworth <dale@farnsworth.org>
 *
 * 2007 (c) MontaVista, Software, Inc.  This file is licensed under
 * the terms of the GNU General Public License version 2.  This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>

#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/irq.h>

#include "mv64x60.h"

/* Interrupt Controller Interface Registers */
#define MV64X60_IC_MAIN_CAUSE_LO	0x0004
#define MV64X60_IC_MAIN_CAUSE_HI	0x000c
#define MV64X60_IC_CPU0_INTR_MASK_LO	0x0014
#define MV64X60_IC_CPU0_INTR_MASK_HI	0x001c
#define MV64X60_IC_CPU0_SELECT_CAUSE	0x0024

#define MV64X60_HIGH_GPP_GROUPS		0x0f000000
#define MV64X60_SELECT_CAUSE_HIGH	0x40000000

/* General Purpose Pins Controller Interface Registers */
#define MV64x60_GPP_INTR_CAUSE		0x0008
#define MV64x60_GPP_INTR_MASK		0x000c

#define MV64x60_LEVEL1_LOW		0
#define MV64x60_LEVEL1_HIGH		1
#define MV64x60_LEVEL1_GPP		2

#define MV64x60_LEVEL1_MASK		0x00000060
#define MV64x60_LEVEL1_OFFSET		5

#define MV64x60_LEVEL2_MASK		0x0000001f

#define MV64x60_NUM_IRQS		96

static DEFINE_SPINLOCK(mv64x60_lock);

static void __iomem *mv64x60_irq_reg_base;
static void __iomem *mv64x60_gpp_reg_base;

/*
 * Interrupt Controller Handling
 *
 * The interrupt controller handles three groups of interrupts:
 *   main low:	IRQ0-IRQ31
 *   main high:	IRQ32-IRQ63
 *   gpp:	IRQ64-IRQ95
 *
 * This code handles interrupts in two levels.  Level 1 selects the
 * interrupt group, and level 2 selects an IRQ within that group.
 * Each group has its own irq_chip structure.
 */

static u32 mv64x60_cached_low_mask;
static u32 mv64x60_cached_high_mask = MV64X60_HIGH_GPP_GROUPS;
static u32 mv64x60_cached_gpp_mask;

static struct irq_domain *mv64x60_irq_host;

/*
 * mv64x60_chip_low functions
 */

static void mv64x60_mask_low(struct irq_data *d)
{
	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
	unsigned long flags;

	spin_lock_irqsave(&mv64x60_lock, flags);
	mv64x60_cached_low_mask &= ~(1 << level2);
	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
		 mv64x60_cached_low_mask);
	spin_unlock_irqrestore(&mv64x60_lock, flags);
	(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
}

static void mv64x60_unmask_low(struct irq_data *d)
{
	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
	unsigned long flags;

	spin_lock_irqsave(&mv64x60_lock, flags);
	mv64x60_cached_low_mask |= 1 << level2;
	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
		 mv64x60_cached_low_mask);
	spin_unlock_irqrestore(&mv64x60_lock, flags);
	(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
}

static struct irq_chip mv64x60_chip_low = {
	.name		= "mv64x60_low",
	.irq_mask	= mv64x60_mask_low,
	.irq_mask_ack	= mv64x60_mask_low,
	.irq_unmask	= mv64x60_unmask_low,
};

/*
 * mv64x60_chip_high functions
 */

static void mv64x60_mask_high(struct irq_data *d)
{
	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
	unsigned long flags;

	spin_lock_irqsave(&mv64x60_lock, flags);
	mv64x60_cached_high_mask &= ~(1 << level2);
	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
		 mv64x60_cached_high_mask);
	spin_unlock_irqrestore(&mv64x60_lock, flags);
	(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
}

static void mv64x60_unmask_high(struct irq_data *d)
{
	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
	unsigned long flags;

	spin_lock_irqsave(&mv64x60_lock, flags);
	mv64x60_cached_high_mask |= 1 << level2;
	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
		 mv64x60_cached_high_mask);
	spin_unlock_irqrestore(&mv64x60_lock, flags);
	(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
}

static struct irq_chip mv64x60_chip_high = {
	.name		= "mv64x60_high",
	.irq_mask	= mv64x60_mask_high,
	.irq_mask_ack	= mv64x60_mask_high,
	.irq_unmask	= mv64x60_unmask_high,
};

/*
 * mv64x60_chip_gpp functions
 */

static void mv64x60_mask_gpp(struct irq_data *d)
{
	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
	unsigned long flags;

	spin_lock_irqsave(&mv64x60_lock, flags);
	mv64x60_cached_gpp_mask &= ~(1 << level2);
	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
		 mv64x60_cached_gpp_mask);
	spin_unlock_irqrestore(&mv64x60_lock, flags);
	(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
}

static void mv64x60_mask_ack_gpp(struct irq_data *d)
{
	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
	unsigned long flags;

	spin_lock_irqsave(&mv64x60_lock, flags);
	mv64x60_cached_gpp_mask &= ~(1 << level2);
	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
		 mv64x60_cached_gpp_mask);
	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE,
		 ~(1 << level2));
	spin_unlock_irqrestore(&mv64x60_lock, flags);
	(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE);
}

static void mv64x60_unmask_gpp(struct irq_data *d)
{
	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
	unsigned long flags;

	spin_lock_irqsave(&mv64x60_lock, flags);
	mv64x60_cached_gpp_mask |= 1 << level2;
	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
		 mv64x60_cached_gpp_mask);
	spin_unlock_irqrestore(&mv64x60_lock, flags);
	(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
}

static struct irq_chip mv64x60_chip_gpp = {
	.name		= "mv64x60_gpp",
	.irq_mask	= mv64x60_mask_gpp,
	.irq_mask_ack	= mv64x60_mask_ack_gpp,
	.irq_unmask	= mv64x60_unmask_gpp,
};

/*
 * mv64x60_host_ops functions
 */

static struct irq_chip *mv64x60_chips[] = {
	[MV64x60_LEVEL1_LOW]  = &mv64x60_chip_low,
	[MV64x60_LEVEL1_HIGH] = &mv64x60_chip_high,
	[MV64x60_LEVEL1_GPP]  = &mv64x60_chip_gpp,
};

static int mv64x60_host_map(struct irq_domain *h, unsigned int virq,
			  irq_hw_number_t hwirq)
{
	int level1;

	irq_set_status_flags(virq, IRQ_LEVEL);

	level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
	BUG_ON(level1 > MV64x60_LEVEL1_GPP);
	irq_set_chip_and_handler(virq, mv64x60_chips[level1],
				 handle_level_irq);

	return 0;
}

static const struct irq_domain_ops mv64x60_host_ops = {
	.map   = mv64x60_host_map,
};

/*
 * Global functions
 */

void __init mv64x60_init_irq(void)
{
	struct device_node *np;
	phys_addr_t paddr;
	unsigned int size;
	const unsigned int *reg;
	unsigned long flags;

	np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
	reg = of_get_property(np, "reg", &size);
	paddr = of_translate_address(np, reg);
	mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
	of_node_put(np);

	np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-pic");
	reg = of_get_property(np, "reg", &size);
	paddr = of_translate_address(np, reg);
	mv64x60_irq_reg_base = ioremap(paddr, reg[1]);

	mv64x60_irq_host = irq_domain_add_linear(np, MV64x60_NUM_IRQS,
					  &mv64x60_host_ops, NULL);

	spin_lock_irqsave(&mv64x60_lock, flags);
	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
		 mv64x60_cached_gpp_mask);
	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
		 mv64x60_cached_low_mask);
	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
		 mv64x60_cached_high_mask);

	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE, 0);
	out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_LO, 0);
	out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_HI, 0);
	spin_unlock_irqrestore(&mv64x60_lock, flags);
}

unsigned int mv64x60_get_irq(void)
{
	u32 cause;
	int level1;
	irq_hw_number_t hwirq;
	int virq = NO_IRQ;

	cause = in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_SELECT_CAUSE);
	if (cause & MV64X60_SELECT_CAUSE_HIGH) {
		cause &= mv64x60_cached_high_mask;
		level1 = MV64x60_LEVEL1_HIGH;
		if (cause & MV64X60_HIGH_GPP_GROUPS) {
			cause = in_le32(mv64x60_gpp_reg_base +
					MV64x60_GPP_INTR_CAUSE);
			cause &= mv64x60_cached_gpp_mask;
			level1 = MV64x60_LEVEL1_GPP;
		}
	} else {
		cause &= mv64x60_cached_low_mask;
		level1 = MV64x60_LEVEL1_LOW;
	}
	if (cause) {
		hwirq = (level1 << MV64x60_LEVEL1_OFFSET) | __ilog2(cause);
		virq = irq_linear_revmap(mv64x60_irq_host, hwirq);
	}

	return virq;
}
Commit	Line	Data
e44b8941 DF	1	/*
	2	* Interrupt handling for Marvell mv64360/mv64460 host bridges (Discovery)
	3	*
	4	* Author: Dale Farnsworth <dale@farnsworth.org>
	5	*
	6	* 2007 (c) MontaVista, Software, Inc. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This program
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11
	12	#include <linux/stddef.h>
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/irq.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/spinlock.h>
	18
	19	#include <asm/byteorder.h>
	20	#include <asm/io.h>
	21	#include <asm/prom.h>
	22	#include <asm/irq.h>
	23
	24	#include "mv64x60.h"
	25
	26	/* Interrupt Controller Interface Registers */
	27	#define MV64X60_IC_MAIN_CAUSE_LO 0x0004
	28	#define MV64X60_IC_MAIN_CAUSE_HI 0x000c
	29	#define MV64X60_IC_CPU0_INTR_MASK_LO 0x0014
	30	#define MV64X60_IC_CPU0_INTR_MASK_HI 0x001c
	31	#define MV64X60_IC_CPU0_SELECT_CAUSE 0x0024
	32
	33	#define MV64X60_HIGH_GPP_GROUPS 0x0f000000
	34	#define MV64X60_SELECT_CAUSE_HIGH 0x40000000
	35
	36	/* General Purpose Pins Controller Interface Registers */
	37	#define MV64x60_GPP_INTR_CAUSE 0x0008
	38	#define MV64x60_GPP_INTR_MASK 0x000c
	39
	40	#define MV64x60_LEVEL1_LOW 0
	41	#define MV64x60_LEVEL1_HIGH 1
	42	#define MV64x60_LEVEL1_GPP 2
	43
	44	#define MV64x60_LEVEL1_MASK 0x00000060
	45	#define MV64x60_LEVEL1_OFFSET 5
	46
	47	#define MV64x60_LEVEL2_MASK 0x0000001f
	48
	49	#define MV64x60_NUM_IRQS 96
	50
	51	static DEFINE_SPINLOCK(mv64x60_lock);
	52
	53	static void __iomem *mv64x60_irq_reg_base;
	54	static void __iomem *mv64x60_gpp_reg_base;
	55
	56	/*
	57	* Interrupt Controller Handling
	58	*
	59	* The interrupt controller handles three groups of interrupts:
	60	* main low: IRQ0-IRQ31
	61	* main high: IRQ32-IRQ63
	62	* gpp: IRQ64-IRQ95
	63	*
	64	* This code handles interrupts in two levels. Level 1 selects the
65	* interrupt group, and level 2 selects an IRQ within that group.
66	* Each group has its own irq_chip structure.
67	*/
68
69	static u32 mv64x60_cached_low_mask;
70	static u32 mv64x60_cached_high_mask = MV64X60_HIGH_GPP_GROUPS;
71	static u32 mv64x60_cached_gpp_mask;
72
bae1d8f1	73	static struct irq_domain *mv64x60_irq_host;
e44b8941 DF	74
	75	/*
	76	* mv64x60_chip_low functions
	77	*/
	78
41f3863b	79	static void mv64x60_mask_low(struct irq_data *d)
e44b8941	80	{
476eb491	81	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
e44b8941 DF	82	unsigned long flags;
	83
	84	spin_lock_irqsave(&mv64x60_lock, flags);
	85	mv64x60_cached_low_mask &= ~(1 << level2);
	86	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
	87	mv64x60_cached_low_mask);
	88	spin_unlock_irqrestore(&mv64x60_lock, flags);
	89	(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
	90	}
	91
41f3863b	92	static void mv64x60_unmask_low(struct irq_data *d)
e44b8941	93	{
476eb491	94	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
e44b8941 DF	95	unsigned long flags;
	96
	97	spin_lock_irqsave(&mv64x60_lock, flags);
	98	mv64x60_cached_low_mask \|= 1 << level2;
	99	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
	100	mv64x60_cached_low_mask);
	101	spin_unlock_irqrestore(&mv64x60_lock, flags);
	102	(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
	103	}
	104
	105	static struct irq_chip mv64x60_chip_low = {
	106	.name = "mv64x60_low",
41f3863b LB	107	.irq_mask = mv64x60_mask_low,
	108	.irq_mask_ack = mv64x60_mask_low,
	109	.irq_unmask = mv64x60_unmask_low,
e44b8941 DF	110	};
	111
	112	/*
	113	* mv64x60_chip_high functions
	114	*/
	115
41f3863b	116	static void mv64x60_mask_high(struct irq_data *d)
e44b8941	117	{
476eb491	118	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
e44b8941 DF	119	unsigned long flags;
	120
	121	spin_lock_irqsave(&mv64x60_lock, flags);
	122	mv64x60_cached_high_mask &= ~(1 << level2);
	123	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
	124	mv64x60_cached_high_mask);
	125	spin_unlock_irqrestore(&mv64x60_lock, flags);
	126	(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
	127	}
	128
41f3863b	129	static void mv64x60_unmask_high(struct irq_data *d)
e44b8941	130	{
476eb491	131	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
e44b8941 DF	132	unsigned long flags;
	133
	134	spin_lock_irqsave(&mv64x60_lock, flags);
	135	mv64x60_cached_high_mask \|= 1 << level2;
	136	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
	137	mv64x60_cached_high_mask);
	138	spin_unlock_irqrestore(&mv64x60_lock, flags);
	139	(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
	140	}
	141
	142	static struct irq_chip mv64x60_chip_high = {
	143	.name = "mv64x60_high",
41f3863b LB	144	.irq_mask = mv64x60_mask_high,
	145	.irq_mask_ack = mv64x60_mask_high,
	146	.irq_unmask = mv64x60_unmask_high,
e44b8941 DF	147	};
	148
	149	/*
	150	* mv64x60_chip_gpp functions
	151	*/
	152
41f3863b	153	static void mv64x60_mask_gpp(struct irq_data *d)
e44b8941	154	{
476eb491	155	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
e44b8941 DF	156	unsigned long flags;
	157
	158	spin_lock_irqsave(&mv64x60_lock, flags);
	159	mv64x60_cached_gpp_mask &= ~(1 << level2);
	160	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
	161	mv64x60_cached_gpp_mask);
	162	spin_unlock_irqrestore(&mv64x60_lock, flags);
	163	(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
	164	}
	165
41f3863b	166	static void mv64x60_mask_ack_gpp(struct irq_data *d)
e44b8941	167	{
476eb491	168	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
e44b8941 DF	169	unsigned long flags;
	170
	171	spin_lock_irqsave(&mv64x60_lock, flags);
	172	mv64x60_cached_gpp_mask &= ~(1 << level2);
	173	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
	174	mv64x60_cached_gpp_mask);
	175	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE,
	176	~(1 << level2));
	177	spin_unlock_irqrestore(&mv64x60_lock, flags);
	178	(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE);
	179	}
	180
41f3863b	181	static void mv64x60_unmask_gpp(struct irq_data *d)
e44b8941	182	{
476eb491	183	int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
e44b8941 DF	184	unsigned long flags;
	185
	186	spin_lock_irqsave(&mv64x60_lock, flags);
	187	mv64x60_cached_gpp_mask \|= 1 << level2;
	188	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
	189	mv64x60_cached_gpp_mask);
	190	spin_unlock_irqrestore(&mv64x60_lock, flags);
	191	(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
	192	}
	193
	194	static struct irq_chip mv64x60_chip_gpp = {
	195	.name = "mv64x60_gpp",
41f3863b LB	196	.irq_mask = mv64x60_mask_gpp,
	197	.irq_mask_ack = mv64x60_mask_ack_gpp,
	198	.irq_unmask = mv64x60_unmask_gpp,
e44b8941 DF	199	};
	200
	201	/*
	202	* mv64x60_host_ops functions
	203	*/
	204
e44b8941 DF	205	static struct irq_chip *mv64x60_chips[] = {
	206	[MV64x60_LEVEL1_LOW] = &mv64x60_chip_low,
	207	[MV64x60_LEVEL1_HIGH] = &mv64x60_chip_high,
	208	[MV64x60_LEVEL1_GPP] = &mv64x60_chip_gpp,
	209	};
	210
bae1d8f1	211	static int mv64x60_host_map(struct irq_domain *h, unsigned int virq,
e44b8941 DF	212	irq_hw_number_t hwirq)
	213	{
	214	int level1;
	215
98488db9	216	irq_set_status_flags(virq, IRQ_LEVEL);
e44b8941 DF	217
	218	level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
	219	BUG_ON(level1 > MV64x60_LEVEL1_GPP);
ec775d0e TG	220	irq_set_chip_and_handler(virq, mv64x60_chips[level1],
ec775d0e TG	221	handle_level_irq);
e44b8941 DF	222
	223	return 0;
	224	}
	225
202648a6	226	static const struct irq_domain_ops mv64x60_host_ops = {
e44b8941 DF	227	.map = mv64x60_host_map,
	228	};
	229
	230	/*
	231	* Global functions
	232	*/
	233
	234	void __init mv64x60_init_irq(void)
	235	{
	236	struct device_node *np;
	237	phys_addr_t paddr;
	238	unsigned int size;
	239	const unsigned int *reg;
	240	unsigned long flags;
	241
a1810b44	242	np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
e44b8941 DF	243	reg = of_get_property(np, "reg", &size);
	244	paddr = of_translate_address(np, reg);
	245	mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
	246	of_node_put(np);
	247
a1810b44	248	np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-pic");
e44b8941 DF	249	reg = of_get_property(np, "reg", &size);
e44b8941 DF	250	paddr = of_translate_address(np, reg);
e44b8941 DF	251	mv64x60_irq_reg_base = ioremap(paddr, reg[1]);
e44b8941 DF	252
a8db8cf0 GL	253	mv64x60_irq_host = irq_domain_add_linear(np, MV64x60_NUM_IRQS,
a8db8cf0 GL	254	&mv64x60_host_ops, NULL);
e44b8941	255
e44b8941 DF	256	spin_lock_irqsave(&mv64x60_lock, flags);
	257	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
	258	mv64x60_cached_gpp_mask);
	259	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
	260	mv64x60_cached_low_mask);
	261	out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
	262	mv64x60_cached_high_mask);
	263
	264	out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE, 0);
	265	out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_LO, 0);
	266	out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_HI, 0);
	267	spin_unlock_irqrestore(&mv64x60_lock, flags);
	268	}
	269
	270	unsigned int mv64x60_get_irq(void)
	271	{
	272	u32 cause;
	273	int level1;
	274	irq_hw_number_t hwirq;
	275	int virq = NO_IRQ;
	276
	277	cause = in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_SELECT_CAUSE);
	278	if (cause & MV64X60_SELECT_CAUSE_HIGH) {
	279	cause &= mv64x60_cached_high_mask;
	280	level1 = MV64x60_LEVEL1_HIGH;
	281	if (cause & MV64X60_HIGH_GPP_GROUPS) {
	282	cause = in_le32(mv64x60_gpp_reg_base +
	283	MV64x60_GPP_INTR_CAUSE);
	284	cause &= mv64x60_cached_gpp_mask;
	285	level1 = MV64x60_LEVEL1_GPP;
	286	}
	287	} else {
	288	cause &= mv64x60_cached_low_mask;
	289	level1 = MV64x60_LEVEL1_LOW;
	290	}
	291	if (cause) {
	292	hwirq = (level1 << MV64x60_LEVEL1_OFFSET) \| __ilog2(cause);
	293	virq = irq_linear_revmap(mv64x60_irq_host, hwirq);
	294	}
	295
	296	return virq;
	297	}