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05af7bd2 ME |
1 | /* |
2 | * Copyright 2006, Segher Boessenkool, IBM Corporation. | |
3 | * Copyright 2006-2007, Michael Ellerman, IBM Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; version 2 of the | |
8 | * License. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include <linux/irq.h> | |
13 | #include <linux/bootmem.h> | |
14 | #include <linux/msi.h> | |
15 | #include <asm/mpic.h> | |
16 | #include <asm/prom.h> | |
17 | #include <asm/hw_irq.h> | |
18 | #include <asm/ppc-pci.h> | |
25235f71 | 19 | #include <asm/msi_bitmap.h> |
05af7bd2 ME |
20 | |
21 | #include "mpic.h" | |
22 | ||
23 | /* A bit ugly, can we get this from the pci_dev somehow? */ | |
24 | static struct mpic *msi_mpic; | |
25 | ||
26 | static void mpic_u3msi_mask_irq(unsigned int irq) | |
27 | { | |
28 | mask_msi_irq(irq); | |
29 | mpic_mask_irq(irq); | |
30 | } | |
31 | ||
32 | static void mpic_u3msi_unmask_irq(unsigned int irq) | |
33 | { | |
34 | mpic_unmask_irq(irq); | |
35 | unmask_msi_irq(irq); | |
36 | } | |
37 | ||
38 | static struct irq_chip mpic_u3msi_chip = { | |
39 | .shutdown = mpic_u3msi_mask_irq, | |
40 | .mask = mpic_u3msi_mask_irq, | |
41 | .unmask = mpic_u3msi_unmask_irq, | |
42 | .eoi = mpic_end_irq, | |
43 | .set_type = mpic_set_irq_type, | |
17b5ee04 | 44 | .set_affinity = mpic_set_affinity, |
05af7bd2 ME |
45 | .typename = "MPIC-U3MSI", |
46 | }; | |
47 | ||
48 | static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos) | |
49 | { | |
50 | u8 flags; | |
51 | u32 tmp; | |
52 | u64 addr; | |
53 | ||
54 | pci_read_config_byte(pdev, pos + HT_MSI_FLAGS, &flags); | |
55 | ||
56 | if (flags & HT_MSI_FLAGS_FIXED) | |
57 | return HT_MSI_FIXED_ADDR; | |
58 | ||
59 | pci_read_config_dword(pdev, pos + HT_MSI_ADDR_LO, &tmp); | |
60 | addr = tmp & HT_MSI_ADDR_LO_MASK; | |
61 | pci_read_config_dword(pdev, pos + HT_MSI_ADDR_HI, &tmp); | |
62 | addr = addr | ((u64)tmp << 32); | |
63 | ||
64 | return addr; | |
65 | } | |
66 | ||
67 | static u64 find_ht_magic_addr(struct pci_dev *pdev) | |
68 | { | |
69 | struct pci_bus *bus; | |
70 | unsigned int pos; | |
71 | ||
72 | for (bus = pdev->bus; bus; bus = bus->parent) { | |
73 | pos = pci_find_ht_capability(bus->self, HT_CAPTYPE_MSI_MAPPING); | |
74 | if (pos) | |
75 | return read_ht_magic_addr(bus->self, pos); | |
76 | } | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | static int u3msi_msi_check_device(struct pci_dev *pdev, int nvec, int type) | |
82 | { | |
83 | if (type == PCI_CAP_ID_MSIX) | |
84 | pr_debug("u3msi: MSI-X untested, trying anyway.\n"); | |
85 | ||
86 | /* If we can't find a magic address then MSI ain't gonna work */ | |
87 | if (find_ht_magic_addr(pdev) == 0) { | |
88 | pr_debug("u3msi: no magic address found for %s\n", | |
89 | pci_name(pdev)); | |
90 | return -ENXIO; | |
91 | } | |
92 | ||
93 | return 0; | |
94 | } | |
95 | ||
96 | static void u3msi_teardown_msi_irqs(struct pci_dev *pdev) | |
97 | { | |
98 | struct msi_desc *entry; | |
99 | ||
100 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
101 | if (entry->irq == NO_IRQ) | |
102 | continue; | |
103 | ||
104 | set_irq_msi(entry->irq, NULL); | |
25235f71 ME |
105 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, |
106 | virq_to_hw(entry->irq), 1); | |
05af7bd2 ME |
107 | irq_dispose_mapping(entry->irq); |
108 | } | |
109 | ||
110 | return; | |
111 | } | |
112 | ||
05af7bd2 ME |
113 | static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) |
114 | { | |
05af7bd2 ME |
115 | unsigned int virq; |
116 | struct msi_desc *entry; | |
117 | struct msi_msg msg; | |
21ccdd31 | 118 | u64 addr; |
25235f71 | 119 | int hwirq; |
21ccdd31 ME |
120 | |
121 | addr = find_ht_magic_addr(pdev); | |
122 | msg.address_lo = addr & 0xFFFFFFFF; | |
123 | msg.address_hi = addr >> 32; | |
05af7bd2 ME |
124 | |
125 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
25235f71 ME |
126 | hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 1); |
127 | if (hwirq < 0) { | |
05af7bd2 | 128 | pr_debug("u3msi: failed allocating hwirq\n"); |
25235f71 | 129 | return hwirq; |
05af7bd2 ME |
130 | } |
131 | ||
132 | virq = irq_create_mapping(msi_mpic->irqhost, hwirq); | |
133 | if (virq == NO_IRQ) { | |
25235f71 ME |
134 | pr_debug("u3msi: failed mapping hwirq 0x%x\n", hwirq); |
135 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 1); | |
d9303d66 | 136 | return -ENOSPC; |
05af7bd2 ME |
137 | } |
138 | ||
139 | set_irq_msi(virq, entry); | |
140 | set_irq_chip(virq, &mpic_u3msi_chip); | |
141 | set_irq_type(virq, IRQ_TYPE_EDGE_RISING); | |
142 | ||
25235f71 ME |
143 | pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n", |
144 | virq, hwirq, (unsigned long)addr); | |
21ccdd31 ME |
145 | |
146 | msg.data = hwirq; | |
05af7bd2 ME |
147 | write_msi_msg(virq, &msg); |
148 | ||
149 | hwirq++; | |
150 | } | |
151 | ||
152 | return 0; | |
05af7bd2 ME |
153 | } |
154 | ||
155 | int mpic_u3msi_init(struct mpic *mpic) | |
156 | { | |
157 | int rc; | |
158 | ||
159 | rc = mpic_msi_init_allocator(mpic); | |
160 | if (rc) { | |
161 | pr_debug("u3msi: Error allocating bitmap!\n"); | |
162 | return rc; | |
163 | } | |
164 | ||
165 | pr_debug("u3msi: Registering MPIC U3 MSI callbacks.\n"); | |
166 | ||
167 | BUG_ON(msi_mpic); | |
168 | msi_mpic = mpic; | |
169 | ||
170 | WARN_ON(ppc_md.setup_msi_irqs); | |
171 | ppc_md.setup_msi_irqs = u3msi_setup_msi_irqs; | |
172 | ppc_md.teardown_msi_irqs = u3msi_teardown_msi_irqs; | |
173 | ppc_md.msi_check_device = u3msi_msi_check_device; | |
174 | ||
175 | return 0; | |
176 | } |