[linux-2.6-block.git] / arch / powerpc / sysdev / mpic_timer.c

/*
 * MPIC timer driver
 *
 * Copyright 2013 Freescale Semiconductor, Inc.
 * Author: Dongsheng Wang <Dongsheng.Wang@freescale.com>
 *	   Li Yang <leoli@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/syscore_ops.h>
#include <sysdev/fsl_soc.h>
#include <asm/io.h>

#include <asm/mpic_timer.h>

#define FSL_GLOBAL_TIMER		0x1

/* Clock Ratio
 * Divide by 64 0x00000300
 * Divide by 32 0x00000200
 * Divide by 16 0x00000100
 * Divide by  8 0x00000000 (Hardware default div)
 */
#define MPIC_TIMER_TCR_CLKDIV		0x00000300

#define MPIC_TIMER_TCR_ROVR_OFFSET	24

#define TIMER_STOP			0x80000000
#define GTCCR_TOG			0x80000000
#define TIMERS_PER_GROUP		4
#define MAX_TICKS			(~0U >> 1)
#define MAX_TICKS_CASCADE		(~0U)
#define TIMER_OFFSET(num)		(1 << (TIMERS_PER_GROUP - 1 - num))

struct timer_regs {
	u32	gtccr;
	u32	res0[3];
	u32	gtbcr;
	u32	res1[3];
	u32	gtvpr;
	u32	res2[3];
	u32	gtdr;
	u32	res3[3];
};

struct cascade_priv {
	u32 tcr_value;			/* TCR register: CASC & ROVR value */
	unsigned int cascade_map;	/* cascade map */
	unsigned int timer_num;		/* cascade control timer */
};

struct timer_group_priv {
	struct timer_regs __iomem	*regs;
	struct mpic_timer		timer[TIMERS_PER_GROUP];
	struct list_head		node;
	unsigned int			timerfreq;
	unsigned int			idle;
	unsigned int			flags;
	spinlock_t			lock;
	void __iomem			*group_tcr;
};

static struct cascade_priv cascade_timer[] = {
	/* cascade timer 0 and 1 */
	{0x1, 0xc, 0x1},
	/* cascade timer 1 and 2 */
	{0x2, 0x6, 0x2},
	/* cascade timer 2 and 3 */
	{0x4, 0x3, 0x3}
};

static LIST_HEAD(timer_group_list);

static void convert_ticks_to_time(struct timer_group_priv *priv,
		const u64 ticks, time64_t *time)
{
	*time = (u64)div_u64(ticks, priv->timerfreq);
}

/* the time set by the user is converted to "ticks" */
static int convert_time_to_ticks(struct timer_group_priv *priv,
		time64_t time, u64 *ticks)
{
	u64 max_value;		/* prevent u64 overflow */

	max_value = div_u64(ULLONG_MAX, priv->timerfreq);

	if (time > max_value)
		return -EINVAL;

	*ticks = (u64)time * (u64)priv->timerfreq;

	return 0;
}

/* detect whether there is a cascade timer available */
static struct mpic_timer *detect_idle_cascade_timer(
					struct timer_group_priv *priv)
{
	struct cascade_priv *casc_priv;
	unsigned int map;
	unsigned int array_size = ARRAY_SIZE(cascade_timer);
	unsigned int num;
	unsigned int i;
	unsigned long flags;

	casc_priv = cascade_timer;
	for (i = 0; i < array_size; i++) {
		spin_lock_irqsave(&priv->lock, flags);
		map = casc_priv->cascade_map & priv->idle;
		if (map == casc_priv->cascade_map) {
			num = casc_priv->timer_num;
			priv->timer[num].cascade_handle = casc_priv;

			/* set timer busy */
			priv->idle &= ~casc_priv->cascade_map;
			spin_unlock_irqrestore(&priv->lock, flags);
			return &priv->timer[num];
		}
		spin_unlock_irqrestore(&priv->lock, flags);
		casc_priv++;
	}

	return NULL;
}

static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks,
		unsigned int num)
{
	struct cascade_priv *casc_priv;
	u32 tcr;
	u32 tmp_ticks;
	u32 rem_ticks;

	/* set group tcr reg for cascade */
	casc_priv = priv->timer[num].cascade_handle;
	if (!casc_priv)
		return -EINVAL;

	tcr = casc_priv->tcr_value |
		(casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
	setbits32(priv->group_tcr, tcr);

	tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);

	out_be32(&priv->regs[num].gtccr, 0);
	out_be32(&priv->regs[num].gtbcr, tmp_ticks | TIMER_STOP);

	out_be32(&priv->regs[num - 1].gtccr, 0);
	out_be32(&priv->regs[num - 1].gtbcr, rem_ticks);

	return 0;
}

static struct mpic_timer *get_cascade_timer(struct timer_group_priv *priv,
					u64 ticks)
{
	struct mpic_timer *allocated_timer;

	/* Two cascade timers: Support the maximum time */
	const u64 max_ticks = (u64)MAX_TICKS * (u64)MAX_TICKS_CASCADE;
	int ret;

	if (ticks > max_ticks)
		return NULL;

	/* detect idle timer */
	allocated_timer = detect_idle_cascade_timer(priv);
	if (!allocated_timer)
		return NULL;

	/* set ticks to timer */
	ret = set_cascade_timer(priv, ticks, allocated_timer->num);
	if (ret < 0)
		return NULL;

	return allocated_timer;
}

static struct mpic_timer *get_timer(time64_t time)
{
	struct timer_group_priv *priv;
	struct mpic_timer *timer;

	u64 ticks;
	unsigned int num;
	unsigned int i;
	unsigned long flags;
	int ret;

	list_for_each_entry(priv, &timer_group_list, node) {
		ret = convert_time_to_ticks(priv, time, &ticks);
		if (ret < 0)
			return NULL;

		if (ticks > MAX_TICKS) {
			if (!(priv->flags & FSL_GLOBAL_TIMER))
				return NULL;

			timer = get_cascade_timer(priv, ticks);
			if (!timer)
				continue;

			return timer;
		}

		for (i = 0; i < TIMERS_PER_GROUP; i++) {
			/* one timer: Reverse allocation */
			num = TIMERS_PER_GROUP - 1 - i;
			spin_lock_irqsave(&priv->lock, flags);
			if (priv->idle & (1 << i)) {
				/* set timer busy */
				priv->idle &= ~(1 << i);
				/* set ticks & stop timer */
				out_be32(&priv->regs[num].gtbcr,
					ticks | TIMER_STOP);
				out_be32(&priv->regs[num].gtccr, 0);
				priv->timer[num].cascade_handle = NULL;
				spin_unlock_irqrestore(&priv->lock, flags);
				return &priv->timer[num];
			}
			spin_unlock_irqrestore(&priv->lock, flags);
		}
	}

	return NULL;
}

/**
 * mpic_start_timer - start hardware timer
 * @handle: the timer to be started.
 *
 * It will do ->fn(->dev) callback from the hardware interrupt at
 * the 'time64_t' point in the future.
 */
void mpic_start_timer(struct mpic_timer *handle)
{
	struct timer_group_priv *priv = container_of(handle,
			struct timer_group_priv, timer[handle->num]);

	clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
}
EXPORT_SYMBOL(mpic_start_timer);

/**
 * mpic_stop_timer - stop hardware timer
 * @handle: the timer to be stoped
 *
 * The timer periodically generates an interrupt. Unless user stops the timer.
 */
void mpic_stop_timer(struct mpic_timer *handle)
{
	struct timer_group_priv *priv = container_of(handle,
			struct timer_group_priv, timer[handle->num]);
	struct cascade_priv *casc_priv;

	setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);

	casc_priv = priv->timer[handle->num].cascade_handle;
	if (casc_priv) {
		out_be32(&priv->regs[handle->num].gtccr, 0);
		out_be32(&priv->regs[handle->num - 1].gtccr, 0);
	} else {
		out_be32(&priv->regs[handle->num].gtccr, 0);
	}
}
EXPORT_SYMBOL(mpic_stop_timer);

/**
 * mpic_get_remain_time - get timer time
 * @handle: the timer to be selected.
 * @time: time for timer
 *
 * Query timer remaining time.
 */
void mpic_get_remain_time(struct mpic_timer *handle, time64_t *time)
{
	struct timer_group_priv *priv = container_of(handle,
			struct timer_group_priv, timer[handle->num]);
	struct cascade_priv *casc_priv;

	u64 ticks;
	u32 tmp_ticks;

	casc_priv = priv->timer[handle->num].cascade_handle;
	if (casc_priv) {
		tmp_ticks = in_be32(&priv->regs[handle->num].gtccr);
		tmp_ticks &= ~GTCCR_TOG;
		ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE;
		tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr);
		ticks += tmp_ticks;
	} else {
		ticks = in_be32(&priv->regs[handle->num].gtccr);
		ticks &= ~GTCCR_TOG;
	}

	convert_ticks_to_time(priv, ticks, time);
}
EXPORT_SYMBOL(mpic_get_remain_time);

/**
 * mpic_free_timer - free hardware timer
 * @handle: the timer to be removed.
 *
 * Free the timer.
 *
 * Note: can not be used in interrupt context.
 */
void mpic_free_timer(struct mpic_timer *handle)
{
	struct timer_group_priv *priv = container_of(handle,
			struct timer_group_priv, timer[handle->num]);

	struct cascade_priv *casc_priv;
	unsigned long flags;

	mpic_stop_timer(handle);

	casc_priv = priv->timer[handle->num].cascade_handle;

	free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev);

	spin_lock_irqsave(&priv->lock, flags);
	if (casc_priv) {
		u32 tcr;
		tcr = casc_priv->tcr_value | (casc_priv->tcr_value <<
					MPIC_TIMER_TCR_ROVR_OFFSET);
		clrbits32(priv->group_tcr, tcr);
		priv->idle |= casc_priv->cascade_map;
		priv->timer[handle->num].cascade_handle = NULL;
	} else {
		priv->idle |= TIMER_OFFSET(handle->num);
	}
	spin_unlock_irqrestore(&priv->lock, flags);
}
EXPORT_SYMBOL(mpic_free_timer);

/**
 * mpic_request_timer - get a hardware timer
 * @fn: interrupt handler function
 * @dev: callback function of the data
 * @time: time for timer
 *
 * This executes the "request_irq", returning NULL
 * else "handle" on success.
 */
struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev,
				      time64_t time)
{
	struct mpic_timer *allocated_timer;
	int ret;

	if (list_empty(&timer_group_list))
		return NULL;

	if (time < 0)
		return NULL;

	allocated_timer = get_timer(time);
	if (!allocated_timer)
		return NULL;

	ret = request_irq(allocated_timer->irq, fn,
			IRQF_TRIGGER_LOW, "global-timer", dev);
	if (ret) {
		mpic_free_timer(allocated_timer);
		return NULL;
	}

	allocated_timer->dev = dev;

	return allocated_timer;
}
EXPORT_SYMBOL(mpic_request_timer);

static int timer_group_get_freq(struct device_node *np,
			struct timer_group_priv *priv)
{
	u32 div;

	if (priv->flags & FSL_GLOBAL_TIMER) {
		struct device_node *dn;

		dn = of_find_compatible_node(NULL, NULL, "fsl,mpic");
		if (dn) {
			of_property_read_u32(dn, "clock-frequency",
					&priv->timerfreq);
			of_node_put(dn);
		}
	}

	if (priv->timerfreq <= 0)
		return -EINVAL;

	if (priv->flags & FSL_GLOBAL_TIMER) {
		div = (1 << (MPIC_TIMER_TCR_CLKDIV >> 8)) * 8;
		priv->timerfreq /= div;
	}

	return 0;
}

static int timer_group_get_irq(struct device_node *np,
		struct timer_group_priv *priv)
{
	const u32 all_timer[] = { 0, TIMERS_PER_GROUP };
	const u32 *p;
	u32 offset;
	u32 count;

	unsigned int i;
	unsigned int j;
	unsigned int irq_index = 0;
	unsigned int irq;
	int len;

	p = of_get_property(np, "fsl,available-ranges", &len);
	if (p && len % (2 * sizeof(u32)) != 0) {
		pr_err("%pOF: malformed available-ranges property.\n", np);
		return -EINVAL;
	}

	if (!p) {
		p = all_timer;
		len = sizeof(all_timer);
	}

	len /= 2 * sizeof(u32);

	for (i = 0; i < len; i++) {
		offset = p[i * 2];
		count = p[i * 2 + 1];
		for (j = 0; j < count; j++) {
			irq = irq_of_parse_and_map(np, irq_index);
			if (!irq) {
				pr_err("%pOF: irq parse and map failed.\n", np);
				return -EINVAL;
			}

			/* Set timer idle */
			priv->idle |= TIMER_OFFSET((offset + j));
			priv->timer[offset + j].irq = irq;
			priv->timer[offset + j].num = offset + j;
			irq_index++;
		}
	}

	return 0;
}

static void timer_group_init(struct device_node *np)
{
	struct timer_group_priv *priv;
	unsigned int i = 0;
	int ret;

	priv = kzalloc(sizeof(struct timer_group_priv), GFP_KERNEL);
	if (!priv) {
		pr_err("%pOF: cannot allocate memory for group.\n", np);
		return;
	}

	if (of_device_is_compatible(np, "fsl,mpic-global-timer"))
		priv->flags |= FSL_GLOBAL_TIMER;

	priv->regs = of_iomap(np, i++);
	if (!priv->regs) {
		pr_err("%pOF: cannot ioremap timer register address.\n", np);
		goto out;
	}

	if (priv->flags & FSL_GLOBAL_TIMER) {
		priv->group_tcr = of_iomap(np, i++);
		if (!priv->group_tcr) {
			pr_err("%pOF: cannot ioremap tcr address.\n", np);
			goto out;
		}
	}

	ret = timer_group_get_freq(np, priv);
	if (ret < 0) {
		pr_err("%pOF: cannot get timer frequency.\n", np);
		goto out;
	}

	ret = timer_group_get_irq(np, priv);
	if (ret < 0) {
		pr_err("%pOF: cannot get timer irqs.\n", np);
		goto out;
	}

	spin_lock_init(&priv->lock);

	/* Init FSL timer hardware */
	if (priv->flags & FSL_GLOBAL_TIMER)
		setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);

	list_add_tail(&priv->node, &timer_group_list);

	return;

out:
	if (priv->regs)
		iounmap(priv->regs);

	if (priv->group_tcr)
		iounmap(priv->group_tcr);

	kfree(priv);
}

static void mpic_timer_resume(void)
{
	struct timer_group_priv *priv;

	list_for_each_entry(priv, &timer_group_list, node) {
		/* Init FSL timer hardware */
		if (priv->flags & FSL_GLOBAL_TIMER)
			setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
	}
}

static const struct of_device_id mpic_timer_ids[] = {
	{ .compatible = "fsl,mpic-global-timer", },
	{},
};

static struct syscore_ops mpic_timer_syscore_ops = {
	.resume = mpic_timer_resume,
};

static int __init mpic_timer_init(void)
{
	struct device_node *np = NULL;

	for_each_matching_node(np, mpic_timer_ids)
		timer_group_init(np);

	register_syscore_ops(&mpic_timer_syscore_ops);

	if (list_empty(&timer_group_list))
		return -ENODEV;

	return 0;
}
subsys_initcall(mpic_timer_init);
Commit	Line	Data
36ca09be D	1	/*
	2	* MPIC timer driver
	3	*
	4	* Copyright 2013 Freescale Semiconductor, Inc.
	5	* Author: Dongsheng Wang <Dongsheng.Wang@freescale.com>
	6	* Li Yang <leoli@freescale.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/module.h>
	17	#include <linux/errno.h>
	18	#include <linux/mm.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/slab.h>
	21	#include <linux/of.h>
26a2056e	22	#include <linux/of_address.h>
36ca09be	23	#include <linux/of_device.h>
26a2056e	24	#include <linux/of_irq.h>
36ca09be D	25	#include <linux/syscore_ops.h>
	26	#include <sysdev/fsl_soc.h>
	27	#include <asm/io.h>
	28
	29	#include <asm/mpic_timer.h>
	30
	31	#define FSL_GLOBAL_TIMER 0x1
	32
	33	/* Clock Ratio
	34	* Divide by 64 0x00000300
	35	* Divide by 32 0x00000200
	36	* Divide by 16 0x00000100
	37	* Divide by 8 0x00000000 (Hardware default div)
	38	*/
	39	#define MPIC_TIMER_TCR_CLKDIV 0x00000300
	40
	41	#define MPIC_TIMER_TCR_ROVR_OFFSET 24
	42
	43	#define TIMER_STOP 0x80000000
0fd79588	44	#define GTCCR_TOG 0x80000000
36ca09be D	45	#define TIMERS_PER_GROUP 4
	46	#define MAX_TICKS (~0U >> 1)
	47	#define MAX_TICKS_CASCADE (~0U)
	48	#define TIMER_OFFSET(num) (1 << (TIMERS_PER_GROUP - 1 - num))
	49
36ca09be D	50	struct timer_regs {
	51	u32 gtccr;
	52	u32 res0[3];
	53	u32 gtbcr;
	54	u32 res1[3];
	55	u32 gtvpr;
	56	u32 res2[3];
	57	u32 gtdr;
	58	u32 res3[3];
	59	};
	60
	61	struct cascade_priv {
	62	u32 tcr_value; /* TCR register: CASC & ROVR value */
	63	unsigned int cascade_map; /* cascade map */
	64	unsigned int timer_num; /* cascade control timer */
	65	};
	66
	67	struct timer_group_priv {
	68	struct timer_regs __iomem *regs;
	69	struct mpic_timer timer[TIMERS_PER_GROUP];
	70	struct list_head node;
	71	unsigned int timerfreq;
	72	unsigned int idle;
	73	unsigned int flags;
	74	spinlock_t lock;
	75	void __iomem *group_tcr;
	76	};
	77
	78	static struct cascade_priv cascade_timer[] = {
	79	/* cascade timer 0 and 1 */
	80	{0x1, 0xc, 0x1},
	81	/* cascade timer 1 and 2 */
	82	{0x2, 0x6, 0x2},
	83	/* cascade timer 2 and 3 */
	84	{0x4, 0x3, 0x3}
	85	};
	86
	87	static LIST_HEAD(timer_group_list);
	88
	89	static void convert_ticks_to_time(struct timer_group_priv *priv,
11ed8c55	90	const u64 ticks, time64_t *time)
36ca09be	91	{
11ed8c55	92	*time = (u64)div_u64(ticks, priv->timerfreq);
36ca09be D	93	}
	94
	95	/* the time set by the user is converted to "ticks" */
	96	static int convert_time_to_ticks(struct timer_group_priv *priv,
11ed8c55	97	time64_t time, u64 *ticks)
36ca09be D	98	{
36ca09be D	99	u64 max_value; /* prevent u64 overflow */
36ca09be D	100
	101	max_value = div_u64(ULLONG_MAX, priv->timerfreq);
	102
11ed8c55	103	if (time > max_value)
36ca09be D	104	return -EINVAL;
36ca09be D	105
11ed8c55	106	ticks = (u64)time (u64)priv->timerfreq;
36ca09be D	107
	108	return 0;
	109	}
	110
	111	/* detect whether there is a cascade timer available */
	112	static struct mpic_timer *detect_idle_cascade_timer(
	113	struct timer_group_priv *priv)
	114	{
	115	struct cascade_priv *casc_priv;
	116	unsigned int map;
	117	unsigned int array_size = ARRAY_SIZE(cascade_timer);
	118	unsigned int num;
	119	unsigned int i;
	120	unsigned long flags;
	121
	122	casc_priv = cascade_timer;
	123	for (i = 0; i < array_size; i++) {
	124	spin_lock_irqsave(&priv->lock, flags);
	125	map = casc_priv->cascade_map & priv->idle;
	126	if (map == casc_priv->cascade_map) {
	127	num = casc_priv->timer_num;
	128	priv->timer[num].cascade_handle = casc_priv;
	129
	130	/* set timer busy */
	131	priv->idle &= ~casc_priv->cascade_map;
	132	spin_unlock_irqrestore(&priv->lock, flags);
	133	return &priv->timer[num];
	134	}
	135	spin_unlock_irqrestore(&priv->lock, flags);
	136	casc_priv++;
	137	}
	138
	139	return NULL;
	140	}
	141
	142	static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks,
	143	unsigned int num)
	144	{
	145	struct cascade_priv *casc_priv;
	146	u32 tcr;
	147	u32 tmp_ticks;
	148	u32 rem_ticks;
	149
	150	/* set group tcr reg for cascade */
	151	casc_priv = priv->timer[num].cascade_handle;
	152	if (!casc_priv)
	153	return -EINVAL;
	154
	155	tcr = casc_priv->tcr_value \|
	156	(casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
	157	setbits32(priv->group_tcr, tcr);
	158
	159	tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);
	160
	161	out_be32(&priv->regs[num].gtccr, 0);
	162	out_be32(&priv->regs[num].gtbcr, tmp_ticks \| TIMER_STOP);
	163
	164	out_be32(&priv->regs[num - 1].gtccr, 0);
	165	out_be32(&priv->regs[num - 1].gtbcr, rem_ticks);
	166
	167	return 0;
	168	}
	169
	170	static struct mpic_timer get_cascade_timer(struct timer_group_priv priv,
171	u64 ticks)
172	{
173	struct mpic_timer *allocated_timer;
174
175	/* Two cascade timers: Support the maximum time */
176	const u64 max_ticks = (u64)MAX_TICKS * (u64)MAX_TICKS_CASCADE;
177	int ret;
178
179	if (ticks > max_ticks)
180	return NULL;
181
182	/* detect idle timer */
183	allocated_timer = detect_idle_cascade_timer(priv);
184	if (!allocated_timer)
185	return NULL;
186
187	/* set ticks to timer */
188	ret = set_cascade_timer(priv, ticks, allocated_timer->num);
189	if (ret < 0)
190	return NULL;
191
192	return allocated_timer;
193	}
194
11ed8c55	195	static struct mpic_timer *get_timer(time64_t time)
36ca09be D	196	{
	197	struct timer_group_priv *priv;
	198	struct mpic_timer *timer;
	199
	200	u64 ticks;
	201	unsigned int num;
	202	unsigned int i;
	203	unsigned long flags;
	204	int ret;
	205
	206	list_for_each_entry(priv, &timer_group_list, node) {
	207	ret = convert_time_to_ticks(priv, time, &ticks);
	208	if (ret < 0)
	209	return NULL;
	210
	211	if (ticks > MAX_TICKS) {
	212	if (!(priv->flags & FSL_GLOBAL_TIMER))
	213	return NULL;
	214
	215	timer = get_cascade_timer(priv, ticks);
	216	if (!timer)
	217	continue;
	218
	219	return timer;
	220	}
	221
	222	for (i = 0; i < TIMERS_PER_GROUP; i++) {
	223	/* one timer: Reverse allocation */
	224	num = TIMERS_PER_GROUP - 1 - i;
	225	spin_lock_irqsave(&priv->lock, flags);
	226	if (priv->idle & (1 << i)) {
	227	/* set timer busy */
	228	priv->idle &= ~(1 << i);
	229	/* set ticks & stop timer */
	230	out_be32(&priv->regs[num].gtbcr,
	231	ticks \| TIMER_STOP);
	232	out_be32(&priv->regs[num].gtccr, 0);
	233	priv->timer[num].cascade_handle = NULL;
	234	spin_unlock_irqrestore(&priv->lock, flags);
	235	return &priv->timer[num];
	236	}
	237	spin_unlock_irqrestore(&priv->lock, flags);
	238	}
	239	}
	240
	241	return NULL;
	242	}
	243
	244	/**
	245	* mpic_start_timer - start hardware timer
	246	* @handle: the timer to be started.
	247	*
	248	* It will do ->fn(->dev) callback from the hardware interrupt at
11ed8c55	249	* the 'time64_t' point in the future.
36ca09be D	250	*/
	251	void mpic_start_timer(struct mpic_timer *handle)
	252	{
	253	struct timer_group_priv *priv = container_of(handle,
	254	struct timer_group_priv, timer[handle->num]);
	255
	256	clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
	257	}
	258	EXPORT_SYMBOL(mpic_start_timer);
	259
	260	/**
	261	* mpic_stop_timer - stop hardware timer
	262	* @handle: the timer to be stoped
	263	*
	264	* The timer periodically generates an interrupt. Unless user stops the timer.
	265	*/
	266	void mpic_stop_timer(struct mpic_timer *handle)
	267	{
	268	struct timer_group_priv *priv = container_of(handle,
	269	struct timer_group_priv, timer[handle->num]);
	270	struct cascade_priv *casc_priv;
	271
	272	setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
	273
	274	casc_priv = priv->timer[handle->num].cascade_handle;
	275	if (casc_priv) {
	276	out_be32(&priv->regs[handle->num].gtccr, 0);
	277	out_be32(&priv->regs[handle->num - 1].gtccr, 0);
	278	} else {
	279	out_be32(&priv->regs[handle->num].gtccr, 0);
	280	}
	281	}
	282	EXPORT_SYMBOL(mpic_stop_timer);
	283
	284	/**
	285	* mpic_get_remain_time - get timer time
	286	* @handle: the timer to be selected.
	287	* @time: time for timer
	288	*
	289	* Query timer remaining time.
	290	*/
11ed8c55	291	void mpic_get_remain_time(struct mpic_timer handle, time64_t time)
36ca09be D	292	{
	293	struct timer_group_priv *priv = container_of(handle,
	294	struct timer_group_priv, timer[handle->num]);
	295	struct cascade_priv *casc_priv;
	296
	297	u64 ticks;
	298	u32 tmp_ticks;
	299
	300	casc_priv = priv->timer[handle->num].cascade_handle;
	301	if (casc_priv) {
	302	tmp_ticks = in_be32(&priv->regs[handle->num].gtccr);
0fd79588	303	tmp_ticks &= ~GTCCR_TOG;
36ca09be D	304	ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE;
	305	tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr);
	306	ticks += tmp_ticks;
	307	} else {
	308	ticks = in_be32(&priv->regs[handle->num].gtccr);
0fd79588	309	ticks &= ~GTCCR_TOG;
36ca09be D	310	}
	311
	312	convert_ticks_to_time(priv, ticks, time);
	313	}
	314	EXPORT_SYMBOL(mpic_get_remain_time);
	315
	316	/**
	317	* mpic_free_timer - free hardware timer
	318	* @handle: the timer to be removed.
	319	*
	320	* Free the timer.
	321	*
	322	* Note: can not be used in interrupt context.
	323	*/
	324	void mpic_free_timer(struct mpic_timer *handle)
	325	{
	326	struct timer_group_priv *priv = container_of(handle,
	327	struct timer_group_priv, timer[handle->num]);
	328
	329	struct cascade_priv *casc_priv;
	330	unsigned long flags;
	331
	332	mpic_stop_timer(handle);
	333
	334	casc_priv = priv->timer[handle->num].cascade_handle;
	335
	336	free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev);
	337
	338	spin_lock_irqsave(&priv->lock, flags);
	339	if (casc_priv) {
	340	u32 tcr;
	341	tcr = casc_priv->tcr_value \| (casc_priv->tcr_value <<
	342	MPIC_TIMER_TCR_ROVR_OFFSET);
	343	clrbits32(priv->group_tcr, tcr);
	344	priv->idle \|= casc_priv->cascade_map;
	345	priv->timer[handle->num].cascade_handle = NULL;
	346	} else {
	347	priv->idle \|= TIMER_OFFSET(handle->num);
	348	}
	349	spin_unlock_irqrestore(&priv->lock, flags);
	350	}
	351	EXPORT_SYMBOL(mpic_free_timer);
	352
	353	/**
	354	* mpic_request_timer - get a hardware timer
	355	* @fn: interrupt handler function
	356	* @dev: callback function of the data
	357	* @time: time for timer
	358	*
	359	* This executes the "request_irq", returning NULL
	360	* else "handle" on success.
	361	*/
	362	struct mpic_timer mpic_request_timer(irq_handler_t fn, void dev,
11ed8c55	363	time64_t time)
36ca09be D	364	{
	365	struct mpic_timer *allocated_timer;
	366	int ret;
	367
	368	if (list_empty(&timer_group_list))
	369	return NULL;
	370
11ed8c55	371	if (time < 0)
36ca09be D	372	return NULL;
	373
	374	allocated_timer = get_timer(time);
	375	if (!allocated_timer)
	376	return NULL;
	377
	378	ret = request_irq(allocated_timer->irq, fn,
	379	IRQF_TRIGGER_LOW, "global-timer", dev);
	380	if (ret) {
	381	mpic_free_timer(allocated_timer);
	382	return NULL;
	383	}
	384
	385	allocated_timer->dev = dev;
	386
	387	return allocated_timer;
	388	}
	389	EXPORT_SYMBOL(mpic_request_timer);
	390
	391	static int timer_group_get_freq(struct device_node *np,
	392	struct timer_group_priv *priv)
	393	{
	394	u32 div;
	395
	396	if (priv->flags & FSL_GLOBAL_TIMER) {
	397	struct device_node *dn;
	398
	399	dn = of_find_compatible_node(NULL, NULL, "fsl,mpic");
	400	if (dn) {
	401	of_property_read_u32(dn, "clock-frequency",
	402	&priv->timerfreq);
	403	of_node_put(dn);
	404	}
	405	}
	406
	407	if (priv->timerfreq <= 0)
	408	return -EINVAL;
	409
	410	if (priv->flags & FSL_GLOBAL_TIMER) {
	411	div = (1 << (MPIC_TIMER_TCR_CLKDIV >> 8)) * 8;
	412	priv->timerfreq /= div;
	413	}
	414
	415	return 0;
	416	}
	417
	418	static int timer_group_get_irq(struct device_node *np,
	419	struct timer_group_priv *priv)
	420	{
	421	const u32 all_timer[] = { 0, TIMERS_PER_GROUP };
	422	const u32 *p;
	423	u32 offset;
	424	u32 count;
	425
	426	unsigned int i;
	427	unsigned int j;
	428	unsigned int irq_index = 0;
	429	unsigned int irq;
	430	int len;
	431
	432	p = of_get_property(np, "fsl,available-ranges", &len);
	433	if (p && len % (2 * sizeof(u32)) != 0) {
b7c670d6	434	pr_err("%pOF: malformed available-ranges property.\n", np);
36ca09be D	435	return -EINVAL;
	436	}
	437
	438	if (!p) {
	439	p = all_timer;
	440	len = sizeof(all_timer);
	441	}
	442
	443	len /= 2 * sizeof(u32);
	444
	445	for (i = 0; i < len; i++) {
	446	offset = p[i * 2];
	447	count = p[i * 2 + 1];
	448	for (j = 0; j < count; j++) {
	449	irq = irq_of_parse_and_map(np, irq_index);
	450	if (!irq) {
b7c670d6	451	pr_err("%pOF: irq parse and map failed.\n", np);
36ca09be D	452	return -EINVAL;
	453	}
	454
	455	/* Set timer idle */
	456	priv->idle \|= TIMER_OFFSET((offset + j));
	457	priv->timer[offset + j].irq = irq;
	458	priv->timer[offset + j].num = offset + j;
	459	irq_index++;
	460	}
	461	}
	462
	463	return 0;
	464	}
	465
	466	static void timer_group_init(struct device_node *np)
	467	{
	468	struct timer_group_priv *priv;
	469	unsigned int i = 0;
	470	int ret;
	471
	472	priv = kzalloc(sizeof(struct timer_group_priv), GFP_KERNEL);
	473	if (!priv) {
b7c670d6	474	pr_err("%pOF: cannot allocate memory for group.\n", np);
36ca09be D	475	return;
	476	}
	477
	478	if (of_device_is_compatible(np, "fsl,mpic-global-timer"))
	479	priv->flags \|= FSL_GLOBAL_TIMER;
	480
	481	priv->regs = of_iomap(np, i++);
	482	if (!priv->regs) {
b7c670d6	483	pr_err("%pOF: cannot ioremap timer register address.\n", np);
36ca09be D	484	goto out;
	485	}
	486
	487	if (priv->flags & FSL_GLOBAL_TIMER) {
	488	priv->group_tcr = of_iomap(np, i++);
	489	if (!priv->group_tcr) {
b7c670d6	490	pr_err("%pOF: cannot ioremap tcr address.\n", np);
36ca09be D	491	goto out;
	492	}
	493	}
	494
	495	ret = timer_group_get_freq(np, priv);
	496	if (ret < 0) {
b7c670d6	497	pr_err("%pOF: cannot get timer frequency.\n", np);
36ca09be D	498	goto out;
	499	}
	500
	501	ret = timer_group_get_irq(np, priv);
	502	if (ret < 0) {
b7c670d6	503	pr_err("%pOF: cannot get timer irqs.\n", np);
36ca09be D	504	goto out;
	505	}
	506
	507	spin_lock_init(&priv->lock);
	508
	509	/* Init FSL timer hardware */
	510	if (priv->flags & FSL_GLOBAL_TIMER)
	511	setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
	512
	513	list_add_tail(&priv->node, &timer_group_list);
	514
	515	return;
	516
	517	out:
	518	if (priv->regs)
	519	iounmap(priv->regs);
	520
	521	if (priv->group_tcr)
	522	iounmap(priv->group_tcr);
	523
	524	kfree(priv);
	525	}
	526
	527	static void mpic_timer_resume(void)
	528	{
	529	struct timer_group_priv *priv;
	530
	531	list_for_each_entry(priv, &timer_group_list, node) {
	532	/* Init FSL timer hardware */
	533	if (priv->flags & FSL_GLOBAL_TIMER)
	534	setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
	535	}
	536	}
	537
	538	static const struct of_device_id mpic_timer_ids[] = {
	539	{ .compatible = "fsl,mpic-global-timer", },
	540	{},
	541	};
	542
	543	static struct syscore_ops mpic_timer_syscore_ops = {
	544	.resume = mpic_timer_resume,
	545	};
	546
	547	static int __init mpic_timer_init(void)
	548	{
	549	struct device_node *np = NULL;
	550
	551	for_each_matching_node(np, mpic_timer_ids)
	552	timer_group_init(np);
	553
	554	register_syscore_ops(&mpic_timer_syscore_ops);
	555
	556	if (list_empty(&timer_group_list))
	557	return -ENODEV;
	558
	559	return 0;
	560	}
	561	subsys_initcall(mpic_timer_init);