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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
[linux-2.6-block.git] / arch / powerpc / sysdev / mpic.c
CommitLineData
14cf11af
PM		 1/*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15#undef DEBUG
1beb6a7d
BH		 16#undef DEBUG_IPI
17#undef DEBUG_IRQ
18#undef DEBUG_LOW
14cf11af 19
14cf11af
PM		 20#include <linux/types.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/irq.h>
24#include <linux/smp.h>
25#include <linux/interrupt.h>
26#include <linux/bootmem.h>
27#include <linux/spinlock.h>
28#include <linux/pci.h>
29
30#include <asm/ptrace.h>
31#include <asm/signal.h>
32#include <asm/io.h>
33#include <asm/pgtable.h>
34#include <asm/irq.h>
35#include <asm/machdep.h>
36#include <asm/mpic.h>
37#include <asm/smp.h>
38
39#ifdef DEBUG
40#define DBG(fmt...) printk(fmt)
41#else
42#define DBG(fmt...)
43#endif
44
45static struct mpic *mpics;
46static struct mpic *mpic_primary;
47static DEFINE_SPINLOCK(mpic_lock);
48
c0c0d996 49#ifdef CONFIG_PPC32 /* XXX for now */
e40c7f02
AW		 50#ifdef CONFIG_IRQ_ALL_CPUS
51#define distribute_irqs (1)
52#else
53#define distribute_irqs (0)
54#endif
c0c0d996 55#endif
14cf11af 56
7233593b
ZR		 57#ifdef CONFIG_MPIC_WEIRD
58static u32 mpic_infos[][MPIC_IDX_END] = {
59 [0] = { /* Original OpenPIC compatible MPIC */
60 MPIC_GREG_BASE,
61 MPIC_GREG_FEATURE_0,
62 MPIC_GREG_GLOBAL_CONF_0,
63 MPIC_GREG_VENDOR_ID,
64 MPIC_GREG_IPI_VECTOR_PRI_0,
65 MPIC_GREG_IPI_STRIDE,
66 MPIC_GREG_SPURIOUS,
67 MPIC_GREG_TIMER_FREQ,
68
69 MPIC_TIMER_BASE,
70 MPIC_TIMER_STRIDE,
71 MPIC_TIMER_CURRENT_CNT,
72 MPIC_TIMER_BASE_CNT,
73 MPIC_TIMER_VECTOR_PRI,
74 MPIC_TIMER_DESTINATION,
75
76 MPIC_CPU_BASE,
77 MPIC_CPU_STRIDE,
78 MPIC_CPU_IPI_DISPATCH_0,
79 MPIC_CPU_IPI_DISPATCH_STRIDE,
80 MPIC_CPU_CURRENT_TASK_PRI,
81 MPIC_CPU_WHOAMI,
82 MPIC_CPU_INTACK,
83 MPIC_CPU_EOI,
84
85 MPIC_IRQ_BASE,
86 MPIC_IRQ_STRIDE,
87 MPIC_IRQ_VECTOR_PRI,
88 MPIC_VECPRI_VECTOR_MASK,
89 MPIC_VECPRI_POLARITY_POSITIVE,
90 MPIC_VECPRI_POLARITY_NEGATIVE,
91 MPIC_VECPRI_SENSE_LEVEL,
92 MPIC_VECPRI_SENSE_EDGE,
93 MPIC_VECPRI_POLARITY_MASK,
94 MPIC_VECPRI_SENSE_MASK,
95 MPIC_IRQ_DESTINATION
96 },
97 [1] = { /* Tsi108/109 PIC */
98 TSI108_GREG_BASE,
99 TSI108_GREG_FEATURE_0,
100 TSI108_GREG_GLOBAL_CONF_0,
101 TSI108_GREG_VENDOR_ID,
102 TSI108_GREG_IPI_VECTOR_PRI_0,
103 TSI108_GREG_IPI_STRIDE,
104 TSI108_GREG_SPURIOUS,
105 TSI108_GREG_TIMER_FREQ,
106
107 TSI108_TIMER_BASE,
108 TSI108_TIMER_STRIDE,
109 TSI108_TIMER_CURRENT_CNT,
110 TSI108_TIMER_BASE_CNT,
111 TSI108_TIMER_VECTOR_PRI,
112 TSI108_TIMER_DESTINATION,
113
114 TSI108_CPU_BASE,
115 TSI108_CPU_STRIDE,
116 TSI108_CPU_IPI_DISPATCH_0,
117 TSI108_CPU_IPI_DISPATCH_STRIDE,
118 TSI108_CPU_CURRENT_TASK_PRI,
119 TSI108_CPU_WHOAMI,
120 TSI108_CPU_INTACK,
121 TSI108_CPU_EOI,
122
123 TSI108_IRQ_BASE,
124 TSI108_IRQ_STRIDE,
125 TSI108_IRQ_VECTOR_PRI,
126 TSI108_VECPRI_VECTOR_MASK,
127 TSI108_VECPRI_POLARITY_POSITIVE,
128 TSI108_VECPRI_POLARITY_NEGATIVE,
129 TSI108_VECPRI_SENSE_LEVEL,
130 TSI108_VECPRI_SENSE_EDGE,
131 TSI108_VECPRI_POLARITY_MASK,
132 TSI108_VECPRI_SENSE_MASK,
133 TSI108_IRQ_DESTINATION
134 },
135};
136
137#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
138
139#else /* CONFIG_MPIC_WEIRD */
140
141#define MPIC_INFO(name) MPIC_##name
142
143#endif /* CONFIG_MPIC_WEIRD */
144
14cf11af
PM		 145/*
146 * Register accessor functions
147 */
148
149
150static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base,
151 unsigned int reg)
152{
153 if (be)
154 return in_be32(base + (reg >> 2));
155 else
156 return in_le32(base + (reg >> 2));
157}
158
159static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
160 unsigned int reg, u32 value)
161{
162 if (be)
163 out_be32(base + (reg >> 2), value);
164 else
165 out_le32(base + (reg >> 2), value);
166}
167
168static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
169{
170 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
7233593b
ZR		 171 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
172 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
14cf11af
PM		 173
174 if (mpic->flags & MPIC_BROKEN_IPI)
175 be = !be;
176 return _mpic_read(be, mpic->gregs, offset);
177}
178
179static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
180{
7233593b
ZR		 181 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
182 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
14cf11af
PM		 183
184 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
185}
186
187static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
188{
189 unsigned int cpu = 0;
190
191 if (mpic->flags & MPIC_PRIMARY)
192 cpu = hard_smp_processor_id();
b9e5b4e6
BH		 193 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,
194 mpic->cpuregs[cpu], reg);
14cf11af
PM		 195}
196
197static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
198{
199 unsigned int cpu = 0;
200
201 if (mpic->flags & MPIC_PRIMARY)
202 cpu = hard_smp_processor_id();
203
204 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value);
205}
206
207static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
208{
209 unsigned int isu = src_no >> mpic->isu_shift;
210 unsigned int idx = src_no & mpic->isu_mask;
211
212 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
7233593b 213 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
14cf11af
PM		 214}
215
216static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
217 unsigned int reg, u32 value)
218{
219 unsigned int isu = src_no >> mpic->isu_shift;
220 unsigned int idx = src_no & mpic->isu_mask;
221
222 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
7233593b 223 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
14cf11af
PM		 224}
225
226#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
227#define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v))
228#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
229#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
230#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
231#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
232#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
233#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
234
235
236/*
237 * Low level utility functions
238 */
239
240
241
242/* Check if we have one of those nice broken MPICs with a flipped endian on
243 * reads from IPI registers
244 */
245static void __init mpic_test_broken_ipi(struct mpic *mpic)
246{
247 u32 r;
248
7233593b
ZR		 249 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
250 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
14cf11af
PM		 251
252 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
253 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
254 mpic->flags |= MPIC_BROKEN_IPI;
255 }
256}
257
258#ifdef CONFIG_MPIC_BROKEN_U3
259
260/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
261 * to force the edge setting on the MPIC and do the ack workaround.
262 */
1beb6a7d 263static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
14cf11af 264{
1beb6a7d 265 if (source >= 128 || !mpic->fixups)
14cf11af 266 return 0;
1beb6a7d 267 return mpic->fixups[source].base != NULL;
14cf11af
PM		 268}
269
c4b22f26 270
1beb6a7d 271static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
14cf11af 272{
1beb6a7d 273 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
14cf11af 274
1beb6a7d
BH		 275 if (fixup->applebase) {
276 unsigned int soff = (fixup->index >> 3) & ~3;
277 unsigned int mask = 1U << (fixup->index & 0x1f);
278 writel(mask, fixup->applebase + soff);
279 } else {
280 spin_lock(&mpic->fixup_lock);
281 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
282 writel(fixup->data, fixup->base + 4);
283 spin_unlock(&mpic->fixup_lock);
284 }
14cf11af
PM		 285}
286
1beb6a7d
BH		 287static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
288 unsigned int irqflags)
289{
290 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
291 unsigned long flags;
292 u32 tmp;
293
294 if (fixup->base == NULL)
295 return;
296
06fe98e6 297 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
1beb6a7d
BH		 298 source, irqflags, fixup->index);
299 spin_lock_irqsave(&mpic->fixup_lock, flags);
300 /* Enable and configure */
301 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
302 tmp = readl(fixup->base + 4);
303 tmp &= ~(0x23U);
304 if (irqflags & IRQ_LEVEL)
305 tmp |= 0x22;
306 writel(tmp, fixup->base + 4);
307 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
308}
309
310static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
311 unsigned int irqflags)
312{
313 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
314 unsigned long flags;
315 u32 tmp;
316
317 if (fixup->base == NULL)
318 return;
319
06fe98e6 320 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
1beb6a7d
BH		 321
322 /* Disable */
323 spin_lock_irqsave(&mpic->fixup_lock, flags);
324 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
325 tmp = readl(fixup->base + 4);
72b13819 326 tmp |= 1;
1beb6a7d
BH		 327 writel(tmp, fixup->base + 4);
328 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
329}
14cf11af 330
1beb6a7d
BH		 331static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
332 unsigned int devfn, u32 vdid)
14cf11af 333{
c4b22f26 334 int i, irq, n;
1beb6a7d 335 u8 __iomem *base;
14cf11af 336 u32 tmp;
c4b22f26 337 u8 pos;
14cf11af 338
1beb6a7d
BH		 339 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
340 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
341 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
46ff3463 342 if (id == PCI_CAP_ID_HT) {
c4b22f26 343 id = readb(devbase + pos + 3);
e78d0169 344 if (id == HT_CAPTYPE_IRQ)
c4b22f26
SB		 345 break;
346 }
14cf11af 347 }
c4b22f26
SB		 348 if (pos == 0)
349 return;
350
1beb6a7d
BH		 351 base = devbase + pos;
352 writeb(0x01, base + 2);
353 n = (readl(base + 4) >> 16) & 0xff;
14cf11af 354
1beb6a7d
BH		 355 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
356 " has %d irqs\n",
357 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
c4b22f26
SB		 358
359 for (i = 0; i <= n; i++) {
1beb6a7d
BH		 360 writeb(0x10 + 2 * i, base + 2);
361 tmp = readl(base + 4);
14cf11af 362 irq = (tmp >> 16) & 0xff;
1beb6a7d
BH		 363 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
364 /* mask it , will be unmasked later */
365 tmp |= 0x1;
366 writel(tmp, base + 4);
367 mpic->fixups[irq].index = i;
368 mpic->fixups[irq].base = base;
369 /* Apple HT PIC has a non-standard way of doing EOIs */
370 if ((vdid & 0xffff) == 0x106b)
371 mpic->fixups[irq].applebase = devbase + 0x60;
372 else
373 mpic->fixups[irq].applebase = NULL;
374 writeb(0x11 + 2 * i, base + 2);
375 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
14cf11af
PM		 376 }
377}
378
c4b22f26 379
1beb6a7d 380static void __init mpic_scan_ht_pics(struct mpic *mpic)
14cf11af
PM		 381{
382 unsigned int devfn;
383 u8 __iomem *cfgspace;
384
1beb6a7d 385 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
14cf11af
PM		 386
387 /* Allocate fixups array */
388 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
389 BUG_ON(mpic->fixups == NULL);
390 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
391
392 /* Init spinlock */
393 spin_lock_init(&mpic->fixup_lock);
394
c4b22f26
SB		 395 /* Map U3 config space. We assume all IO-APICs are on the primary bus
396 * so we only need to map 64kB.
14cf11af 397 */
c4b22f26 398 cfgspace = ioremap(0xf2000000, 0x10000);
14cf11af
PM		 399 BUG_ON(cfgspace == NULL);
400
1beb6a7d
BH		 401 /* Now we scan all slots. We do a very quick scan, we read the header
402 * type, vendor ID and device ID only, that's plenty enough
14cf11af 403 */
c4b22f26 404 for (devfn = 0; devfn < 0x100; devfn++) {
14cf11af
PM		 405 u8 __iomem *devbase = cfgspace + (devfn << 8);
406 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
407 u32 l = readl(devbase + PCI_VENDOR_ID);
1beb6a7d 408 u16 s;
14cf11af
PM		 409
410 DBG("devfn %x, l: %x\n", devfn, l);
411
412 /* If no device, skip */
413 if (l == 0xffffffff || l == 0x00000000 ||
414 l == 0x0000ffff || l == 0xffff0000)
415 goto next;
1beb6a7d
BH		 416 /* Check if is supports capability lists */
417 s = readw(devbase + PCI_STATUS);
418 if (!(s & PCI_STATUS_CAP_LIST))
419 goto next;
14cf11af 420
1beb6a7d 421 mpic_scan_ht_pic(mpic, devbase, devfn, l);
c4b22f26 422
14cf11af
PM		 423 next:
424 /* next device, if function 0 */
c4b22f26 425 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
14cf11af
PM		 426 devfn += 7;
427 }
428}
429
6e99e458
BH		 430#else /* CONFIG_MPIC_BROKEN_U3 */
431
432static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
433{
434 return 0;
435}
436
437static void __init mpic_scan_ht_pics(struct mpic *mpic)
438{
439}
440
14cf11af
PM		 441#endif /* CONFIG_MPIC_BROKEN_U3 */
442
443
0ebfff14
BH		 444#define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
445
14cf11af
PM		 446/* Find an mpic associated with a given linux interrupt */
447static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
448{
0ebfff14
BH		 449 unsigned int src = mpic_irq_to_hw(irq);
450
451 if (irq < NUM_ISA_INTERRUPTS)
452 return NULL;
453 if (is_ipi)
454 *is_ipi = (src >= MPIC_VEC_IPI_0 && src <= MPIC_VEC_IPI_3);
455
456 return irq_desc[irq].chip_data;
14cf11af
PM		 457}
458
459/* Convert a cpu mask from logical to physical cpu numbers. */
460static inline u32 mpic_physmask(u32 cpumask)
461{
462 int i;
463 u32 mask = 0;
464
465 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
466 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
467 return mask;
468}
469
470#ifdef CONFIG_SMP
471/* Get the mpic structure from the IPI number */
472static inline struct mpic * mpic_from_ipi(unsigned int ipi)
473{
b9e5b4e6 474 return irq_desc[ipi].chip_data;
14cf11af
PM		 475}
476#endif
477
478/* Get the mpic structure from the irq number */
479static inline struct mpic * mpic_from_irq(unsigned int irq)
480{
b9e5b4e6 481 return irq_desc[irq].chip_data;
14cf11af
PM		 482}
483
484/* Send an EOI */
485static inline void mpic_eoi(struct mpic *mpic)
486{
7233593b
ZR		 487 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
488 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
14cf11af
PM		 489}
490
491#ifdef CONFIG_SMP
7d12e780 492static irqreturn_t mpic_ipi_action(int irq, void *dev_id)
14cf11af 493{
7d12e780 494 smp_message_recv(mpic_irq_to_hw(irq) - MPIC_VEC_IPI_0);
14cf11af
PM		 495 return IRQ_HANDLED;
496}
497#endif /* CONFIG_SMP */
498
499/*
500 * Linux descriptor level callbacks
501 */
502
503
b9e5b4e6 504static void mpic_unmask_irq(unsigned int irq)
14cf11af
PM		 505{
506 unsigned int loops = 100000;
507 struct mpic *mpic = mpic_from_irq(irq);
0ebfff14 508 unsigned int src = mpic_irq_to_hw(irq);
14cf11af 509
bd561c79 510 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
14cf11af 511
7233593b
ZR		 512 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
513 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
e5356640 514 ~MPIC_VECPRI_MASK);
14cf11af
PM		 515 /* make sure mask gets to controller before we return to user */
516 do {
517 if (!loops--) {
518 printk(KERN_ERR "mpic_enable_irq timeout\n");
519 break;
520 }
7233593b 521 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
14cf11af
PM		 522}
523
b9e5b4e6 524static void mpic_mask_irq(unsigned int irq)
14cf11af
PM		 525{
526 unsigned int loops = 100000;
527 struct mpic *mpic = mpic_from_irq(irq);
0ebfff14 528 unsigned int src = mpic_irq_to_hw(irq);
14cf11af
PM		 529
530 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
531
7233593b
ZR		 532 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
533 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
e5356640 534 MPIC_VECPRI_MASK);
14cf11af
PM		 535
536 /* make sure mask gets to controller before we return to user */
537 do {
538 if (!loops--) {
539 printk(KERN_ERR "mpic_enable_irq timeout\n");
540 break;
541 }
7233593b 542 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
14cf11af
PM		 543}
544
b9e5b4e6 545static void mpic_end_irq(unsigned int irq)
1beb6a7d 546{
b9e5b4e6
BH		 547 struct mpic *mpic = mpic_from_irq(irq);
548
549#ifdef DEBUG_IRQ
550 DBG("%s: end_irq: %d\n", mpic->name, irq);
551#endif
552 /* We always EOI on end_irq() even for edge interrupts since that
553 * should only lower the priority, the MPIC should have properly
554 * latched another edge interrupt coming in anyway
555 */
556
557 mpic_eoi(mpic);
558}
559
1beb6a7d 560#ifdef CONFIG_MPIC_BROKEN_U3
b9e5b4e6
BH		 561
562static void mpic_unmask_ht_irq(unsigned int irq)
563{
1beb6a7d 564 struct mpic *mpic = mpic_from_irq(irq);
0ebfff14 565 unsigned int src = mpic_irq_to_hw(irq);
1beb6a7d 566
b9e5b4e6 567 mpic_unmask_irq(irq);
1beb6a7d 568
b9e5b4e6
BH		 569 if (irq_desc[irq].status & IRQ_LEVEL)
570 mpic_ht_end_irq(mpic, src);
571}
572
573static unsigned int mpic_startup_ht_irq(unsigned int irq)
574{
575 struct mpic *mpic = mpic_from_irq(irq);
0ebfff14 576 unsigned int src = mpic_irq_to_hw(irq);
1beb6a7d 577
b9e5b4e6
BH		 578 mpic_unmask_irq(irq);
579 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
580
581 return 0;
1beb6a7d
BH		 582}
583
b9e5b4e6
BH		 584static void mpic_shutdown_ht_irq(unsigned int irq)
585{
586 struct mpic *mpic = mpic_from_irq(irq);
0ebfff14 587 unsigned int src = mpic_irq_to_hw(irq);
b9e5b4e6
BH		 588
589 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
590 mpic_mask_irq(irq);
591}
592
593static void mpic_end_ht_irq(unsigned int irq)
14cf11af
PM		 594{
595 struct mpic *mpic = mpic_from_irq(irq);
0ebfff14 596 unsigned int src = mpic_irq_to_hw(irq);
14cf11af 597
1beb6a7d 598#ifdef DEBUG_IRQ
14cf11af 599 DBG("%s: end_irq: %d\n", mpic->name, irq);
1beb6a7d 600#endif
14cf11af
PM		 601 /* We always EOI on end_irq() even for edge interrupts since that
602 * should only lower the priority, the MPIC should have properly
603 * latched another edge interrupt coming in anyway
604 */
605
b9e5b4e6
BH		 606 if (irq_desc[irq].status & IRQ_LEVEL)
607 mpic_ht_end_irq(mpic, src);
14cf11af
PM		 608 mpic_eoi(mpic);
609}
6e99e458 610#endif /* !CONFIG_MPIC_BROKEN_U3 */
b9e5b4e6 611
14cf11af
PM		 612#ifdef CONFIG_SMP
613
b9e5b4e6 614static void mpic_unmask_ipi(unsigned int irq)
14cf11af
PM		 615{
616 struct mpic *mpic = mpic_from_ipi(irq);
0ebfff14 617 unsigned int src = mpic_irq_to_hw(irq) - MPIC_VEC_IPI_0;
14cf11af
PM		 618
619 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
620 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
621}
622
b9e5b4e6 623static void mpic_mask_ipi(unsigned int irq)
14cf11af
PM		 624{
625 /* NEVER disable an IPI... that's just plain wrong! */
626}
627
628static void mpic_end_ipi(unsigned int irq)
629{
630 struct mpic *mpic = mpic_from_ipi(irq);
631
632 /*
633 * IPIs are marked IRQ_PER_CPU. This has the side effect of
634 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
635 * applying to them. We EOI them late to avoid re-entering.
6714465e 636 * We mark IPI's with IRQF_DISABLED as they must run with
14cf11af
PM		 637 * irqs disabled.
638 */
639 mpic_eoi(mpic);
640}
641
642#endif /* CONFIG_SMP */
643
644static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
645{
646 struct mpic *mpic = mpic_from_irq(irq);
0ebfff14 647 unsigned int src = mpic_irq_to_hw(irq);
14cf11af
PM		 648
649 cpumask_t tmp;
650
651 cpus_and(tmp, cpumask, cpu_online_map);
652
7233593b 653 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
14cf11af
PM		 654 mpic_physmask(cpus_addr(tmp)[0]));
655}
656
7233593b 657static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
0ebfff14 658{
0ebfff14 659 /* Now convert sense value */
6e99e458 660 switch(type & IRQ_TYPE_SENSE_MASK) {
0ebfff14 661 case IRQ_TYPE_EDGE_RISING:
7233593b
ZR		 662 return MPIC_INFO(VECPRI_SENSE_EDGE) |
663 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
0ebfff14 664 case IRQ_TYPE_EDGE_FALLING:
6e99e458 665 case IRQ_TYPE_EDGE_BOTH:
7233593b
ZR		 666 return MPIC_INFO(VECPRI_SENSE_EDGE) |
667 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
0ebfff14 668 case IRQ_TYPE_LEVEL_HIGH:
7233593b
ZR		 669 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
670 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
0ebfff14
BH		 671 case IRQ_TYPE_LEVEL_LOW:
672 default:
7233593b
ZR		 673 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
674 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
0ebfff14 675 }
6e99e458
BH		 676}
677
678static int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
679{
680 struct mpic *mpic = mpic_from_irq(virq);
681 unsigned int src = mpic_irq_to_hw(virq);
682 struct irq_desc *desc = get_irq_desc(virq);
683 unsigned int vecpri, vold, vnew;
684
06fe98e6
BH		 685 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
686 mpic, virq, src, flow_type);
6e99e458
BH		 687
688 if (src >= mpic->irq_count)
689 return -EINVAL;
690
691 if (flow_type == IRQ_TYPE_NONE)
692 if (mpic->senses && src < mpic->senses_count)
693 flow_type = mpic->senses[src];
694 if (flow_type == IRQ_TYPE_NONE)
695 flow_type = IRQ_TYPE_LEVEL_LOW;
696
697 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
698 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
699 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
700 desc->status |= IRQ_LEVEL;
701
702 if (mpic_is_ht_interrupt(mpic, src))
703 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
704 MPIC_VECPRI_SENSE_EDGE;
705 else
7233593b 706 vecpri = mpic_type_to_vecpri(mpic, flow_type);
6e99e458 707
7233593b
ZR		 708 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
709 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
710 MPIC_INFO(VECPRI_SENSE_MASK));
6e99e458
BH		 711 vnew |= vecpri;
712 if (vold != vnew)
7233593b 713 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
6e99e458
BH		 714
715 return 0;
0ebfff14
BH		 716}
717
b9e5b4e6 718static struct irq_chip mpic_irq_chip = {
6e99e458
BH		 719 .mask = mpic_mask_irq,
720 .unmask = mpic_unmask_irq,
721 .eoi = mpic_end_irq,
722 .set_type = mpic_set_irq_type,
b9e5b4e6
BH		 723};
724
725#ifdef CONFIG_SMP
726static struct irq_chip mpic_ipi_chip = {
6e99e458
BH		 727 .mask = mpic_mask_ipi,
728 .unmask = mpic_unmask_ipi,
729 .eoi = mpic_end_ipi,
b9e5b4e6
BH		 730};
731#endif /* CONFIG_SMP */
732
733#ifdef CONFIG_MPIC_BROKEN_U3
734static struct irq_chip mpic_irq_ht_chip = {
735 .startup = mpic_startup_ht_irq,
736 .shutdown = mpic_shutdown_ht_irq,
737 .mask = mpic_mask_irq,
738 .unmask = mpic_unmask_ht_irq,
739 .eoi = mpic_end_ht_irq,
6e99e458 740 .set_type = mpic_set_irq_type,
b9e5b4e6
BH		 741};
742#endif /* CONFIG_MPIC_BROKEN_U3 */
743
14cf11af 744
0ebfff14
BH		 745static int mpic_host_match(struct irq_host *h, struct device_node *node)
746{
747 struct mpic *mpic = h->host_data;
748
749 /* Exact match, unless mpic node is NULL */
750 return mpic->of_node == NULL || mpic->of_node == node;
751}
752
753static int mpic_host_map(struct irq_host *h, unsigned int virq,
6e99e458 754 irq_hw_number_t hw)
0ebfff14 755{
0ebfff14 756 struct mpic *mpic = h->host_data;
6e99e458 757 struct irq_chip *chip;
0ebfff14 758
06fe98e6 759 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
0ebfff14
BH		 760
761 if (hw == MPIC_VEC_SPURRIOUS)
762 return -EINVAL;
06fe98e6 763
0ebfff14
BH		 764#ifdef CONFIG_SMP
765 else if (hw >= MPIC_VEC_IPI_0) {
766 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
767
06fe98e6 768 DBG("mpic: mapping as IPI\n");
0ebfff14
BH		 769 set_irq_chip_data(virq, mpic);
770 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
771 handle_percpu_irq);
772 return 0;
773 }
774#endif /* CONFIG_SMP */
775
776 if (hw >= mpic->irq_count)
777 return -EINVAL;
778
6e99e458 779 /* Default chip */
0ebfff14
BH		 780 chip = &mpic->hc_irq;
781
782#ifdef CONFIG_MPIC_BROKEN_U3
783 /* Check for HT interrupts, override vecpri */
6e99e458 784 if (mpic_is_ht_interrupt(mpic, hw))
0ebfff14 785 chip = &mpic->hc_ht_irq;
6e99e458 786#endif /* CONFIG_MPIC_BROKEN_U3 */
0ebfff14 787
06fe98e6 788 DBG("mpic: mapping to irq chip @%p\n", chip);
0ebfff14
BH		 789
790 set_irq_chip_data(virq, mpic);
791 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
6e99e458
BH		 792
793 /* Set default irq type */
794 set_irq_type(virq, IRQ_TYPE_NONE);
795
0ebfff14
BH		 796 return 0;
797}
798
799static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
800 u32 *intspec, unsigned int intsize,
801 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
802
803{
804 static unsigned char map_mpic_senses[4] = {
805 IRQ_TYPE_EDGE_RISING,
806 IRQ_TYPE_LEVEL_LOW,
807 IRQ_TYPE_LEVEL_HIGH,
808 IRQ_TYPE_EDGE_FALLING,
809 };
810
811 *out_hwirq = intspec[0];
06fe98e6
BH		 812 if (intsize > 1) {
813 u32 mask = 0x3;
814
815 /* Apple invented a new race of encoding on machines with
816 * an HT APIC. They encode, among others, the index within
817 * the HT APIC. We don't care about it here since thankfully,
818 * it appears that they have the APIC already properly
819 * configured, and thus our current fixup code that reads the
820 * APIC config works fine. However, we still need to mask out
821 * bits in the specifier to make sure we only get bit 0 which
822 * is the level/edge bit (the only sense bit exposed by Apple),
823 * as their bit 1 means something else.
824 */
825 if (machine_is(powermac))
826 mask = 0x1;
827 *out_flags = map_mpic_senses[intspec[1] & mask];
828 } else
0ebfff14
BH		 829 *out_flags = IRQ_TYPE_NONE;
830
06fe98e6
BH		 831 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
832 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
833
0ebfff14
BH		 834 return 0;
835}
836
837static struct irq_host_ops mpic_host_ops = {
838 .match = mpic_host_match,
839 .map = mpic_host_map,
840 .xlate = mpic_host_xlate,
841};
842
14cf11af
PM		 843/*
844 * Exported functions
845 */
846
0ebfff14
BH		 847struct mpic * __init mpic_alloc(struct device_node *node,
848 unsigned long phys_addr,
14cf11af
PM		 849 unsigned int flags,
850 unsigned int isu_size,
14cf11af 851 unsigned int irq_count,
14cf11af
PM		 852 const char *name)
853{
854 struct mpic *mpic;
855 u32 reg;
856 const char *vers;
857 int i;
858
859 mpic = alloc_bootmem(sizeof(struct mpic));
860 if (mpic == NULL)
861 return NULL;
862
14cf11af
PM		 863 memset(mpic, 0, sizeof(struct mpic));
864 mpic->name = name;
0ebfff14 865 mpic->of_node = node ? of_node_get(node) : NULL;
14cf11af 866
0ebfff14
BH		 867 mpic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 256,
868 &mpic_host_ops,
869 MPIC_VEC_SPURRIOUS);
870 if (mpic->irqhost == NULL) {
871 of_node_put(node);
872 return NULL;
873 }
874
875 mpic->irqhost->host_data = mpic;
b9e5b4e6 876 mpic->hc_irq = mpic_irq_chip;
14cf11af 877 mpic->hc_irq.typename = name;
14cf11af
PM		 878 if (flags & MPIC_PRIMARY)
879 mpic->hc_irq.set_affinity = mpic_set_affinity;
b9e5b4e6
BH		 880#ifdef CONFIG_MPIC_BROKEN_U3
881 mpic->hc_ht_irq = mpic_irq_ht_chip;
882 mpic->hc_ht_irq.typename = name;
883 if (flags & MPIC_PRIMARY)
884 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
885#endif /* CONFIG_MPIC_BROKEN_U3 */
14cf11af 886#ifdef CONFIG_SMP
b9e5b4e6 887 mpic->hc_ipi = mpic_ipi_chip;
0ebfff14 888 mpic->hc_ipi.typename = name;
14cf11af
PM		 889#endif /* CONFIG_SMP */
890
891 mpic->flags = flags;
892 mpic->isu_size = isu_size;
14cf11af 893 mpic->irq_count = irq_count;
14cf11af 894 mpic->num_sources = 0; /* so far */
14cf11af 895
7233593b
ZR		 896#ifdef CONFIG_MPIC_WEIRD
897 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
898#endif
899
14cf11af 900 /* Map the global registers */
7233593b
ZR		 901 mpic->gregs = ioremap(phys_addr + MPIC_INFO(GREG_BASE), 0x1000);
902 mpic->tmregs = mpic->gregs +
903 ((MPIC_INFO(TIMER_BASE) - MPIC_INFO(GREG_BASE)) >> 2);
14cf11af
PM		 904 BUG_ON(mpic->gregs == NULL);
905
906 /* Reset */
907 if (flags & MPIC_WANTS_RESET) {
7233593b
ZR		 908 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
909 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
14cf11af 910 | MPIC_GREG_GCONF_RESET);
7233593b 911 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
14cf11af
PM		 912 & MPIC_GREG_GCONF_RESET)
913 mb();
914 }
915
916 /* Read feature register, calculate num CPUs and, for non-ISU
917 * MPICs, num sources as well. On ISU MPICs, sources are counted
918 * as ISUs are added
919 */
7233593b 920 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
14cf11af
PM		 921 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
922 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
923 if (isu_size == 0)
924 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
925 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
926
927 /* Map the per-CPU registers */
928 for (i = 0; i < mpic->num_cpus; i++) {
7233593b
ZR		 929 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_INFO(CPU_BASE) +
930 i * MPIC_INFO(CPU_STRIDE), 0x1000);
14cf11af
PM		 931 BUG_ON(mpic->cpuregs[i] == NULL);
932 }
933
934 /* Initialize main ISU if none provided */
935 if (mpic->isu_size == 0) {
936 mpic->isu_size = mpic->num_sources;
7233593b
ZR		 937 mpic->isus[0] = ioremap(phys_addr + MPIC_INFO(IRQ_BASE),
938 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
14cf11af
PM		 939 BUG_ON(mpic->isus[0] == NULL);
940 }
941 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
942 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
943
944 /* Display version */
945 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
946 case 1:
947 vers = "1.0";
948 break;
949 case 2:
950 vers = "1.2";
951 break;
952 case 3:
953 vers = "1.3";
954 break;
955 default:
956 vers = "<unknown>";
957 break;
958 }
959 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n",
960 name, vers, phys_addr, mpic->num_cpus);
961 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size,
962 mpic->isu_shift, mpic->isu_mask);
963
964 mpic->next = mpics;
965 mpics = mpic;
966
0ebfff14 967 if (flags & MPIC_PRIMARY) {
14cf11af 968 mpic_primary = mpic;
0ebfff14
BH		 969 irq_set_default_host(mpic->irqhost);
970 }
14cf11af
PM		 971
972 return mpic;
973}
974
975void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
976 unsigned long phys_addr)
977{
978 unsigned int isu_first = isu_num * mpic->isu_size;
979
980 BUG_ON(isu_num >= MPIC_MAX_ISU);
981
7233593b
ZR		 982 mpic->isus[isu_num] = ioremap(phys_addr,
983 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
14cf11af
PM		 984 if ((isu_first + mpic->isu_size) > mpic->num_sources)
985 mpic->num_sources = isu_first + mpic->isu_size;
986}
987
0ebfff14
BH		 988void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
989{
990 mpic->senses = senses;
991 mpic->senses_count = count;
992}
993
14cf11af
PM		 994void __init mpic_init(struct mpic *mpic)
995{
996 int i;
997
998 BUG_ON(mpic->num_sources == 0);
0ebfff14
BH		 999 WARN_ON(mpic->num_sources > MPIC_VEC_IPI_0);
1000
1001 /* Sanitize source count */
1002 if (mpic->num_sources > MPIC_VEC_IPI_0)
1003 mpic->num_sources = MPIC_VEC_IPI_0;
14cf11af
PM		 1004
1005 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1006
1007 /* Set current processor priority to max */
7233593b 1008 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
14cf11af
PM		 1009
1010 /* Initialize timers: just disable them all */
1011 for (i = 0; i < 4; i++) {
1012 mpic_write(mpic->tmregs,
7233593b
ZR		 1013 i * MPIC_INFO(TIMER_STRIDE) +
1014 MPIC_INFO(TIMER_DESTINATION), 0);
14cf11af 1015 mpic_write(mpic->tmregs,
7233593b
ZR		 1016 i * MPIC_INFO(TIMER_STRIDE) +
1017 MPIC_INFO(TIMER_VECTOR_PRI),
14cf11af
PM		 1018 MPIC_VECPRI_MASK |
1019 (MPIC_VEC_TIMER_0 + i));
1020 }
1021
1022 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1023 mpic_test_broken_ipi(mpic);
1024 for (i = 0; i < 4; i++) {
1025 mpic_ipi_write(i,
1026 MPIC_VECPRI_MASK |
1027 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1028 (MPIC_VEC_IPI_0 + i));
14cf11af
PM		 1029 }
1030
1031 /* Initialize interrupt sources */
1032 if (mpic->irq_count == 0)
1033 mpic->irq_count = mpic->num_sources;
1034
1beb6a7d 1035 /* Do the HT PIC fixups on U3 broken mpic */
14cf11af
PM		 1036 DBG("MPIC flags: %x\n", mpic->flags);
1037 if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY))
b9e5b4e6 1038 mpic_scan_ht_pics(mpic);
14cf11af
PM		 1039
1040 for (i = 0; i < mpic->num_sources; i++) {
1041 /* start with vector = source number, and masked */
6e99e458
BH		 1042 u32 vecpri = MPIC_VECPRI_MASK | i |
1043 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
14cf11af 1044
14cf11af 1045 /* init hw */
7233593b
ZR		 1046 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1047 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
14cf11af 1048 1 << hard_smp_processor_id());
14cf11af
PM		 1049 }
1050
1051 /* Init spurrious vector */
7233593b 1052 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), MPIC_VEC_SPURRIOUS);
14cf11af 1053
7233593b
ZR		 1054 /* Disable 8259 passthrough, if supported */
1055 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1056 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1057 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1058 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
14cf11af
PM		 1059
1060 /* Set current processor priority to 0 */
7233593b 1061 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
14cf11af
PM		 1062}
1063
868ea0c9
MG		 1064void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1065{
1066 u32 v;
1067
1068 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1069 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1070 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1071 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1072}
14cf11af 1073
868ea0c9
MG		 1074void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1075{
ba1826e5 1076 unsigned long flags;
868ea0c9
MG		 1077 u32 v;
1078
ba1826e5 1079 spin_lock_irqsave(&mpic_lock, flags);
868ea0c9
MG		 1080 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1081 if (enable)
1082 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1083 else
1084 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1085 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
ba1826e5 1086 spin_unlock_irqrestore(&mpic_lock, flags);
868ea0c9 1087}
14cf11af
PM		 1088
1089void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1090{
1091 int is_ipi;
1092 struct mpic *mpic = mpic_find(irq, &is_ipi);
0ebfff14 1093 unsigned int src = mpic_irq_to_hw(irq);
14cf11af
PM		 1094 unsigned long flags;
1095 u32 reg;
1096
1097 spin_lock_irqsave(&mpic_lock, flags);
1098 if (is_ipi) {
0ebfff14 1099 reg = mpic_ipi_read(src - MPIC_VEC_IPI_0) &
e5356640 1100 ~MPIC_VECPRI_PRIORITY_MASK;
0ebfff14 1101 mpic_ipi_write(src - MPIC_VEC_IPI_0,
14cf11af
PM		 1102 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1103 } else {
7233593b 1104 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
e5356640 1105 & ~MPIC_VECPRI_PRIORITY_MASK;
7233593b 1106 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
14cf11af
PM		 1107 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1108 }
1109 spin_unlock_irqrestore(&mpic_lock, flags);
1110}
1111
1112unsigned int mpic_irq_get_priority(unsigned int irq)
1113{
1114 int is_ipi;
1115 struct mpic *mpic = mpic_find(irq, &is_ipi);
0ebfff14 1116 unsigned int src = mpic_irq_to_hw(irq);
14cf11af
PM		 1117 unsigned long flags;
1118 u32 reg;
1119
1120 spin_lock_irqsave(&mpic_lock, flags);
1121 if (is_ipi)
0ebfff14 1122 reg = mpic_ipi_read(src = MPIC_VEC_IPI_0);
14cf11af 1123 else
7233593b 1124 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
14cf11af
PM		 1125 spin_unlock_irqrestore(&mpic_lock, flags);
1126 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
1127}
1128
1129void mpic_setup_this_cpu(void)
1130{
1131#ifdef CONFIG_SMP
1132 struct mpic *mpic = mpic_primary;
1133 unsigned long flags;
1134 u32 msk = 1 << hard_smp_processor_id();
1135 unsigned int i;
1136
1137 BUG_ON(mpic == NULL);
1138
1139 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1140
1141 spin_lock_irqsave(&mpic_lock, flags);
1142
1143 /* let the mpic know we want intrs. default affinity is 0xffffffff
1144 * until changed via /proc. That's how it's done on x86. If we want
1145 * it differently, then we should make sure we also change the default
a53da52f 1146 * values of irq_desc[].affinity in irq.c.
14cf11af
PM		 1147 */
1148 if (distribute_irqs) {
1149 for (i = 0; i < mpic->num_sources ; i++)
7233593b
ZR		 1150 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1151 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
14cf11af
PM		 1152 }
1153
1154 /* Set current processor priority to 0 */
7233593b 1155 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
14cf11af
PM		 1156
1157 spin_unlock_irqrestore(&mpic_lock, flags);
1158#endif /* CONFIG_SMP */
1159}
1160
1161int mpic_cpu_get_priority(void)
1162{
1163 struct mpic *mpic = mpic_primary;
1164
7233593b 1165 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
14cf11af
PM		 1166}
1167
1168void mpic_cpu_set_priority(int prio)
1169{
1170 struct mpic *mpic = mpic_primary;
1171
1172 prio &= MPIC_CPU_TASKPRI_MASK;
7233593b 1173 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
14cf11af
PM		 1174}
1175
1176/*
1177 * XXX: someone who knows mpic should check this.
1178 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
1179 * or can we reset the mpic in the new kernel?
1180 */
1181void mpic_teardown_this_cpu(int secondary)
1182{
1183 struct mpic *mpic = mpic_primary;
1184 unsigned long flags;
1185 u32 msk = 1 << hard_smp_processor_id();
1186 unsigned int i;
1187
1188 BUG_ON(mpic == NULL);
1189
1190 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1191 spin_lock_irqsave(&mpic_lock, flags);
1192
1193 /* let the mpic know we don't want intrs. */
1194 for (i = 0; i < mpic->num_sources ; i++)
7233593b
ZR		 1195 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1196 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
14cf11af
PM		 1197
1198 /* Set current processor priority to max */
7233593b 1199 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
14cf11af
PM		 1200
1201 spin_unlock_irqrestore(&mpic_lock, flags);
1202}
1203
1204
1205void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1206{
1207 struct mpic *mpic = mpic_primary;
1208
1209 BUG_ON(mpic == NULL);
1210
1beb6a7d 1211#ifdef DEBUG_IPI
14cf11af 1212 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1beb6a7d 1213#endif
14cf11af 1214
7233593b
ZR		 1215 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1216 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
14cf11af
PM		 1217 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1218}
1219
0ebfff14 1220unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
14cf11af 1221{
0ebfff14 1222 u32 src;
14cf11af 1223
7233593b 1224 src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
1beb6a7d 1225#ifdef DEBUG_LOW
0ebfff14 1226 DBG("%s: get_one_irq(): %d\n", mpic->name, src);
1beb6a7d 1227#endif
0ebfff14
BH		 1228 if (unlikely(src == MPIC_VEC_SPURRIOUS))
1229 return NO_IRQ;
1230 return irq_linear_revmap(mpic->irqhost, src);
14cf11af
PM		 1231}
1232
0ebfff14 1233unsigned int mpic_get_irq(struct pt_regs *regs)
14cf11af
PM		 1234{
1235 struct mpic *mpic = mpic_primary;
1236
1237 BUG_ON(mpic == NULL);
1238
1239 return mpic_get_one_irq(mpic, regs);
1240}
1241
1242
1243#ifdef CONFIG_SMP
1244void mpic_request_ipis(void)
1245{
1246 struct mpic *mpic = mpic_primary;
0ebfff14
BH		 1247 int i;
1248 static char *ipi_names[] = {
1249 "IPI0 (call function)",
1250 "IPI1 (reschedule)",
1251 "IPI2 (unused)",
1252 "IPI3 (debugger break)",
1253 };
14cf11af 1254 BUG_ON(mpic == NULL);
14cf11af 1255
0ebfff14
BH		 1256 printk(KERN_INFO "mpic: requesting IPIs ... \n");
1257
1258 for (i = 0; i < 4; i++) {
1259 unsigned int vipi = irq_create_mapping(mpic->irqhost,
6e99e458 1260 MPIC_VEC_IPI_0 + i);
0ebfff14
BH		 1261 if (vipi == NO_IRQ) {
1262 printk(KERN_ERR "Failed to map IPI %d\n", i);
1263 break;
1264 }
1265 request_irq(vipi, mpic_ipi_action, IRQF_DISABLED,
1266 ipi_names[i], mpic);
1267 }
14cf11af 1268}
a9c59264
PM		 1269
1270void smp_mpic_message_pass(int target, int msg)
1271{
1272 /* make sure we're sending something that translates to an IPI */
1273 if ((unsigned int)msg > 3) {
1274 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1275 smp_processor_id(), msg);
1276 return;
1277 }
1278 switch (target) {
1279 case MSG_ALL:
1280 mpic_send_ipi(msg, 0xffffffff);
1281 break;
1282 case MSG_ALL_BUT_SELF:
1283 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1284 break;
1285 default:
1286 mpic_send_ipi(msg, 1 << target);
1287 break;
1288 }
1289}
14cf11af 1290#endif /* CONFIG_SMP */
Linux 6.x block layer and io_uring tree(s)