[linux-2.6-block.git] / arch / powerpc / sysdev / mpc8xx_pic.c

#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/signal.h>
#include <linux/irq.h>
#include <linux/dma-mapping.h>
#include <asm/prom.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/8xx_immap.h>

#include "mpc8xx_pic.h"


#define PIC_VEC_SPURRIOUS      15

extern int cpm_get_irq(struct pt_regs *regs);

static struct irq_domain *mpc8xx_pic_host;
#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
static sysconf8xx_t __iomem *siu_reg;

int cpm_get_irq(struct pt_regs *regs);

static void mpc8xx_unmask_irq(struct irq_data *d)
{
	int	bit, word;
	unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);

	bit = irq_nr & 0x1f;
	word = irq_nr >> 5;

	ppc_cached_irq_mask[word] |= (1 << (31-bit));
	out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
}

static void mpc8xx_mask_irq(struct irq_data *d)
{
	int	bit, word;
	unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);

	bit = irq_nr & 0x1f;
	word = irq_nr >> 5;

	ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
	out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
}

static void mpc8xx_ack(struct irq_data *d)
{
	int	bit;
	unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);

	bit = irq_nr & 0x1f;
	out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
}

static void mpc8xx_end_irq(struct irq_data *d)
{
	int bit, word;
	unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);

	bit = irq_nr & 0x1f;
	word = irq_nr >> 5;

	ppc_cached_irq_mask[word] |= (1 << (31-bit));
	out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
}

static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
{
	if (flow_type & IRQ_TYPE_EDGE_FALLING) {
		irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
		unsigned int siel = in_be32(&siu_reg->sc_siel);

		/* only external IRQ senses are programmable */
		if ((hw & 1) == 0) {
			siel |= (0x80000000 >> hw);
			out_be32(&siu_reg->sc_siel, siel);
			__irq_set_handler_locked(d->irq, handle_edge_irq);
		}
	}
	return 0;
}

static struct irq_chip mpc8xx_pic = {
	.name = "MPC8XX SIU",
	.irq_unmask = mpc8xx_unmask_irq,
	.irq_mask = mpc8xx_mask_irq,
	.irq_ack = mpc8xx_ack,
	.irq_eoi = mpc8xx_end_irq,
	.irq_set_type = mpc8xx_set_irq_type,
};

unsigned int mpc8xx_get_irq(void)
{
	int irq;

	/* For MPC8xx, read the SIVEC register and shift the bits down
	 * to get the irq number.
	 */
	irq = in_be32(&siu_reg->sc_sivec) >> 26;

	if (irq == PIC_VEC_SPURRIOUS)
		irq = NO_IRQ;

        return irq_linear_revmap(mpc8xx_pic_host, irq);

}

static int mpc8xx_pic_host_map(struct irq_domain *h, unsigned int virq,
			  irq_hw_number_t hw)
{
	pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);

	/* Set default irq handle */
	irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
	return 0;
}


static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
			    const u32 *intspec, unsigned int intsize,
			    irq_hw_number_t *out_hwirq, unsigned int *out_flags)
{
	static unsigned char map_pic_senses[4] = {
		IRQ_TYPE_EDGE_RISING,
		IRQ_TYPE_LEVEL_LOW,
		IRQ_TYPE_LEVEL_HIGH,
		IRQ_TYPE_EDGE_FALLING,
	};

	*out_hwirq = intspec[0];
	if (intsize > 1 && intspec[1] < 4)
		*out_flags = map_pic_senses[intspec[1]];
	else
		*out_flags = IRQ_TYPE_NONE;

	return 0;
}


static struct irq_domain_ops mpc8xx_pic_host_ops = {
	.map = mpc8xx_pic_host_map,
	.xlate = mpc8xx_pic_host_xlate,
};

int mpc8xx_pic_init(void)
{
	struct resource res;
	struct device_node *np;
	int ret;

	np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic");
	if (np == NULL)
		np = of_find_node_by_type(NULL, "mpc8xx-pic");
	if (np == NULL) {
		printk(KERN_ERR "Could not find fsl,pq1-pic node\n");
		return -ENOMEM;
	}

	ret = of_address_to_resource(np, 0, &res);
	if (ret)
		goto out;

	siu_reg = ioremap(res.start, resource_size(&res));
	if (siu_reg == NULL) {
		ret = -EINVAL;
		goto out;
	}

	mpc8xx_pic_host = irq_domain_add_linear(np, 64, &mpc8xx_pic_host_ops, NULL);
	if (mpc8xx_pic_host == NULL) {
		printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");
		ret = -ENOMEM;
		goto out;
	}
	return 0;

out:
	of_node_put(np);
	return ret;
}
Commit	Line	Data
f2a0bd37	1	#include <linux/kernel.h>
f2a0bd37 VB	2	#include <linux/stddef.h>
	3	#include <linux/init.h>
	4	#include <linux/sched.h>
	5	#include <linux/signal.h>
	6	#include <linux/irq.h>
	7	#include <linux/dma-mapping.h>
	8	#include <asm/prom.h>
	9	#include <asm/irq.h>
	10	#include <asm/io.h>
	11	#include <asm/8xx_immap.h>
f2a0bd37 VB	12
	13	#include "mpc8xx_pic.h"
	14
	15
	16	#define PIC_VEC_SPURRIOUS 15
	17
	18	extern int cpm_get_irq(struct pt_regs *regs);
	19
bae1d8f1	20	static struct irq_domain *mpc8xx_pic_host;
f2a0bd37 VB	21	#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
f2a0bd37 VB	22	static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
fb533d0c	23	static sysconf8xx_t __iomem *siu_reg;
f2a0bd37 VB	24
	25	int cpm_get_irq(struct pt_regs *regs);
	26
febd4017	27	static void mpc8xx_unmask_irq(struct irq_data *d)
f2a0bd37 VB	28	{
f2a0bd37 VB	29	int bit, word;
476eb491	30	unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
f2a0bd37 VB	31
	32	bit = irq_nr & 0x1f;
	33	word = irq_nr >> 5;
	34
	35	ppc_cached_irq_mask[word] \|= (1 << (31-bit));
	36	out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
	37	}
	38
febd4017	39	static void mpc8xx_mask_irq(struct irq_data *d)
f2a0bd37 VB	40	{
f2a0bd37 VB	41	int bit, word;
476eb491	42	unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
f2a0bd37 VB	43
	44	bit = irq_nr & 0x1f;
	45	word = irq_nr >> 5;
	46
	47	ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
	48	out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
	49	}
	50
febd4017	51	static void mpc8xx_ack(struct irq_data *d)
f2a0bd37 VB	52	{
f2a0bd37 VB	53	int bit;
476eb491	54	unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
f2a0bd37 VB	55
	56	bit = irq_nr & 0x1f;
	57	out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
	58	}
	59
febd4017	60	static void mpc8xx_end_irq(struct irq_data *d)
f2a0bd37 VB	61	{
f2a0bd37 VB	62	int bit, word;
476eb491	63	unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
f2a0bd37 VB	64
	65	bit = irq_nr & 0x1f;
	66	word = irq_nr >> 5;
	67
	68	ppc_cached_irq_mask[word] \|= (1 << (31-bit));
	69	out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
	70	}
	71
febd4017	72	static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
f2a0bd37	73	{
f2a0bd37	74	if (flow_type & IRQ_TYPE_EDGE_FALLING) {
476eb491	75	irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
f2a0bd37 VB	76	unsigned int siel = in_be32(&siu_reg->sc_siel);
	77
	78	/* only external IRQ senses are programmable */
	79	if ((hw & 1) == 0) {
	80	siel \|= (0x80000000 >> hw);
	81	out_be32(&siu_reg->sc_siel, siel);
b3cf2bb3	82	__irq_set_handler_locked(d->irq, handle_edge_irq);
f2a0bd37 VB	83	}
	84	}
	85	return 0;
	86	}
	87
	88	static struct irq_chip mpc8xx_pic = {
fc380c0c	89	.name = "MPC8XX SIU",
febd4017 LB	90	.irq_unmask = mpc8xx_unmask_irq,
	91	.irq_mask = mpc8xx_mask_irq,
	92	.irq_ack = mpc8xx_ack,
	93	.irq_eoi = mpc8xx_end_irq,
	94	.irq_set_type = mpc8xx_set_irq_type,
f2a0bd37 VB	95	};
	96
	97	unsigned int mpc8xx_get_irq(void)
	98	{
	99	int irq;
	100
	101	/* For MPC8xx, read the SIVEC register and shift the bits down
	102	* to get the irq number.
	103	*/
	104	irq = in_be32(&siu_reg->sc_sivec) >> 26;
	105
	106	if (irq == PIC_VEC_SPURRIOUS)
	107	irq = NO_IRQ;
	108
	109	return irq_linear_revmap(mpc8xx_pic_host, irq);
	110
	111	}
	112
bae1d8f1	113	static int mpc8xx_pic_host_map(struct irq_domain *h, unsigned int virq,
f2a0bd37 VB	114	irq_hw_number_t hw)
	115	{
	116	pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
	117
	118	/* Set default irq handle */
ec775d0e	119	irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
f2a0bd37 VB	120	return 0;
	121	}
	122
	123
bae1d8f1	124	static int mpc8xx_pic_host_xlate(struct irq_domain h, struct device_node ct,
40d50cf7	125	const u32 *intspec, unsigned int intsize,
f2a0bd37 VB	126	irq_hw_number_t out_hwirq, unsigned int out_flags)
	127	{
	128	static unsigned char map_pic_senses[4] = {
	129	IRQ_TYPE_EDGE_RISING,
	130	IRQ_TYPE_LEVEL_LOW,
	131	IRQ_TYPE_LEVEL_HIGH,
	132	IRQ_TYPE_EDGE_FALLING,
	133	};
	134
	135	*out_hwirq = intspec[0];
	136	if (intsize > 1 && intspec[1] < 4)
	137	*out_flags = map_pic_senses[intspec[1]];
	138	else
	139	*out_flags = IRQ_TYPE_NONE;
	140
	141	return 0;
	142	}
	143
	144
bae1d8f1	145	static struct irq_domain_ops mpc8xx_pic_host_ops = {
f2a0bd37 VB	146	.map = mpc8xx_pic_host_map,
	147	.xlate = mpc8xx_pic_host_xlate,
	148	};
	149
	150	int mpc8xx_pic_init(void)
	151	{
	152	struct resource res;
fb533d0c	153	struct device_node *np;
f2a0bd37 VB	154	int ret;
f2a0bd37 VB	155
fb533d0c SW	156	np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic");
	157	if (np == NULL)
	158	np = of_find_node_by_type(NULL, "mpc8xx-pic");
f2a0bd37	159	if (np == NULL) {
fb533d0c	160	printk(KERN_ERR "Could not find fsl,pq1-pic node\n");
f2a0bd37 VB	161	return -ENOMEM;
	162	}
	163
f2a0bd37	164	ret = of_address_to_resource(np, 0, &res);
f2a0bd37	165	if (ret)
52964f87	166	goto out;
f2a0bd37	167
28f65c11	168	siu_reg = ioremap(res.start, resource_size(&res));
b1725c93 JL	169	if (siu_reg == NULL) {
	170	ret = -EINVAL;
	171	goto out;
	172	}
f2a0bd37	173
a8db8cf0	174	mpc8xx_pic_host = irq_domain_add_linear(np, 64, &mpc8xx_pic_host_ops, NULL);
f2a0bd37 VB	175	if (mpc8xx_pic_host == NULL) {
	176	printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");
	177	ret = -ENOMEM;
b1725c93	178	goto out;
f2a0bd37	179	}
b1725c93	180	return 0;
f2a0bd37	181
52964f87 ME	182	out:
52964f87 ME	183	of_node_put(np);
f2a0bd37 VB	184	return ret;
f2a0bd37 VB	185	}