[linux-block.git] / arch / powerpc / sysdev / indirect_pci.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Support for indirect PCI bridges.
 *
 * Copyright (C) 1998 Gabriel Paubert.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>

#include <asm/io.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>

int __indirect_read_config(struct pci_controller *hose,
			   unsigned char bus_number, unsigned int devfn,
			   int offset, int len, u32 *val)
{
	volatile void __iomem *cfg_data;
	u8 cfg_type = 0;
	u32 bus_no, reg;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
		if (bus_number != hose->first_busno)
			return PCIBIOS_DEVICE_NOT_FOUND;
		if (devfn != 0)
			return PCIBIOS_DEVICE_NOT_FOUND;
	}

	if (ppc_md.pci_exclude_device)
		if (ppc_md.pci_exclude_device(hose, bus_number, devfn))
			return PCIBIOS_DEVICE_NOT_FOUND;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
		if (bus_number != hose->first_busno)
			cfg_type = 1;

	bus_no = (bus_number == hose->first_busno) ?
			hose->self_busno : bus_number;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
	else
		reg = offset & 0xfc;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
			 (devfn << 8) | reg | cfg_type));
	else
		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
			 (devfn << 8) | reg | cfg_type));

	/*
	 * Note: the caller has already checked that offset is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	cfg_data = hose->cfg_data + (offset & 3);
	switch (len) {
	case 1:
		*val = in_8(cfg_data);
		break;
	case 2:
		*val = in_le16(cfg_data);
		break;
	default:
		*val = in_le32(cfg_data);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
			 int offset, int len, u32 *val)
{
	struct pci_controller *hose = pci_bus_to_host(bus);

	return __indirect_read_config(hose, bus->number, devfn, offset, len,
				      val);
}

int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
			  int offset, int len, u32 val)
{
	struct pci_controller *hose = pci_bus_to_host(bus);
	volatile void __iomem *cfg_data;
	u8 cfg_type = 0;
	u32 bus_no, reg;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
		if (bus->number != hose->first_busno)
			return PCIBIOS_DEVICE_NOT_FOUND;
		if (devfn != 0)
			return PCIBIOS_DEVICE_NOT_FOUND;
	}

	if (ppc_md.pci_exclude_device)
		if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
			return PCIBIOS_DEVICE_NOT_FOUND;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
		if (bus->number != hose->first_busno)
			cfg_type = 1;

	bus_no = (bus->number == hose->first_busno) ?
			hose->self_busno : bus->number;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
	else
		reg = offset & 0xfc;

	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
			 (devfn << 8) | reg | cfg_type));
	else
		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
			 (devfn << 8) | reg | cfg_type));

	/* suppress setting of PCI_PRIMARY_BUS */
	if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
		if ((offset == PCI_PRIMARY_BUS) &&
			(bus->number == hose->first_busno))
		val &= 0xffffff00;

	/* Workaround for PCI_28 Errata in 440EPx/GRx */
	if ((hose->indirect_type & PPC_INDIRECT_TYPE_BROKEN_MRM) &&
			offset == PCI_CACHE_LINE_SIZE) {
		val = 0;
	}

	/*
	 * Note: the caller has already checked that offset is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	cfg_data = hose->cfg_data + (offset & 3);
	switch (len) {
	case 1:
		out_8(cfg_data, val);
		break;
	case 2:
		out_le16(cfg_data, val);
		break;
	default:
		out_le32(cfg_data, val);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops indirect_pci_ops =
{
	.read = indirect_read_config,
	.write = indirect_write_config,
};

void setup_indirect_pci(struct pci_controller *hose, resource_size_t cfg_addr,
			resource_size_t cfg_data, u32 flags)
{
	resource_size_t base = cfg_addr & PAGE_MASK;
	void __iomem *mbase;

	mbase = ioremap(base, PAGE_SIZE);
	hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
	if ((cfg_data & PAGE_MASK) != base)
		mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
	hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
	hose->ops = &indirect_pci_ops;
	hose->indirect_type = flags;
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
daec962e PM	2	/*
	3	* Support for indirect PCI bridges.
	4	*
	5	* Copyright (C) 1998 Gabriel Paubert.
daec962e PM	6	*/
	7
	8	#include <linux/kernel.h>
	9	#include <linux/pci.h>
	10	#include <linux/delay.h>
	11	#include <linux/string.h>
	12	#include <linux/init.h>
	13
	14	#include <asm/io.h>
daec962e PM	15	#include <asm/pci-bridge.h>
	16	#include <asm/machdep.h>
	17
6d5f6a0e KP	18	int __indirect_read_config(struct pci_controller *hose,
	19	unsigned char bus_number, unsigned int devfn,
	20	int offset, int len, u32 *val)
daec962e	21	{
daec962e PM	22	volatile void __iomem *cfg_data;
daec962e PM	23	u8 cfg_type = 0;
ab0f9ad3	24	u32 bus_no, reg;
daec962e	25
62c66c8e	26	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
6d5f6a0e	27	if (bus_number != hose->first_busno)
62c66c8e KG	28	return PCIBIOS_DEVICE_NOT_FOUND;
	29	if (devfn != 0)
	30	return PCIBIOS_DEVICE_NOT_FOUND;
	31	}
	32
daec962e	33	if (ppc_md.pci_exclude_device)
6d5f6a0e	34	if (ppc_md.pci_exclude_device(hose, bus_number, devfn))
daec962e	35	return PCIBIOS_DEVICE_NOT_FOUND;
62c66c8e	36
ab0f9ad3	37	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
6d5f6a0e	38	if (bus_number != hose->first_busno)
daec962e PM	39	cfg_type = 1;
daec962e PM	40
6d5f6a0e KP	41	bus_no = (bus_number == hose->first_busno) ?
6d5f6a0e KP	42	hose->self_busno : bus_number;
5ab65ecd	43
ab0f9ad3 KG	44	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
	45	reg = ((offset & 0xf00) << 16) \| (offset & 0xfc);
	46	else
	47	reg = offset & 0xfc;
	48
2e56ff20 KG	49	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
	50	out_be32(hose->cfg_addr, (0x80000000 \| (bus_no << 16) \|
	51	(devfn << 8) \| reg \| cfg_type));
	52	else
	53	out_le32(hose->cfg_addr, (0x80000000 \| (bus_no << 16) \|
	54	(devfn << 8) \| reg \| cfg_type));
daec962e PM	55
	56	/*
	57	* Note: the caller has already checked that offset is
	58	* suitably aligned and that len is 1, 2 or 4.
	59	*/
	60	cfg_data = hose->cfg_data + (offset & 3);
	61	switch (len) {
	62	case 1:
	63	*val = in_8(cfg_data);
	64	break;
	65	case 2:
	66	*val = in_le16(cfg_data);
	67	break;
	68	default:
	69	*val = in_le32(cfg_data);
	70	break;
	71	}
	72	return PCIBIOS_SUCCESSFUL;
	73	}
	74
6d5f6a0e KP	75	int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
	76	int offset, int len, u32 *val)
	77	{
	78	struct pci_controller *hose = pci_bus_to_host(bus);
	79
	80	return __indirect_read_config(hose, bus->number, devfn, offset, len,
	81	val);
	82	}
	83
50d8f87d RI	84	int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
50d8f87d RI	85	int offset, int len, u32 val)
daec962e	86	{
19afa407	87	struct pci_controller *hose = pci_bus_to_host(bus);
daec962e PM	88	volatile void __iomem *cfg_data;
daec962e PM	89	u8 cfg_type = 0;
ab0f9ad3	90	u32 bus_no, reg;
daec962e	91
62c66c8e KG	92	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
	93	if (bus->number != hose->first_busno)
	94	return PCIBIOS_DEVICE_NOT_FOUND;
	95	if (devfn != 0)
	96	return PCIBIOS_DEVICE_NOT_FOUND;
	97	}
	98
daec962e	99	if (ppc_md.pci_exclude_device)
7d52c7b0	100	if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
daec962e PM	101	return PCIBIOS_DEVICE_NOT_FOUND;
daec962e PM	102
ab0f9ad3	103	if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
daec962e PM	104	if (bus->number != hose->first_busno)
	105	cfg_type = 1;
	106
5ab65ecd	107	bus_no = (bus->number == hose->first_busno) ?
0a3786c5	108	hose->self_busno : bus->number;
5ab65ecd	109
ab0f9ad3 KG	110	if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
	111	reg = ((offset & 0xf00) << 16) \| (offset & 0xfc);
	112	else
	113	reg = offset & 0xfc;
	114
2e56ff20 KG	115	if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
	116	out_be32(hose->cfg_addr, (0x80000000 \| (bus_no << 16) \|
	117	(devfn << 8) \| reg \| cfg_type));
	118	else
	119	out_le32(hose->cfg_addr, (0x80000000 \| (bus_no << 16) \|
	120	(devfn << 8) \| reg \| cfg_type));
daec962e	121
25985edc	122	/* suppress setting of PCI_PRIMARY_BUS */
476f5779 KG	123	if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
	124	if ((offset == PCI_PRIMARY_BUS) &&
	125	(bus->number == hose->first_busno))
	126	val &= 0xffffff00;
	127
5ce4b596 JB	128	/* Workaround for PCI_28 Errata in 440EPx/GRx */
	129	if ((hose->indirect_type & PPC_INDIRECT_TYPE_BROKEN_MRM) &&
	130	offset == PCI_CACHE_LINE_SIZE) {
	131	val = 0;
	132	}
	133
daec962e PM	134	/*
	135	* Note: the caller has already checked that offset is
	136	* suitably aligned and that len is 1, 2 or 4.
	137	*/
	138	cfg_data = hose->cfg_data + (offset & 3);
	139	switch (len) {
	140	case 1:
	141	out_8(cfg_data, val);
	142	break;
	143	case 2:
	144	out_le16(cfg_data, val);
	145	break;
	146	default:
	147	out_le32(cfg_data, val);
	148	break;
	149	}
	150	return PCIBIOS_SUCCESSFUL;
	151	}
	152
	153	static struct pci_ops indirect_pci_ops =
	154	{
c78d453b NL	155	.read = indirect_read_config,
c78d453b NL	156	.write = indirect_write_config,
daec962e PM	157	};
daec962e PM	158
1e83bf87 CE	159	void setup_indirect_pci(struct pci_controller *hose, resource_size_t cfg_addr,
1e83bf87 CE	160	resource_size_t cfg_data, u32 flags)
daec962e	161	{
d94bad82	162	resource_size_t base = cfg_addr & PAGE_MASK;
d5269966	163	void __iomem *mbase;
daec962e PM	164
daec962e PM	165	mbase = ioremap(base, PAGE_SIZE);
d5269966	166	hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
daec962e PM	167	if ((cfg_data & PAGE_MASK) != base)
daec962e PM	168	mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
d5269966 KG	169	hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
d5269966 KG	170	hose->ops = &indirect_pci_ops;
7659c038	171	hose->indirect_type = flags;
daec962e	172	}