Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
eed32001 KG |
2 | #ifndef __PPC_FSL_SOC_H |
3 | #define __PPC_FSL_SOC_H | |
4 | #ifdef __KERNEL__ | |
5 | ||
3d574abd SW |
6 | #include <asm/mmu.h> |
7 | ||
364fdbc0 AV |
8 | struct spi_device; |
9 | ||
eed32001 | 10 | extern phys_addr_t get_immrbase(void); |
ea16e83a | 11 | #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) |
fba43665 VB |
12 | extern u32 get_brgfreq(void); |
13 | extern u32 get_baudrate(void); | |
a5dae76a AV |
14 | #else |
15 | static inline u32 get_brgfreq(void) { return -1; } | |
16 | static inline u32 get_baudrate(void) { return -1; } | |
17 | #endif | |
38664095 | 18 | extern u32 fsl_get_sys_freq(void); |
eed32001 | 19 | |
26f6cb99 | 20 | struct spi_board_info; |
d49747bd | 21 | struct device_node; |
26f6cb99 | 22 | |
7653aaab TT |
23 | /* The different ports that the DIU can be connected to */ |
24 | enum fsl_diu_monitor_port { | |
25 | FSL_DIU_PORT_DVI, /* DVI */ | |
26 | FSL_DIU_PORT_LVDS, /* Single-link LVDS */ | |
27 | FSL_DIU_PORT_DLVDS /* Dual-link LVDS */ | |
28 | }; | |
29 | ||
6f90a8bd | 30 | struct platform_diu_data_ops { |
7653aaab TT |
31 | u32 (*get_pixel_format)(enum fsl_diu_monitor_port port, |
32 | unsigned int bpp); | |
33 | void (*set_gamma_table)(enum fsl_diu_monitor_port port, | |
34 | char *gamma_table_base); | |
35 | void (*set_monitor_port)(enum fsl_diu_monitor_port port); | |
36 | void (*set_pixel_clock)(unsigned int pixclock); | |
37 | enum fsl_diu_monitor_port (*valid_monitor_port) | |
38 | (enum fsl_diu_monitor_port port); | |
39 | void (*release_bootmem)(void); | |
6f90a8bd YS |
40 | }; |
41 | ||
42 | extern struct platform_diu_data_ops diu_ops; | |
6f90a8bd | 43 | |
95ec77c0 DA |
44 | void __noreturn fsl_hv_restart(char *cmd); |
45 | void __noreturn fsl_hv_halt(void); | |
d173ea6b | 46 | |
eed32001 KG |
47 | #endif |
48 | #endif |