Commit | Line | Data |
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eed32001 KG |
1 | #ifndef __PPC_FSL_SOC_H |
2 | #define __PPC_FSL_SOC_H | |
3 | #ifdef __KERNEL__ | |
4 | ||
3d574abd SW |
5 | #include <asm/mmu.h> |
6 | ||
364fdbc0 AV |
7 | struct spi_device; |
8 | ||
eed32001 | 9 | extern phys_addr_t get_immrbase(void); |
a5dae76a | 10 | #if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx) |
fba43665 VB |
11 | extern u32 get_brgfreq(void); |
12 | extern u32 get_baudrate(void); | |
a5dae76a AV |
13 | #else |
14 | static inline u32 get_brgfreq(void) { return -1; } | |
15 | static inline u32 get_baudrate(void) { return -1; } | |
16 | #endif | |
38664095 | 17 | extern u32 fsl_get_sys_freq(void); |
eed32001 | 18 | |
26f6cb99 | 19 | struct spi_board_info; |
d49747bd | 20 | struct device_node; |
26f6cb99 | 21 | |
e1c1575f | 22 | extern void fsl_rstcr_restart(char *cmd); |
6f90a8bd YS |
23 | |
24 | #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) | |
7653aaab TT |
25 | |
26 | /* The different ports that the DIU can be connected to */ | |
27 | enum fsl_diu_monitor_port { | |
28 | FSL_DIU_PORT_DVI, /* DVI */ | |
29 | FSL_DIU_PORT_LVDS, /* Single-link LVDS */ | |
30 | FSL_DIU_PORT_DLVDS /* Dual-link LVDS */ | |
31 | }; | |
32 | ||
6f90a8bd | 33 | struct platform_diu_data_ops { |
7653aaab TT |
34 | u32 (*get_pixel_format)(enum fsl_diu_monitor_port port, |
35 | unsigned int bpp); | |
36 | void (*set_gamma_table)(enum fsl_diu_monitor_port port, | |
37 | char *gamma_table_base); | |
38 | void (*set_monitor_port)(enum fsl_diu_monitor_port port); | |
39 | void (*set_pixel_clock)(unsigned int pixclock); | |
40 | enum fsl_diu_monitor_port (*valid_monitor_port) | |
41 | (enum fsl_diu_monitor_port port); | |
42 | void (*release_bootmem)(void); | |
6f90a8bd YS |
43 | }; |
44 | ||
45 | extern struct platform_diu_data_ops diu_ops; | |
6f90a8bd YS |
46 | #endif |
47 | ||
d173ea6b TT |
48 | void fsl_hv_restart(char *cmd); |
49 | void fsl_hv_halt(void); | |
50 | ||
eed32001 KG |
51 | #endif |
52 | #endif |