[linux-block.git] / arch / powerpc / sysdev / fsl_rio.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Freescale MPC85xx/MPC86xx RapidIO support
 *
 * Copyright 2009 Sysgo AG
 * Thomas Moll <thomas.moll@sysgo.com>
 * - fixed maintenance access routines, check for aligned access
 *
 * Copyright 2009 Integrated Device Technology, Inc.
 * Alex Bounine <alexandre.bounine@idt.com>
 * - Added Port-Write message handling
 * - Added Machine Check exception handling
 *
 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
 * Zhang Wei <wei.zhang@freescale.com>
 * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
 * Liu Gang <Gang.Liu@freescale.com>
 *
 * Copyright 2005 MontaVista Software, Inc.
 * Matt Porter <mporter@kernel.crashing.org>
 */

#ifndef __FSL_RIO_H
#define __FSL_RIO_H

#include <linux/rio.h>
#include <linux/rio_drv.h>
#include <linux/kfifo.h>

#define RIO_REGS_WIN(mport)	(((struct rio_priv *)(mport->priv))->regs_win)

#define RIO_MAINT_WIN_SIZE	0x400000
#define RIO_LTLEDCSR		0x0608

#define DOORBELL_ROWAR_EN	0x80000000
#define DOORBELL_ROWAR_TFLOWLV	0x08000000 /* highest priority level */
#define DOORBELL_ROWAR_PCI	0x02000000 /* PCI window */
#define DOORBELL_ROWAR_NREAD	0x00040000 /* NREAD */
#define DOORBELL_ROWAR_MAINTRD	0x00070000  /* maintenance read */
#define DOORBELL_ROWAR_RES	0x00002000 /* wrtpy: reserved */
#define DOORBELL_ROWAR_MAINTWD	0x00007000
#define DOORBELL_ROWAR_SIZE	0x0000000b /* window size is 4k */

#define RIO_ATMU_REGS_PORT1_OFFSET	0x10c00
#define RIO_ATMU_REGS_PORT2_OFFSET	0x10e00
#define RIO_S_DBELL_REGS_OFFSET	0x13400
#define RIO_S_PW_REGS_OFFSET	0x134e0
#define RIO_ATMU_REGS_DBELL_OFFSET	0x10C40
#define RIO_INB_ATMU_REGS_PORT1_OFFSET 0x10d60
#define RIO_INB_ATMU_REGS_PORT2_OFFSET 0x10f60

#define MAX_MSG_UNIT_NUM	2
#define MAX_PORT_NUM		4
#define RIO_INB_ATMU_COUNT	4

struct rio_atmu_regs {
	 u32 rowtar;
	 u32 rowtear;
	 u32 rowbar;
	 u32 pad1;
	 u32 rowar;
	 u32 pad2[3];
};

struct rio_inb_atmu_regs {
	u32 riwtar;
	u32 pad1;
	u32 riwbar;
	u32 pad2;
	u32 riwar;
	u32 pad3[3];
};

struct rio_dbell_ring {
	void *virt;
	dma_addr_t phys;
};

struct rio_port_write_msg {
	 void *virt;
	 dma_addr_t phys;
	 u32 msg_count;
	 u32 err_count;
	 u32 discard_count;
};

struct fsl_rio_dbell {
	struct rio_mport *mport[MAX_PORT_NUM];
	struct device *dev;
	struct rio_dbell_regs __iomem *dbell_regs;
	struct rio_dbell_ring dbell_ring;
	int bellirq;
};

struct fsl_rio_pw {
	struct rio_mport *mport[MAX_PORT_NUM];
	struct device *dev;
	struct rio_pw_regs __iomem *pw_regs;
	struct rio_port_write_msg port_write_msg;
	int pwirq;
	struct work_struct pw_work;
	struct kfifo pw_fifo;
	spinlock_t pw_fifo_lock;
};

struct rio_priv {
	struct device *dev;
	void __iomem *regs_win;
	struct rio_atmu_regs __iomem *atmu_regs;
	struct rio_atmu_regs __iomem *maint_atmu_regs;
	struct rio_inb_atmu_regs __iomem *inb_atmu_regs;
	void __iomem *maint_win;
	void *rmm_handle; /* RapidIO message manager(unit) Handle */
};

extern void __iomem *rio_regs_win;
extern void __iomem *rmu_regs_win;

extern resource_size_t rio_law_start;

extern struct fsl_rio_dbell *dbell;
extern struct fsl_rio_pw *pw;

extern int fsl_rio_setup_rmu(struct rio_mport *mport,
	struct device_node *node);
extern int fsl_rio_port_write_init(struct fsl_rio_pw *pw);
extern int fsl_rio_pw_enable(struct rio_mport *mport, int enable);
extern void fsl_rio_port_error_handler(int offset);
extern int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell);

extern int fsl_rio_doorbell_send(struct rio_mport *mport,
				int index, u16 destid, u16 data);
extern int fsl_add_outb_message(struct rio_mport *mport,
	struct rio_dev *rdev,
	int mbox, void *buffer, size_t len);
extern int fsl_open_outb_mbox(struct rio_mport *mport,
	void *dev_id, int mbox, int entries);
extern void fsl_close_outb_mbox(struct rio_mport *mport, int mbox);
extern int fsl_open_inb_mbox(struct rio_mport *mport,
	void *dev_id, int mbox, int entries);
extern void fsl_close_inb_mbox(struct rio_mport *mport, int mbox);
extern int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf);
extern void *fsl_get_inb_message(struct rio_mport *mport, int mbox);

#endif
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
6ec4bedb LG	2	/*
	3	* Freescale MPC85xx/MPC86xx RapidIO support
	4	*
	5	* Copyright 2009 Sysgo AG
	6	* Thomas Moll <thomas.moll@sysgo.com>
	7	* - fixed maintenance access routines, check for aligned access
	8	*
	9	* Copyright 2009 Integrated Device Technology, Inc.
	10	* Alex Bounine <alexandre.bounine@idt.com>
	11	* - Added Port-Write message handling
	12	* - Added Machine Check exception handling
	13	*
	14	* Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
	15	* Zhang Wei <wei.zhang@freescale.com>
	16	* Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
	17	* Liu Gang <Gang.Liu@freescale.com>
	18	*
	19	* Copyright 2005 MontaVista Software, Inc.
	20	* Matt Porter <mporter@kernel.crashing.org>
6ec4bedb LG	21	*/
	22
	23	#ifndef __FSL_RIO_H
	24	#define __FSL_RIO_H
	25
	26	#include <linux/rio.h>
	27	#include <linux/rio_drv.h>
	28	#include <linux/kfifo.h>
	29
	30	#define RIO_REGS_WIN(mport) (((struct rio_priv *)(mport->priv))->regs_win)
	31
	32	#define RIO_MAINT_WIN_SIZE 0x400000
	33	#define RIO_LTLEDCSR 0x0608
	34
abc3aeae LG	35	#define DOORBELL_ROWAR_EN 0x80000000
	36	#define DOORBELL_ROWAR_TFLOWLV 0x08000000 /* highest priority level */
	37	#define DOORBELL_ROWAR_PCI 0x02000000 /* PCI window */
	38	#define DOORBELL_ROWAR_NREAD 0x00040000 /* NREAD */
	39	#define DOORBELL_ROWAR_MAINTRD 0x00070000 /* maintenance read */
a0837876	40	#define DOORBELL_ROWAR_RES 0x00002000 /* wrtpy: reserved */
abc3aeae LG	41	#define DOORBELL_ROWAR_MAINTWD 0x00007000
	42	#define DOORBELL_ROWAR_SIZE 0x0000000b /* window size is 4k */
	43
	44	#define RIO_ATMU_REGS_PORT1_OFFSET 0x10c00
	45	#define RIO_ATMU_REGS_PORT2_OFFSET 0x10e00
	46	#define RIO_S_DBELL_REGS_OFFSET 0x13400
	47	#define RIO_S_PW_REGS_OFFSET 0x134e0
	48	#define RIO_ATMU_REGS_DBELL_OFFSET 0x10C40
e6a546fd MG	49	#define RIO_INB_ATMU_REGS_PORT1_OFFSET 0x10d60
e6a546fd MG	50	#define RIO_INB_ATMU_REGS_PORT2_OFFSET 0x10f60
abc3aeae LG	51
	52	#define MAX_MSG_UNIT_NUM 2
	53	#define MAX_PORT_NUM 4
e6a546fd	54	#define RIO_INB_ATMU_COUNT 4
abc3aeae	55
6ec4bedb LG	56	struct rio_atmu_regs {
	57	u32 rowtar;
	58	u32 rowtear;
	59	u32 rowbar;
abc3aeae	60	u32 pad1;
6ec4bedb	61	u32 rowar;
abc3aeae LG	62	u32 pad2[3];
	63	};
	64
e6a546fd MG	65	struct rio_inb_atmu_regs {
	66	u32 riwtar;
	67	u32 pad1;
	68	u32 riwbar;
	69	u32 pad2;
	70	u32 riwar;
	71	u32 pad3[3];
	72	};
	73
abc3aeae LG	74	struct rio_dbell_ring {
	75	void *virt;
	76	dma_addr_t phys;
6ec4bedb LG	77	};
	78
	79	struct rio_port_write_msg {
	80	void *virt;
	81	dma_addr_t phys;
	82	u32 msg_count;
	83	u32 err_count;
	84	u32 discard_count;
	85	};
	86
abc3aeae LG	87	struct fsl_rio_dbell {
abc3aeae LG	88	struct rio_mport *mport[MAX_PORT_NUM];
6ec4bedb	89	struct device *dev;
abc3aeae LG	90	struct rio_dbell_regs __iomem *dbell_regs;
	91	struct rio_dbell_ring dbell_ring;
	92	int bellirq;
	93	};
	94
	95	struct fsl_rio_pw {
9a0b0627	96	struct rio_mport *mport[MAX_PORT_NUM];
abc3aeae LG	97	struct device *dev;
abc3aeae LG	98	struct rio_pw_regs __iomem *pw_regs;
6ec4bedb LG	99	struct rio_port_write_msg port_write_msg;
	100	int pwirq;
	101	struct work_struct pw_work;
	102	struct kfifo pw_fifo;
	103	spinlock_t pw_fifo_lock;
abc3aeae LG	104	};
	105
	106	struct rio_priv {
	107	struct device *dev;
	108	void __iomem *regs_win;
	109	struct rio_atmu_regs __iomem *atmu_regs;
	110	struct rio_atmu_regs __iomem *maint_atmu_regs;
e6a546fd	111	struct rio_inb_atmu_regs __iomem *inb_atmu_regs;
abc3aeae	112	void __iomem *maint_win;
6ec4bedb LG	113	void rmm_handle; / RapidIO message manager(unit) Handle */
	114	};
	115
	116	extern void __iomem *rio_regs_win;
abc3aeae LG	117	extern void __iomem *rmu_regs_win;
	118
	119	extern resource_size_t rio_law_start;
	120
	121	extern struct fsl_rio_dbell *dbell;
	122	extern struct fsl_rio_pw *pw;
6ec4bedb LG	123
	124	extern int fsl_rio_setup_rmu(struct rio_mport *mport,
	125	struct device_node *node);
abc3aeae	126	extern int fsl_rio_port_write_init(struct fsl_rio_pw *pw);
6ec4bedb	127	extern int fsl_rio_pw_enable(struct rio_mport *mport, int enable);
abc3aeae LG	128	extern void fsl_rio_port_error_handler(int offset);
	129	extern int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell);
	130
	131	extern int fsl_rio_doorbell_send(struct rio_mport *mport,
	132	int index, u16 destid, u16 data);
	133	extern int fsl_add_outb_message(struct rio_mport *mport,
	134	struct rio_dev *rdev,
	135	int mbox, void *buffer, size_t len);
	136	extern int fsl_open_outb_mbox(struct rio_mport *mport,
	137	void *dev_id, int mbox, int entries);
	138	extern void fsl_close_outb_mbox(struct rio_mport *mport, int mbox);
	139	extern int fsl_open_inb_mbox(struct rio_mport *mport,
	140	void *dev_id, int mbox, int entries);
	141	extern void fsl_close_inb_mbox(struct rio_mport *mport, int mbox);
	142	extern int fsl_add_inb_buffer(struct rio_mport mport, int mbox, void buf);
	143	extern void fsl_get_inb_message(struct rio_mport mport, int mbox);
6ec4bedb LG	144
6ec4bedb LG	145	#endif