Commit | Line | Data |
---|---|---|
2b0c28d7 | 1 | /* |
d02443a6 | 2 | * Freescale MPC85xx/MPC86xx RapidIO support |
2b0c28d7 | 3 | * |
bd4fb654 TM |
4 | * Copyright 2009 Sysgo AG |
5 | * Thomas Moll <thomas.moll@sysgo.com> | |
6 | * - fixed maintenance access routines, check for aligned access | |
7 | * | |
5b2074ae AB |
8 | * Copyright 2009 Integrated Device Technology, Inc. |
9 | * Alex Bounine <alexandre.bounine@idt.com> | |
10 | * - Added Port-Write message handling | |
11 | * - Added Machine Check exception handling | |
12 | * | |
6ec4bedb | 13 | * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc. |
ad1e9380 ZW |
14 | * Zhang Wei <wei.zhang@freescale.com> |
15 | * | |
2b0c28d7 MP |
16 | * Copyright 2005 MontaVista Software, Inc. |
17 | * Matt Porter <mporter@kernel.crashing.org> | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify it | |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | */ | |
24 | ||
2b0c28d7 | 25 | #include <linux/init.h> |
8a39b05f | 26 | #include <linux/extable.h> |
2b0c28d7 MP |
27 | #include <linux/types.h> |
28 | #include <linux/dma-mapping.h> | |
29 | #include <linux/interrupt.h> | |
0dbbbf1a | 30 | #include <linux/device.h> |
26a2056e RH |
31 | #include <linux/of_address.h> |
32 | #include <linux/of_irq.h> | |
cc2bb696 | 33 | #include <linux/of_platform.h> |
61b26917 | 34 | #include <linux/delay.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
2b0c28d7 | 36 | |
6ec4bedb LG |
37 | #include <linux/io.h> |
38 | #include <linux/uaccess.h> | |
a52c8f52 | 39 | #include <asm/machdep.h> |
2b0c28d7 | 40 | |
6ec4bedb | 41 | #include "fsl_rio.h" |
5b2074ae | 42 | |
6ec4bedb | 43 | #undef DEBUG_PW /* Port-Write debugging */ |
6ff31453 SX |
44 | |
45 | #define RIO_PORT1_EDCSR 0x0640 | |
46 | #define RIO_PORT2_EDCSR 0x0680 | |
47 | #define RIO_PORT1_IECSR 0x10130 | |
48 | #define RIO_PORT2_IECSR 0x101B0 | |
6ff31453 | 49 | |
af84ca38 | 50 | #define RIO_GCCSR 0x13c |
61b26917 | 51 | #define RIO_ESCSR 0x158 |
6ec4bedb | 52 | #define ESCSR_CLEAR 0x07120204 |
6ff31453 | 53 | #define RIO_PORT2_ESCSR 0x178 |
61b26917 | 54 | #define RIO_CCSR 0x15c |
6ff31453 SX |
55 | #define RIO_LTLEDCSR_IER 0x80000000 |
56 | #define RIO_LTLEDCSR_PRT 0x01000000 | |
6ec4bedb | 57 | #define IECSR_CLEAR 0x80000000 |
61b26917 ZW |
58 | #define RIO_ISR_AACR 0x10120 |
59 | #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */ | |
2b0c28d7 | 60 | |
e6a546fd MG |
61 | #define RIWTAR_TRAD_VAL_SHIFT 12 |
62 | #define RIWTAR_TRAD_MASK 0x00FFFFFF | |
63 | #define RIWBAR_BADD_VAL_SHIFT 12 | |
64 | #define RIWBAR_BADD_MASK 0x003FFFFF | |
65 | #define RIWAR_ENABLE 0x80000000 | |
66 | #define RIWAR_TGINT_LOCAL 0x00F00000 | |
67 | #define RIWAR_RDTYP_NO_SNOOP 0x00040000 | |
68 | #define RIWAR_RDTYP_SNOOP 0x00050000 | |
69 | #define RIWAR_WRTYP_NO_SNOOP 0x00004000 | |
70 | #define RIWAR_WRTYP_SNOOP 0x00005000 | |
71 | #define RIWAR_WRTYP_ALLOC 0x00006000 | |
72 | #define RIWAR_SIZE_MASK 0x0000003F | |
73 | ||
31d1e130 IN |
74 | static DEFINE_SPINLOCK(fsl_rio_config_lock); |
75 | ||
a52c8f52 AB |
76 | #define __fsl_read_rio_config(x, addr, err, op) \ |
77 | __asm__ __volatile__( \ | |
78 | "1: "op" %1,0(%2)\n" \ | |
79 | " eieio\n" \ | |
80 | "2:\n" \ | |
81 | ".section .fixup,\"ax\"\n" \ | |
82 | "3: li %1,-1\n" \ | |
83 | " li %0,%3\n" \ | |
84 | " b 2b\n" \ | |
24bfa6a9 NP |
85 | ".previous\n" \ |
86 | EX_TABLE(1b, 3b) \ | |
a52c8f52 AB |
87 | : "=r" (err), "=r" (x) \ |
88 | : "b" (addr), "i" (-EFAULT), "0" (err)) | |
89 | ||
6ec4bedb | 90 | void __iomem *rio_regs_win; |
abc3aeae LG |
91 | void __iomem *rmu_regs_win; |
92 | resource_size_t rio_law_start; | |
93 | ||
94 | struct fsl_rio_dbell *dbell; | |
95 | struct fsl_rio_pw *pw; | |
a52c8f52 | 96 | |
ff33f182 | 97 | #ifdef CONFIG_E500 |
cce1f106 | 98 | int fsl_rio_mcheck_exception(struct pt_regs *regs) |
a52c8f52 | 99 | { |
82a9a480 SW |
100 | const struct exception_table_entry *entry; |
101 | unsigned long reason; | |
a52c8f52 | 102 | |
82a9a480 SW |
103 | if (!rio_regs_win) |
104 | return 0; | |
105 | ||
106 | reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR)); | |
107 | if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) { | |
108 | /* Check if we are prepared to handle this fault */ | |
109 | entry = search_exception_tables(regs->nip); | |
110 | if (entry) { | |
111 | pr_debug("RIO: %s - MC Exception handled\n", | |
112 | __func__); | |
113 | out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), | |
114 | 0); | |
115 | regs->msr |= MSR_RI; | |
61a92f70 | 116 | regs->nip = extable_fixup(entry); |
82a9a480 | 117 | return 1; |
a52c8f52 AB |
118 | } |
119 | } | |
120 | ||
cce1f106 | 121 | return 0; |
a52c8f52 | 122 | } |
cce1f106 | 123 | EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception); |
ff33f182 | 124 | #endif |
a52c8f52 | 125 | |
2b0c28d7 | 126 | /** |
d02443a6 | 127 | * fsl_local_config_read - Generate a MPC85xx local config space read |
9941d945 | 128 | * @mport: RapidIO master port info |
2b0c28d7 MP |
129 | * @index: ID of RapdiIO interface |
130 | * @offset: Offset into configuration space | |
131 | * @len: Length (in bytes) of the maintenance transaction | |
132 | * @data: Value to be read into | |
133 | * | |
134 | * Generates a MPC85xx local configuration space read. Returns %0 on | |
135 | * success or %-EINVAL on failure. | |
136 | */ | |
ad1e9380 ZW |
137 | static int fsl_local_config_read(struct rio_mport *mport, |
138 | int index, u32 offset, int len, u32 *data) | |
2b0c28d7 | 139 | { |
ad1e9380 | 140 | struct rio_priv *priv = mport->priv; |
d02443a6 | 141 | pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index, |
abc3aeae | 142 | offset); |
ad1e9380 | 143 | *data = in_be32(priv->regs_win + offset); |
2b0c28d7 MP |
144 | |
145 | return 0; | |
146 | } | |
147 | ||
148 | /** | |
d02443a6 | 149 | * fsl_local_config_write - Generate a MPC85xx local config space write |
9941d945 | 150 | * @mport: RapidIO master port info |
2b0c28d7 MP |
151 | * @index: ID of RapdiIO interface |
152 | * @offset: Offset into configuration space | |
153 | * @len: Length (in bytes) of the maintenance transaction | |
154 | * @data: Value to be written | |
155 | * | |
156 | * Generates a MPC85xx local configuration space write. Returns %0 on | |
157 | * success or %-EINVAL on failure. | |
158 | */ | |
ad1e9380 ZW |
159 | static int fsl_local_config_write(struct rio_mport *mport, |
160 | int index, u32 offset, int len, u32 data) | |
2b0c28d7 | 161 | { |
ad1e9380 | 162 | struct rio_priv *priv = mport->priv; |
2b0c28d7 | 163 | pr_debug |
6ec4bedb LG |
164 | ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n", |
165 | index, offset, data); | |
ad1e9380 | 166 | out_be32(priv->regs_win + offset, data); |
2b0c28d7 MP |
167 | |
168 | return 0; | |
169 | } | |
170 | ||
171 | /** | |
d02443a6 | 172 | * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction |
9941d945 | 173 | * @mport: RapidIO master port info |
2b0c28d7 MP |
174 | * @index: ID of RapdiIO interface |
175 | * @destid: Destination ID of transaction | |
176 | * @hopcount: Number of hops to target device | |
177 | * @offset: Offset into configuration space | |
178 | * @len: Length (in bytes) of the maintenance transaction | |
179 | * @val: Location to be read into | |
180 | * | |
181 | * Generates a MPC85xx read maintenance transaction. Returns %0 on | |
182 | * success or %-EINVAL on failure. | |
183 | */ | |
184 | static int | |
ad1e9380 ZW |
185 | fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid, |
186 | u8 hopcount, u32 offset, int len, u32 *val) | |
2b0c28d7 | 187 | { |
ad1e9380 | 188 | struct rio_priv *priv = mport->priv; |
31d1e130 | 189 | unsigned long flags; |
2b0c28d7 | 190 | u8 *data; |
a52c8f52 | 191 | u32 rval, err = 0; |
2b0c28d7 MP |
192 | |
193 | pr_debug | |
6ec4bedb LG |
194 | ("fsl_rio_config_read:" |
195 | " index %d destid %d hopcount %d offset %8.8x len %d\n", | |
abc3aeae | 196 | index, destid, hopcount, offset, len); |
bd4fb654 TM |
197 | |
198 | /* 16MB maintenance window possible */ | |
199 | /* allow only aligned access to maintenance registers */ | |
200 | if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) | |
201 | return -EINVAL; | |
202 | ||
31d1e130 IN |
203 | spin_lock_irqsave(&fsl_rio_config_lock, flags); |
204 | ||
ad1e9380 | 205 | out_be32(&priv->maint_atmu_regs->rowtar, |
bd4fb654 | 206 | (destid << 22) | (hopcount << 12) | (offset >> 12)); |
6ec4bedb | 207 | out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); |
2b0c28d7 | 208 | |
bd4fb654 | 209 | data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); |
2b0c28d7 MP |
210 | switch (len) { |
211 | case 1: | |
a52c8f52 | 212 | __fsl_read_rio_config(rval, data, err, "lbz"); |
2b0c28d7 MP |
213 | break; |
214 | case 2: | |
a52c8f52 | 215 | __fsl_read_rio_config(rval, data, err, "lhz"); |
2b0c28d7 | 216 | break; |
bd4fb654 | 217 | case 4: |
a52c8f52 | 218 | __fsl_read_rio_config(rval, data, err, "lwz"); |
2b0c28d7 | 219 | break; |
bd4fb654 | 220 | default: |
31d1e130 | 221 | spin_unlock_irqrestore(&fsl_rio_config_lock, flags); |
bd4fb654 | 222 | return -EINVAL; |
2b0c28d7 MP |
223 | } |
224 | ||
a52c8f52 AB |
225 | if (err) { |
226 | pr_debug("RIO: cfg_read error %d for %x:%x:%x\n", | |
227 | err, destid, hopcount, offset); | |
228 | } | |
229 | ||
31d1e130 | 230 | spin_unlock_irqrestore(&fsl_rio_config_lock, flags); |
a52c8f52 AB |
231 | *val = rval; |
232 | ||
233 | return err; | |
2b0c28d7 MP |
234 | } |
235 | ||
236 | /** | |
d02443a6 | 237 | * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction |
9941d945 | 238 | * @mport: RapidIO master port info |
2b0c28d7 MP |
239 | * @index: ID of RapdiIO interface |
240 | * @destid: Destination ID of transaction | |
241 | * @hopcount: Number of hops to target device | |
242 | * @offset: Offset into configuration space | |
243 | * @len: Length (in bytes) of the maintenance transaction | |
244 | * @val: Value to be written | |
245 | * | |
246 | * Generates an MPC85xx write maintenance transaction. Returns %0 on | |
247 | * success or %-EINVAL on failure. | |
248 | */ | |
249 | static int | |
ad1e9380 ZW |
250 | fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid, |
251 | u8 hopcount, u32 offset, int len, u32 val) | |
2b0c28d7 | 252 | { |
ad1e9380 | 253 | struct rio_priv *priv = mport->priv; |
31d1e130 | 254 | unsigned long flags; |
2b0c28d7 | 255 | u8 *data; |
31d1e130 IN |
256 | int ret = 0; |
257 | ||
2b0c28d7 | 258 | pr_debug |
6ec4bedb | 259 | ("fsl_rio_config_write:" |
abc3aeae LG |
260 | " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", |
261 | index, destid, hopcount, offset, len, val); | |
bd4fb654 TM |
262 | |
263 | /* 16MB maintenance windows possible */ | |
264 | /* allow only aligned access to maintenance registers */ | |
265 | if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len)) | |
266 | return -EINVAL; | |
267 | ||
31d1e130 IN |
268 | spin_lock_irqsave(&fsl_rio_config_lock, flags); |
269 | ||
ad1e9380 | 270 | out_be32(&priv->maint_atmu_regs->rowtar, |
bd4fb654 | 271 | (destid << 22) | (hopcount << 12) | (offset >> 12)); |
6ec4bedb | 272 | out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10)); |
2b0c28d7 | 273 | |
bd4fb654 | 274 | data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1)); |
2b0c28d7 MP |
275 | switch (len) { |
276 | case 1: | |
277 | out_8((u8 *) data, val); | |
278 | break; | |
279 | case 2: | |
280 | out_be16((u16 *) data, val); | |
281 | break; | |
bd4fb654 | 282 | case 4: |
2b0c28d7 MP |
283 | out_be32((u32 *) data, val); |
284 | break; | |
bd4fb654 | 285 | default: |
31d1e130 | 286 | ret = -EINVAL; |
2b0c28d7 | 287 | } |
31d1e130 | 288 | spin_unlock_irqrestore(&fsl_rio_config_lock, flags); |
2b0c28d7 | 289 | |
31d1e130 | 290 | return ret; |
2b0c28d7 MP |
291 | } |
292 | ||
e6a546fd MG |
293 | static void fsl_rio_inbound_mem_init(struct rio_priv *priv) |
294 | { | |
295 | int i; | |
296 | ||
297 | /* close inbound windows */ | |
298 | for (i = 0; i < RIO_INB_ATMU_COUNT; i++) | |
299 | out_be32(&priv->inb_atmu_regs[i].riwar, 0); | |
300 | } | |
301 | ||
302 | int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart, | |
a057a52e | 303 | u64 rstart, u64 size, u32 flags) |
e6a546fd MG |
304 | { |
305 | struct rio_priv *priv = mport->priv; | |
306 | u32 base_size; | |
307 | unsigned int base_size_log; | |
308 | u64 win_start, win_end; | |
309 | u32 riwar; | |
310 | int i; | |
311 | ||
a057a52e | 312 | if ((size & (size - 1)) != 0 || size > 0x400000000ULL) |
e6a546fd MG |
313 | return -EINVAL; |
314 | ||
315 | base_size_log = ilog2(size); | |
316 | base_size = 1 << base_size_log; | |
317 | ||
318 | /* check if addresses are aligned with the window size */ | |
319 | if (lstart & (base_size - 1)) | |
320 | return -EINVAL; | |
321 | if (rstart & (base_size - 1)) | |
322 | return -EINVAL; | |
323 | ||
324 | /* check for conflicting ranges */ | |
325 | for (i = 0; i < RIO_INB_ATMU_COUNT; i++) { | |
326 | riwar = in_be32(&priv->inb_atmu_regs[i].riwar); | |
327 | if ((riwar & RIWAR_ENABLE) == 0) | |
328 | continue; | |
329 | win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK)) | |
330 | << RIWBAR_BADD_VAL_SHIFT; | |
331 | win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1); | |
332 | if (rstart < win_end && (rstart + size) > win_start) | |
333 | return -EINVAL; | |
334 | } | |
335 | ||
336 | /* find unused atmu */ | |
337 | for (i = 0; i < RIO_INB_ATMU_COUNT; i++) { | |
338 | riwar = in_be32(&priv->inb_atmu_regs[i].riwar); | |
339 | if ((riwar & RIWAR_ENABLE) == 0) | |
340 | break; | |
341 | } | |
342 | if (i >= RIO_INB_ATMU_COUNT) | |
343 | return -ENOMEM; | |
344 | ||
345 | out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT); | |
346 | out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT); | |
347 | out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL | | |
348 | RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1)); | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart) | |
354 | { | |
355 | u32 win_start_shift, base_start_shift; | |
356 | struct rio_priv *priv = mport->priv; | |
357 | u32 riwar, riwtar; | |
358 | int i; | |
359 | ||
360 | /* skip default window */ | |
361 | base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT; | |
362 | for (i = 0; i < RIO_INB_ATMU_COUNT; i++) { | |
363 | riwar = in_be32(&priv->inb_atmu_regs[i].riwar); | |
364 | if ((riwar & RIWAR_ENABLE) == 0) | |
365 | continue; | |
366 | ||
367 | riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar); | |
368 | win_start_shift = riwtar & RIWTAR_TRAD_MASK; | |
369 | if (win_start_shift == base_start_shift) { | |
370 | out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE); | |
371 | return; | |
372 | } | |
373 | } | |
374 | } | |
375 | ||
abc3aeae | 376 | void fsl_rio_port_error_handler(int offset) |
6ff31453 SX |
377 | { |
378 | /*XXX: Error recovery is not implemented, we just clear errors */ | |
379 | out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); | |
380 | ||
381 | if (offset == 0) { | |
382 | out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0); | |
671ee7f0 | 383 | out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR); |
6ff31453 SX |
384 | out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR); |
385 | } else { | |
386 | out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0); | |
671ee7f0 | 387 | out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR); |
6ff31453 SX |
388 | out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR); |
389 | } | |
390 | } | |
7f620df8 ZW |
391 | static inline void fsl_rio_info(struct device *dev, u32 ccsr) |
392 | { | |
393 | const char *str; | |
394 | if (ccsr & 1) { | |
395 | /* Serial phy */ | |
396 | switch (ccsr >> 30) { | |
397 | case 0: | |
398 | str = "1"; | |
399 | break; | |
400 | case 1: | |
401 | str = "4"; | |
402 | break; | |
403 | default: | |
404 | str = "Unknown"; | |
d258e64e | 405 | break; |
7f620df8 ZW |
406 | } |
407 | dev_info(dev, "Hardware port width: %s\n", str); | |
408 | ||
409 | switch ((ccsr >> 27) & 7) { | |
410 | case 0: | |
411 | str = "Single-lane 0"; | |
412 | break; | |
413 | case 1: | |
414 | str = "Single-lane 2"; | |
415 | break; | |
416 | case 2: | |
417 | str = "Four-lane"; | |
418 | break; | |
419 | default: | |
420 | str = "Unknown"; | |
421 | break; | |
422 | } | |
423 | dev_info(dev, "Training connection status: %s\n", str); | |
424 | } else { | |
425 | /* Parallel phy */ | |
426 | if (!(ccsr & 0x80000000)) | |
427 | dev_info(dev, "Output port operating in 8-bit mode\n"); | |
428 | if (!(ccsr & 0x08000000)) | |
429 | dev_info(dev, "Input port operating in 8-bit mode\n"); | |
430 | } | |
431 | } | |
432 | ||
2b0c28d7 | 433 | /** |
9941d945 | 434 | * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface |
2dc11581 | 435 | * @dev: platform_device pointer |
2b0c28d7 MP |
436 | * |
437 | * Initializes MPC85xx RapidIO hardware interface, configures | |
438 | * master port with system-specific info, and registers the | |
439 | * master port with the RapidIO subsystem. | |
440 | */ | |
a454dc50 | 441 | int fsl_rio_setup(struct platform_device *dev) |
2b0c28d7 MP |
442 | { |
443 | struct rio_ops *ops; | |
444 | struct rio_mport *port; | |
cc2bb696 ZW |
445 | struct rio_priv *priv; |
446 | int rc = 0; | |
abc3aeae LG |
447 | const u32 *dt_range, *cell, *port_index; |
448 | u32 active_ports = 0; | |
449 | struct resource regs, rmu_regs; | |
450 | struct device_node *np, *rmu_node; | |
cc2bb696 | 451 | int rlen; |
61b26917 | 452 | u32 ccsr; |
abc3aeae | 453 | u64 range_start, range_size; |
cc2bb696 | 454 | int paw, aw, sw; |
abc3aeae LG |
455 | u32 i; |
456 | static int tmp; | |
457 | struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL}; | |
cc2bb696 | 458 | |
61c7a080 | 459 | if (!dev->dev.of_node) { |
cc2bb696 | 460 | dev_err(&dev->dev, "Device OF-Node is NULL"); |
abc3aeae | 461 | return -ENODEV; |
cc2bb696 ZW |
462 | } |
463 | ||
61c7a080 | 464 | rc = of_address_to_resource(dev->dev.of_node, 0, ®s); |
cc2bb696 | 465 | if (rc) { |
b7c670d6 RH |
466 | dev_err(&dev->dev, "Can't get %pOF property 'reg'\n", |
467 | dev->dev.of_node); | |
cc2bb696 ZW |
468 | return -EFAULT; |
469 | } | |
b7c670d6 RH |
470 | dev_info(&dev->dev, "Of-device full name %pOF\n", |
471 | dev->dev.of_node); | |
fc274a15 | 472 | dev_info(&dev->dev, "Regs: %pR\n", ®s); |
cc2bb696 | 473 | |
abc3aeae LG |
474 | rio_regs_win = ioremap(regs.start, resource_size(®s)); |
475 | if (!rio_regs_win) { | |
476 | dev_err(&dev->dev, "Unable to map rio register window\n"); | |
477 | rc = -ENOMEM; | |
478 | goto err_rio_regs; | |
cc2bb696 ZW |
479 | } |
480 | ||
e5cabeb3 | 481 | ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL); |
6c75933c JL |
482 | if (!ops) { |
483 | rc = -ENOMEM; | |
484 | goto err_ops; | |
485 | } | |
d02443a6 ZW |
486 | ops->lcread = fsl_local_config_read; |
487 | ops->lcwrite = fsl_local_config_write; | |
488 | ops->cread = fsl_rio_config_read; | |
489 | ops->cwrite = fsl_rio_config_write; | |
abc3aeae | 490 | ops->dsend = fsl_rio_doorbell_send; |
5b2074ae | 491 | ops->pwenable = fsl_rio_pw_enable; |
abc3aeae LG |
492 | ops->open_outb_mbox = fsl_open_outb_mbox; |
493 | ops->open_inb_mbox = fsl_open_inb_mbox; | |
494 | ops->close_outb_mbox = fsl_close_outb_mbox; | |
495 | ops->close_inb_mbox = fsl_close_inb_mbox; | |
496 | ops->add_outb_message = fsl_add_outb_message; | |
497 | ops->add_inb_buffer = fsl_add_inb_buffer; | |
498 | ops->get_inb_message = fsl_get_inb_message; | |
e6a546fd MG |
499 | ops->map_inb = fsl_map_inb_mem; |
500 | ops->unmap_inb = fsl_unmap_inb_mem; | |
abc3aeae LG |
501 | |
502 | rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0); | |
a614db9a SW |
503 | if (!rmu_node) { |
504 | dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n"); | |
380afa36 | 505 | rc = -ENOENT; |
abc3aeae | 506 | goto err_rmu; |
a614db9a | 507 | } |
abc3aeae LG |
508 | rc = of_address_to_resource(rmu_node, 0, &rmu_regs); |
509 | if (rc) { | |
b7c670d6 RH |
510 | dev_err(&dev->dev, "Can't get %pOF property 'reg'\n", |
511 | rmu_node); | |
abc3aeae LG |
512 | goto err_rmu; |
513 | } | |
514 | rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs)); | |
515 | if (!rmu_regs_win) { | |
516 | dev_err(&dev->dev, "Unable to map rmu register window\n"); | |
6c75933c | 517 | rc = -ENOMEM; |
abc3aeae LG |
518 | goto err_rmu; |
519 | } | |
520 | for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") { | |
521 | rmu_np[tmp] = np; | |
522 | tmp++; | |
6c75933c | 523 | } |
ad1e9380 | 524 | |
abc3aeae LG |
525 | /*set up doobell node*/ |
526 | np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit"); | |
527 | if (!np) { | |
a614db9a | 528 | dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n"); |
abc3aeae LG |
529 | rc = -ENODEV; |
530 | goto err_dbell; | |
531 | } | |
532 | dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL); | |
533 | if (!(dbell)) { | |
534 | dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n"); | |
ad1e9380 | 535 | rc = -ENOMEM; |
abc3aeae | 536 | goto err_dbell; |
ad1e9380 | 537 | } |
abc3aeae LG |
538 | dbell->dev = &dev->dev; |
539 | dbell->bellirq = irq_of_parse_and_map(np, 1); | |
540 | dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq); | |
ad1e9380 | 541 | |
abc3aeae LG |
542 | aw = of_n_addr_cells(np); |
543 | dt_range = of_get_property(np, "reg", &rlen); | |
544 | if (!dt_range) { | |
b7c670d6 RH |
545 | pr_err("%pOF: unable to find 'reg' property\n", |
546 | np); | |
abc3aeae LG |
547 | rc = -ENOMEM; |
548 | goto err_pw; | |
549 | } | |
550 | range_start = of_read_number(dt_range, aw); | |
551 | dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win + | |
552 | (u32)range_start); | |
553 | ||
554 | /*set up port write node*/ | |
555 | np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit"); | |
556 | if (!np) { | |
a614db9a | 557 | dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n"); |
abc3aeae LG |
558 | rc = -ENODEV; |
559 | goto err_pw; | |
560 | } | |
561 | pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL); | |
562 | if (!(pw)) { | |
563 | dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n"); | |
564 | rc = -ENOMEM; | |
565 | goto err_pw; | |
566 | } | |
567 | pw->dev = &dev->dev; | |
568 | pw->pwirq = irq_of_parse_and_map(np, 0); | |
569 | dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq); | |
570 | aw = of_n_addr_cells(np); | |
571 | dt_range = of_get_property(np, "reg", &rlen); | |
572 | if (!dt_range) { | |
b7c670d6 RH |
573 | pr_err("%pOF: unable to find 'reg' property\n", |
574 | np); | |
abc3aeae LG |
575 | rc = -ENOMEM; |
576 | goto err; | |
c1256ebe | 577 | } |
abc3aeae LG |
578 | range_start = of_read_number(dt_range, aw); |
579 | pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start); | |
580 | ||
581 | /*set up ports node*/ | |
582 | for_each_child_of_node(dev->dev.of_node, np) { | |
583 | port_index = of_get_property(np, "cell-index", NULL); | |
584 | if (!port_index) { | |
b7c670d6 RH |
585 | dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n", |
586 | np); | |
abc3aeae LG |
587 | continue; |
588 | } | |
589 | ||
590 | dt_range = of_get_property(np, "ranges", &rlen); | |
591 | if (!dt_range) { | |
b7c670d6 RH |
592 | dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n", |
593 | np); | |
abc3aeae LG |
594 | continue; |
595 | } | |
c1256ebe | 596 | |
abc3aeae LG |
597 | /* Get node address wide */ |
598 | cell = of_get_property(np, "#address-cells", NULL); | |
599 | if (cell) | |
600 | aw = *cell; | |
601 | else | |
602 | aw = of_n_addr_cells(np); | |
603 | /* Get node size wide */ | |
604 | cell = of_get_property(np, "#size-cells", NULL); | |
605 | if (cell) | |
606 | sw = *cell; | |
607 | else | |
608 | sw = of_n_size_cells(np); | |
609 | /* Get parent address wide wide */ | |
610 | paw = of_n_addr_cells(np); | |
611 | range_start = of_read_number(dt_range + aw, paw); | |
612 | range_size = of_read_number(dt_range + aw + paw, sw); | |
613 | ||
b7c670d6 RH |
614 | dev_info(&dev->dev, "%pOF: LAW start 0x%016llx, size 0x%016llx.\n", |
615 | np, range_start, range_size); | |
abc3aeae LG |
616 | |
617 | port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL); | |
618 | if (!port) | |
619 | continue; | |
620 | ||
dd64f4fe AB |
621 | rc = rio_mport_initialize(port); |
622 | if (rc) { | |
623 | kfree(port); | |
624 | continue; | |
625 | } | |
626 | ||
abc3aeae LG |
627 | i = *port_index - 1; |
628 | port->index = (unsigned char)i; | |
629 | ||
630 | priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL); | |
631 | if (!priv) { | |
632 | dev_err(&dev->dev, "Can't alloc memory for 'priv'\n"); | |
633 | kfree(port); | |
634 | continue; | |
635 | } | |
636 | ||
637 | INIT_LIST_HEAD(&port->dbells); | |
638 | port->iores.start = range_start; | |
639 | port->iores.end = port->iores.start + range_size - 1; | |
640 | port->iores.flags = IORESOURCE_MEM; | |
641 | port->iores.name = "rio_io_win"; | |
642 | ||
643 | if (request_resource(&iomem_resource, &port->iores) < 0) { | |
644 | dev_err(&dev->dev, "RIO: Error requesting master port region" | |
645 | " 0x%016llx-0x%016llx\n", | |
646 | (u64)port->iores.start, (u64)port->iores.end); | |
647 | kfree(priv); | |
648 | kfree(port); | |
649 | continue; | |
650 | } | |
651 | sprintf(port->name, "RIO mport %d", i); | |
652 | ||
653 | priv->dev = &dev->dev; | |
2aaf308b | 654 | port->dev.parent = &dev->dev; |
abc3aeae LG |
655 | port->ops = ops; |
656 | port->priv = priv; | |
657 | port->phys_efptr = 0x100; | |
adff1649 | 658 | port->phys_rmap = 1; |
abc3aeae LG |
659 | priv->regs_win = rio_regs_win; |
660 | ||
abc3aeae | 661 | ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20); |
adff1649 | 662 | |
abc3aeae LG |
663 | /* Checking the port training status */ |
664 | if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) { | |
665 | dev_err(&dev->dev, "Port %d is not ready. " | |
666 | "Try to restart connection...\n", i); | |
7f620df8 | 667 | /* Disable ports */ |
abc3aeae LG |
668 | out_be32(priv->regs_win |
669 | + RIO_CCSR + i*0x20, 0); | |
7f620df8 | 670 | /* Set 1x lane */ |
abc3aeae LG |
671 | setbits32(priv->regs_win |
672 | + RIO_CCSR + i*0x20, 0x02000000); | |
7f620df8 | 673 | /* Enable ports */ |
abc3aeae LG |
674 | setbits32(priv->regs_win |
675 | + RIO_CCSR + i*0x20, 0x00600000); | |
676 | msleep(100); | |
677 | if (in_be32((priv->regs_win | |
678 | + RIO_ESCSR + i*0x20)) & 1) { | |
679 | dev_err(&dev->dev, | |
680 | "Port %d restart failed.\n", i); | |
681 | release_resource(&port->iores); | |
682 | kfree(priv); | |
683 | kfree(port); | |
684 | continue; | |
685 | } | |
686 | dev_info(&dev->dev, "Port %d restart success!\n", i); | |
7f620df8 | 687 | } |
abc3aeae | 688 | fsl_rio_info(&dev->dev, ccsr); |
61b26917 | 689 | |
abc3aeae | 690 | port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR)) |
e0423236 | 691 | & RIO_PEF_CTLS) >> 4; |
abc3aeae LG |
692 | dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n", |
693 | port->sys_size ? 65536 : 256); | |
694 | ||
abc3aeae LG |
695 | if (port->host_deviceid >= 0) |
696 | out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST | | |
697 | RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED); | |
698 | else | |
699 | out_be32(priv->regs_win + RIO_GCCSR, | |
700 | RIO_PORT_GEN_MASTER); | |
e0423236 | 701 | |
abc3aeae LG |
702 | priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win |
703 | + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET : | |
704 | RIO_ATMU_REGS_PORT2_OFFSET)); | |
705 | ||
706 | priv->maint_atmu_regs = priv->atmu_regs + 1; | |
e6a546fd MG |
707 | priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *) |
708 | (priv->regs_win + | |
709 | ((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET : | |
710 | RIO_INB_ATMU_REGS_PORT2_OFFSET)); | |
711 | ||
adff1649 AB |
712 | /* Set to receive packets with any dest ID */ |
713 | out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80), | |
714 | RIO_ISR_AACR_AA); | |
af84ca38 | 715 | |
abc3aeae LG |
716 | /* Configure maintenance transaction window */ |
717 | out_be32(&priv->maint_atmu_regs->rowbar, | |
718 | port->iores.start >> 12); | |
719 | out_be32(&priv->maint_atmu_regs->rowar, | |
720 | 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1)); | |
61b26917 | 721 | |
abc3aeae LG |
722 | priv->maint_win = ioremap(port->iores.start, |
723 | RIO_MAINT_WIN_SIZE); | |
2b0c28d7 | 724 | |
abc3aeae | 725 | rio_law_start = range_start; |
2b0c28d7 | 726 | |
abc3aeae | 727 | fsl_rio_setup_rmu(port, rmu_np[i]); |
e6a546fd | 728 | fsl_rio_inbound_mem_init(priv); |
2b0c28d7 | 729 | |
abc3aeae | 730 | dbell->mport[i] = port; |
9a0b0627 | 731 | pw->mport[i] = port; |
abc3aeae | 732 | |
dd64f4fe AB |
733 | if (rio_register_mport(port)) { |
734 | release_resource(&port->iores); | |
735 | kfree(priv); | |
736 | kfree(port); | |
737 | continue; | |
738 | } | |
abc3aeae LG |
739 | active_ports++; |
740 | } | |
741 | ||
742 | if (!active_ports) { | |
743 | rc = -ENOLINK; | |
744 | goto err; | |
745 | } | |
6ec4bedb | 746 | |
abc3aeae LG |
747 | fsl_rio_doorbell_init(dbell); |
748 | fsl_rio_port_write_init(pw); | |
ad1e9380 | 749 | |
cc2bb696 | 750 | return 0; |
ad1e9380 | 751 | err: |
abc3aeae | 752 | kfree(pw); |
a614db9a | 753 | pw = NULL; |
abc3aeae LG |
754 | err_pw: |
755 | kfree(dbell); | |
a614db9a | 756 | dbell = NULL; |
abc3aeae LG |
757 | err_dbell: |
758 | iounmap(rmu_regs_win); | |
a614db9a | 759 | rmu_regs_win = NULL; |
abc3aeae | 760 | err_rmu: |
6c75933c JL |
761 | kfree(ops); |
762 | err_ops: | |
abc3aeae | 763 | iounmap(rio_regs_win); |
a614db9a | 764 | rio_regs_win = NULL; |
abc3aeae | 765 | err_rio_regs: |
cc2bb696 | 766 | return rc; |
2b0c28d7 | 767 | } |
cc2bb696 ZW |
768 | |
769 | /* The probe function for RapidIO peer-to-peer network. | |
770 | */ | |
cad5cef6 | 771 | static int fsl_of_rio_rpn_probe(struct platform_device *dev) |
cc2bb696 | 772 | { |
b7c670d6 RH |
773 | printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n", |
774 | dev->dev.of_node); | |
cc2bb696 | 775 | |
2f809985 | 776 | return fsl_rio_setup(dev); |
cc2bb696 ZW |
777 | }; |
778 | ||
779 | static const struct of_device_id fsl_of_rio_rpn_ids[] = { | |
780 | { | |
abc3aeae | 781 | .compatible = "fsl,srio", |
cc2bb696 ZW |
782 | }, |
783 | {}, | |
784 | }; | |
785 | ||
00006124 | 786 | static struct platform_driver fsl_of_rio_rpn_driver = { |
4018294b GL |
787 | .driver = { |
788 | .name = "fsl-of-rio", | |
4018294b GL |
789 | .of_match_table = fsl_of_rio_rpn_ids, |
790 | }, | |
cc2bb696 ZW |
791 | .probe = fsl_of_rio_rpn_probe, |
792 | }; | |
793 | ||
794 | static __init int fsl_of_rio_rpn_init(void) | |
795 | { | |
00006124 | 796 | return platform_driver_register(&fsl_of_rio_rpn_driver); |
cc2bb696 ZW |
797 | } |
798 | ||
799 | subsys_initcall(fsl_of_rio_rpn_init); |