Commit | Line | Data |
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b809b3e8 | 1 | /* |
9ac4dd30 | 2 | * MPC85xx/86xx PCI/PCIE support routing. |
b809b3e8 | 3 | * |
9ac4dd30 | 4 | * Copyright 2007 Freescale Semiconductor, Inc |
b809b3e8 | 5 | * |
9ac4dd30 ZR |
6 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> |
7 | * Recode: ZHANG WEI <wei.zhang@freescale.com> | |
8 | * Rewrite the routing for Frescale PCI and PCI Express | |
9 | * Roy Zang <tie-fei.zang@freescale.com> | |
b809b3e8 JL |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | */ | |
9ac4dd30 | 16 | #include <linux/kernel.h> |
b809b3e8 | 17 | #include <linux/pci.h> |
9ac4dd30 ZR |
18 | #include <linux/delay.h> |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/bootmem.h> | |
b809b3e8 | 22 | |
b809b3e8 JL |
23 | #include <asm/io.h> |
24 | #include <asm/prom.h> | |
b809b3e8 | 25 | #include <asm/pci-bridge.h> |
9ac4dd30 | 26 | #include <asm/machdep.h> |
b809b3e8 | 27 | #include <sysdev/fsl_soc.h> |
55c44991 | 28 | #include <sysdev/fsl_pci.h> |
b809b3e8 | 29 | |
9ac4dd30 ZR |
30 | /* atmu setup for fsl pci/pcie controller */ |
31 | void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc) | |
b809b3e8 | 32 | { |
9ac4dd30 ZR |
33 | struct ccsr_pci __iomem *pci; |
34 | int i; | |
b809b3e8 | 35 | |
9ac4dd30 | 36 | pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start, |
b809b3e8 | 37 | rsrc->end - rsrc->start + 1); |
9ac4dd30 ZR |
38 | pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); |
39 | ||
40 | /* Disable all windows (except powar0 since its ignored) */ | |
41 | for(i = 1; i < 5; i++) | |
42 | out_be32(&pci->pow[i].powar, 0); | |
43 | for(i = 0; i < 3; i++) | |
44 | out_be32(&pci->piw[i].piwar, 0); | |
45 | ||
46 | /* Setup outbound MEM window */ | |
47 | for(i = 0; i < 3; i++) | |
48 | if (hose->mem_resources[i].flags & IORESOURCE_MEM){ | |
49 | pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n", | |
50 | hose->mem_resources[i].start, | |
51 | hose->mem_resources[i].end | |
52 | - hose->mem_resources[i].start + 1); | |
53 | out_be32(&pci->pow[i+1].potar, | |
54 | (hose->mem_resources[i].start >> 12) | |
55 | & 0x000fffff); | |
56 | out_be32(&pci->pow[i+1].potear, 0); | |
57 | out_be32(&pci->pow[i+1].powbar, | |
58 | (hose->mem_resources[i].start >> 12) | |
59 | & 0x000fffff); | |
60 | /* Enable, Mem R/W */ | |
61 | out_be32(&pci->pow[i+1].powar, 0x80044000 | |
62 | | (__ilog2(hose->mem_resources[i].end | |
63 | - hose->mem_resources[i].start + 1) - 1)); | |
64 | } | |
65 | ||
66 | /* Setup outbound IO window */ | |
67 | if (hose->io_resource.flags & IORESOURCE_IO){ | |
68 | pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", | |
69 | hose->io_resource.start, | |
70 | hose->io_resource.end - hose->io_resource.start + 1, | |
71 | hose->io_base_phys); | |
72 | out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12) | |
73 | & 0x000fffff); | |
74 | out_be32(&pci->pow[i+1].potear, 0); | |
75 | out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12) | |
76 | & 0x000fffff); | |
77 | /* Enable, IO R/W */ | |
78 | out_be32(&pci->pow[i+1].powar, 0x80088000 | |
79 | | (__ilog2(hose->io_resource.end | |
80 | - hose->io_resource.start + 1) - 1)); | |
81 | } | |
82 | ||
83 | /* Setup 2G inbound Memory Window @ 1 */ | |
84 | out_be32(&pci->piw[2].pitar, 0x00000000); | |
85 | out_be32(&pci->piw[2].piwbar,0x00000000); | |
86 | out_be32(&pci->piw[2].piwar, PIWAR_2G); | |
b809b3e8 JL |
87 | } |
88 | ||
9ac4dd30 | 89 | void __init setup_pci_cmd(struct pci_controller *hose) |
b809b3e8 | 90 | { |
b809b3e8 | 91 | u16 cmd; |
b809b3e8 JL |
92 | early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); |
93 | cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | |
9ac4dd30 | 94 | | PCI_COMMAND_IO; |
b809b3e8 | 95 | early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); |
b809b3e8 | 96 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); |
9ad494f6 KG |
97 | } |
98 | ||
20243c72 ZW |
99 | static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) |
100 | { | |
101 | struct resource *res; | |
102 | int i, res_idx = PCI_BRIDGE_RESOURCES; | |
103 | struct pci_controller *hose; | |
104 | ||
957ecffc KG |
105 | /* if we aren't a PCIe don't bother */ |
106 | if (!pci_find_capability(dev, PCI_CAP_ID_EXP)) | |
107 | return ; | |
108 | ||
20243c72 ZW |
109 | /* |
110 | * Make the bridge be transparent. | |
111 | */ | |
112 | dev->transparent = 1; | |
113 | ||
0b1d40c4 | 114 | hose = pci_bus_to_host(dev->bus); |
20243c72 ZW |
115 | if (!hose) { |
116 | printk(KERN_ERR "Can't find hose for bus %d\n", | |
117 | dev->bus->number); | |
118 | return; | |
119 | } | |
120 | ||
7391ff35 KG |
121 | /* Clear out any of the virtual P2P bridge registers */ |
122 | pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0); | |
123 | pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0); | |
124 | pci_write_config_byte(dev, PCI_IO_BASE, 0x10); | |
125 | pci_write_config_byte(dev, PCI_IO_LIMIT, 0); | |
126 | pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10); | |
127 | pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0); | |
128 | pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0); | |
129 | pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0); | |
130 | pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10); | |
131 | pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0); | |
132 | ||
20243c72 ZW |
133 | if (hose->io_resource.flags) { |
134 | res = &dev->resource[res_idx++]; | |
135 | res->start = hose->io_resource.start; | |
136 | res->end = hose->io_resource.end; | |
137 | res->flags = hose->io_resource.flags; | |
7391ff35 | 138 | update_bridge_resource(dev, res); |
20243c72 ZW |
139 | } |
140 | ||
141 | for (i = 0; i < 3; i++) { | |
142 | res = &dev->resource[res_idx + i]; | |
143 | res->start = hose->mem_resources[i].start; | |
144 | res->end = hose->mem_resources[i].end; | |
145 | res->flags = hose->mem_resources[i].flags; | |
7391ff35 | 146 | update_bridge_resource(dev, res); |
20243c72 ZW |
147 | } |
148 | } | |
149 | ||
9ac4dd30 ZR |
150 | int __init fsl_pcie_check_link(struct pci_controller *hose) |
151 | { | |
152 | u16 val; | |
153 | early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); | |
154 | if (val < PCIE_LTSSM_L0) | |
155 | return 1; | |
156 | return 0; | |
157 | } | |
20243c72 | 158 | |
6c0a11c1 KG |
159 | void fsl_pcibios_fixup_bus(struct pci_bus *bus) |
160 | { | |
161 | struct pci_controller *hose = (struct pci_controller *) bus->sysdata; | |
162 | int i; | |
163 | ||
164 | /* deal with bogus pci_bus when we don't have anything connected on PCIe */ | |
165 | if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { | |
166 | if (bus->parent) { | |
167 | for (i = 0; i < 4; ++i) | |
168 | bus->resource[i] = bus->parent->resource[i]; | |
169 | } | |
170 | } | |
171 | } | |
172 | ||
9ac4dd30 | 173 | int __init fsl_add_bridge(struct device_node *dev, int is_primary) |
b809b3e8 JL |
174 | { |
175 | int len; | |
176 | struct pci_controller *hose; | |
177 | struct resource rsrc; | |
8efca493 | 178 | const int *bus_range; |
b809b3e8 | 179 | |
9ac4dd30 | 180 | pr_debug("Adding PCI host bridge %s\n", dev->full_name); |
b809b3e8 JL |
181 | |
182 | /* Fetch host bridge registers address */ | |
9ac4dd30 ZR |
183 | if (of_address_to_resource(dev, 0, &rsrc)) { |
184 | printk(KERN_WARNING "Can't get pci register base!"); | |
185 | return -ENOMEM; | |
186 | } | |
b809b3e8 JL |
187 | |
188 | /* Get bus range if any */ | |
e2eb6392 | 189 | bus_range = of_get_property(dev, "bus-range", &len); |
b809b3e8 JL |
190 | if (bus_range == NULL || len < 2 * sizeof(int)) |
191 | printk(KERN_WARNING "Can't get bus-range for %s, assume" | |
9ac4dd30 | 192 | " bus 0\n", dev->full_name); |
b809b3e8 | 193 | |
476f5779 | 194 | pci_assign_all_buses = 1; |
dbf8471f | 195 | hose = pcibios_alloc_controller(dev); |
b809b3e8 JL |
196 | if (!hose) |
197 | return -ENOMEM; | |
dbf8471f | 198 | |
b809b3e8 | 199 | hose->first_busno = bus_range ? bus_range[0] : 0x0; |
bf7c036f | 200 | hose->last_busno = bus_range ? bus_range[1] : 0xff; |
b809b3e8 | 201 | |
2e56ff20 KG |
202 | setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, |
203 | PPC_INDIRECT_TYPE_BIG_ENDIAN); | |
9ac4dd30 | 204 | setup_pci_cmd(hose); |
b809b3e8 | 205 | |
9ac4dd30 | 206 | /* check PCI express link status */ |
957ecffc KG |
207 | if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { |
208 | hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | | |
209 | PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; | |
9ac4dd30 | 210 | if (fsl_pcie_check_link(hose)) |
957ecffc KG |
211 | hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; |
212 | } | |
b809b3e8 | 213 | |
9ac4dd30 ZR |
214 | printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx." |
215 | "Firmware bus number: %d->%d\n", | |
216 | (unsigned long long)rsrc.start, hose->first_busno, | |
217 | hose->last_busno); | |
b809b3e8 | 218 | |
9ac4dd30 | 219 | pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
b809b3e8 JL |
220 | hose, hose->cfg_addr, hose->cfg_data); |
221 | ||
222 | /* Interpret the "ranges" property */ | |
223 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
9ac4dd30 | 224 | pci_process_bridge_OF_ranges(hose, dev, is_primary); |
b809b3e8 JL |
225 | |
226 | /* Setup PEX window registers */ | |
9ac4dd30 | 227 | setup_pci_atmu(hose, &rsrc); |
b809b3e8 JL |
228 | |
229 | return 0; | |
230 | } | |
9ac4dd30 | 231 | |
3f6c5dae RZ |
232 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0012, quirk_fsl_pcie_transparent); |
233 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0013, quirk_fsl_pcie_transparent); | |
234 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0014, quirk_fsl_pcie_transparent); | |
235 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0015, quirk_fsl_pcie_transparent); | |
236 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0018, quirk_fsl_pcie_transparent); | |
237 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0019, quirk_fsl_pcie_transparent); | |
238 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x001a, quirk_fsl_pcie_transparent); | |
aa3c1121 KG |
239 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0020, quirk_fsl_pcie_transparent); |
240 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0021, quirk_fsl_pcie_transparent); | |
241 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0024, quirk_fsl_pcie_transparent); | |
242 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0025, quirk_fsl_pcie_transparent); | |
f16dab98 RZ |
243 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0030, quirk_fsl_pcie_transparent); |
244 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0031, quirk_fsl_pcie_transparent); | |
9ac4dd30 ZR |
245 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); |
246 | DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); |