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powerpc/fsl-pci: fix the unreachable warning message
[linux-2.6-block.git] / arch / powerpc / sysdev / fsl_pci.c
CommitLineData
b809b3e8 1/*
5b70a097 2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
b809b3e8 3 *
07e4f801 4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
598804cd 5 * Copyright 2008-2009 MontaVista Software, Inc.
b809b3e8 6 *
9ac4dd30
ZR		 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
598804cd
AV		 11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
b809b3e8
JL		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
9ac4dd30 20#include <linux/kernel.h>
b809b3e8 21#include <linux/pci.h>
9ac4dd30
ZR		 22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/init.h>
25#include <linux/bootmem.h>
95f72d1e 26#include <linux/memblock.h>
54c18193 27#include <linux/log2.h>
5a0e3ad6 28#include <linux/slab.h>
4e0e3435 29#include <linux/uaccess.h>
b809b3e8 30
b809b3e8
JL		 31#include <asm/io.h>
32#include <asm/prom.h>
b809b3e8 33#include <asm/pci-bridge.h>
4e0e3435 34#include <asm/ppc-pci.h>
9ac4dd30 35#include <asm/machdep.h>
4e0e3435
HJ		 36#include <asm/disassemble.h>
37#include <asm/ppc-opcode.h>
b809b3e8 38#include <sysdev/fsl_soc.h>
55c44991 39#include <sysdev/fsl_pci.h>
b809b3e8 40
b8f44ec2 41static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
598804cd 42
cad5cef6 43static void quirk_fsl_pcie_header(struct pci_dev *dev)
598804cd 44{
59c58c32 45 u8 hdr_type;
470788d4 46
598804cd
AV		 47 /* if we aren't a PCIe don't bother */
48 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
49 return;
50
470788d4 51 /* if we aren't in host mode don't bother */
59c58c32
ML		 52 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
53 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
470788d4
KG		 54 return;
55
598804cd
AV		 56 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
57 fsl_pcie_bus_fixup = 1;
58 return;
59}
60
50d8f87d
RI		 61static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
62 int, int, u32 *);
63
64static int fsl_pcie_check_link(struct pci_controller *hose)
598804cd 65{
50d8f87d 66 u32 val = 0;
598804cd 67
34642bbb 68 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
50d8f87d
RI		 69 if (hose->ops->read == fsl_indirect_read_config) {
70 struct pci_bus bus;
71 bus.number = 0;
72 bus.sysdata = hose;
73 bus.ops = hose->ops;
74 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
75 } else
76 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
34642bbb
KG		 77 if (val < PCIE_LTSSM_L0)
78 return 1;
79 } else {
80 struct ccsr_pci __iomem *pci = hose->private_data;
81 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
82 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
83 >> PEX_CSR0_LTSSM_SHIFT;
84 if (val != PEX_CSR0_LTSSM_L0)
85 return 1;
cc6ea0dd 86 }
cc6ea0dd 87
598804cd
AV		 88 return 0;
89}
90
50d8f87d
RI		 91static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
92 int offset, int len, u32 *val)
93{
94 struct pci_controller *hose = pci_bus_to_host(bus);
95
96 if (fsl_pcie_check_link(hose))
97 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
98 else
99 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
100
101 return indirect_read_config(bus, devfn, offset, len, val);
102}
103
b37e1613
RI		 104#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
105
106static struct pci_ops fsl_indirect_pcie_ops =
50d8f87d
RI		 107{
108 .read = fsl_indirect_read_config,
109 .write = indirect_write_config,
110};
111
96ea3b4a
KG		 112#define MAX_PHYS_ADDR_BITS 40
113static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
114
115static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
116{
117 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
118 return -EIO;
119
120 /*
121 * Fixup PCI devices that are able to DMA to above the physical
122 * address width of the SoC such that we can address any internal
123 * SoC address from across PCI if needed
124 */
125 if ((dev->bus == &pci_bus_type) &&
126 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
127 set_dma_ops(dev, &dma_direct_ops);
128 set_dma_offset(dev, pci64_dma_offset);
129 }
130
131 *dev->dma_mask = dma_mask;
132 return 0;
133}
134
a393d897 135static int setup_one_atmu(struct ccsr_pci __iomem *pci,
a097a78c
TP		 136 unsigned int index, const struct resource *res,
137 resource_size_t offset)
138{
139 resource_size_t pci_addr = res->start - offset;
140 resource_size_t phys_addr = res->start;
28f65c11 141 resource_size_t size = resource_size(res);
a097a78c
TP		 142 u32 flags = 0x80044000; /* enable & mem R/W */
143 unsigned int i;
144
145 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
146 (u64)res->start, (u64)size);
147
565f3764
TP		 148 if (res->flags & IORESOURCE_PREFETCH)
149 flags |= 0x10000000; /* enable relaxed ordering */
150
a097a78c 151 for (i = 0; size > 0; i++) {
2b4a8bd2 152 unsigned int bits = min(ilog2(size),
a097a78c
TP		 153 __ffs(pci_addr | phys_addr));
154
155 if (index + i >= 5)
156 return -1;
157
158 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
159 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
160 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
161 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
162
163 pci_addr += (resource_size_t)1U << bits;
164 phys_addr += (resource_size_t)1U << bits;
165 size -= (resource_size_t)1U << bits;
166 }
167
168 return i;
169}
170
9ac4dd30 171/* atmu setup for fsl pci/pcie controller */
34642bbb 172static void setup_pci_atmu(struct pci_controller *hose)
b809b3e8 173{
34642bbb 174 struct ccsr_pci __iomem *pci = hose->private_data;
f4154e16 175 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
54c18193 176 u64 mem, sz, paddr_hi = 0;
3fd47f06 177 u64 offset = 0, paddr_lo = ULLONG_MAX;
54c18193
KG		 178 u32 pcicsrbar = 0, pcicsrbar_sz;
179 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
180 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
c22618a1 181 const char *name = hose->dn->full_name;
446bc1ff
TT		 182 const u64 *reg;
183 int len;
b809b3e8 184
9e67886b
RZ		 185 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
186 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
187 win_idx = 2;
188 start_idx = 0;
189 end_idx = 3;
190 }
191 }
192
a097a78c 193 /* Disable all windows (except powar0 since it's ignored) */
9ac4dd30
ZR		 194 for(i = 1; i < 5; i++)
195 out_be32(&pci->pow[i].powar, 0);
f4154e16 196 for (i = start_idx; i < end_idx; i++)
9ac4dd30
ZR		 197 out_be32(&pci->piw[i].piwar, 0);
198
199 /* Setup outbound MEM window */
a097a78c
TP		 200 for(i = 0, j = 1; i < 3; i++) {
201 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
202 continue;
203
54c18193
KG		 204 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
205 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
206
3fd47f06
BH		 207 /* We assume all memory resources have the same offset */
208 offset = hose->mem_offset[i];
209 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
a097a78c
TP		 210
211 if (n < 0 || j >= 5) {
212 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
213 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
214 } else
215 j += n;
216 }
9ac4dd30
ZR		 217
218 /* Setup outbound IO window */
a097a78c
TP		 219 if (hose->io_resource.flags & IORESOURCE_IO) {
220 if (j >= 5) {
221 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
222 } else {
223 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
224 "phy base 0x%016llx.\n",
28f65c11
JP		 225 (u64)hose->io_resource.start,
226 (u64)resource_size(&hose->io_resource),
227 (u64)hose->io_base_phys);
a097a78c
TP		 228 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
229 out_be32(&pci->pow[j].potear, 0);
230 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
231 /* Enable, IO R/W */
232 out_be32(&pci->pow[j].powar, 0x80088000
2b4a8bd2 233 | (ilog2(hose->io_resource.end
a097a78c
TP		 234 - hose->io_resource.start + 1) - 1));
235 }
9ac4dd30
ZR		 236 }
237
54c18193 238 /* convert to pci address space */
3fd47f06
BH		 239 paddr_hi -= offset;
240 paddr_lo -= offset;
54c18193
KG		 241
242 if (paddr_hi == paddr_lo) {
243 pr_err("%s: No outbound window space\n", name);
04aa99cd 244 return;
54c18193
KG		 245 }
246
247 if (paddr_lo == 0) {
248 pr_err("%s: No space for inbound window\n", name);
04aa99cd 249 return;
54c18193
KG		 250 }
251
252 /* setup PCSRBAR/PEXCSRBAR */
253 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
254 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
255 pcicsrbar_sz = ~pcicsrbar_sz + 1;
256
257 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
258 (paddr_lo > 0x100000000ull))
259 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
260 else
261 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
262 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
263
264 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
265
266 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
267
268 /* Setup inbound mem window */
95f72d1e 269 mem = memblock_end_of_DRAM();
446bc1ff
TT		 270
271 /*
272 * The msi-address-64 property, if it exists, indicates the physical
273 * address of the MSIIR register. Normally, this register is located
274 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
275 * this property exists, then we normally need to create a new ATMU
276 * for it. For now, however, we cheat. The only entity that creates
277 * this property is the Freescale hypervisor, and the address is
278 * specified in the partition configuration. Typically, the address
279 * is located in the page immediately after the end of DDR. If so, we
280 * can avoid allocating a new ATMU by extending the DDR ATMU by one
281 * page.
282 */
283 reg = of_get_property(hose->dn, "msi-address-64", &len);
284 if (reg && (len == sizeof(u64))) {
285 u64 address = be64_to_cpup(reg);
286
287 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
288 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
289 mem += PAGE_SIZE;
290 } else {
291 /* TODO: Create a new ATMU for MSIIR */
292 pr_warn("%s: msi-address-64 address of %llx is "
293 "unsupported\n", name, address);
294 }
295 }
296
54c18193 297 sz = min(mem, paddr_lo);
2b4a8bd2 298 mem_log = ilog2(sz);
54c18193
KG		 299
300 /* PCIe can overmap inbound & outbound since RX & TX are separated */
301 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
302 /* Size window to exact size if power-of-two or one size up */
303 if ((1ull << mem_log) != mem) {
2d49c42a 304 mem_log++;
54c18193
KG		 305 if ((1ull << mem_log) > mem)
306 pr_info("%s: Setting PCI inbound window "
307 "greater than memory size\n", name);
54c18193
KG		 308 }
309
f4154e16 310 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
54c18193
KG		 311
312 /* Setup inbound memory window */
313 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
314 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
315 out_be32(&pci->piw[win_idx].piwar, piwar);
316 win_idx--;
317
318 hose->dma_window_base_cur = 0x00000000;
319 hose->dma_window_size = (resource_size_t)sz;
96ea3b4a
KG		 320
321 /*
322 * if we have >4G of memory setup second PCI inbound window to
323 * let devices that are 64-bit address capable to work w/o
324 * SWIOTLB and access the full range of memory
325 */
326 if (sz != mem) {
2b4a8bd2 327 mem_log = ilog2(mem);
96ea3b4a
KG		 328
329 /* Size window up if we dont fit in exact power-of-2 */
330 if ((1ull << mem_log) != mem)
331 mem_log++;
332
333 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
334
335 /* Setup inbound memory window */
336 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
337 out_be32(&pci->piw[win_idx].piwbear,
338 pci64_dma_offset >> 44);
339 out_be32(&pci->piw[win_idx].piwbar,
340 pci64_dma_offset >> 12);
341 out_be32(&pci->piw[win_idx].piwar, piwar);
342
343 /*
344 * install our own dma_set_mask handler to fixup dma_ops
345 * and dma_offset
346 */
347 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
348
349 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
350 }
54c18193
KG		 351 } else {
352 u64 paddr = 0;
353
354 /* Setup inbound memory window */
355 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
356 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
357 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
358 win_idx--;
359
360 paddr += 1ull << mem_log;
361 sz -= 1ull << mem_log;
362
363 if (sz) {
2b4a8bd2 364 mem_log = ilog2(sz);
54c18193
KG		 365 piwar |= (mem_log - 1);
366
367 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
368 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
369 out_be32(&pci->piw[win_idx].piwar, piwar);
370 win_idx--;
371
372 paddr += 1ull << mem_log;
373 }
374
375 hose->dma_window_base_cur = 0x00000000;
376 hose->dma_window_size = (resource_size_t)paddr;
377 }
a097a78c 378
54c18193
KG		 379 if (hose->dma_window_size < mem) {
380#ifndef CONFIG_SWIOTLB
381 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
382 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
383 name);
384#endif
385 /* adjusting outbound windows could reclaim space in mem map */
386 if (paddr_hi < 0xffffffffull)
387 pr_warning("%s: WARNING: Outbound window cfg leaves "
388 "gaps in memory map. Adjusting the memory map "
389 "could reduce unnecessary bounce buffering.\n",
390 name);
391
392 pr_info("%s: DMA window size is 0x%llx\n", name,
393 (u64)hose->dma_window_size);
394 }
b809b3e8
JL		 395}
396
c9dadffb 397static void __init setup_pci_cmd(struct pci_controller *hose)
b809b3e8 398{
b809b3e8 399 u16 cmd;
eb12af43
KG		 400 int cap_x;
401
b809b3e8
JL		 402 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
403 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
9ac4dd30 404 | PCI_COMMAND_IO;
b809b3e8 405 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
eb12af43
KG		 406
407 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
408 if (cap_x) {
409 int pci_x_cmd = cap_x + PCI_X_CMD;
410 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
411 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
412 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
413 } else {
414 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
415 }
9ad494f6
KG		 416}
417
6c0a11c1
KG		 418void fsl_pcibios_fixup_bus(struct pci_bus *bus)
419{
8206a110 420 struct pci_controller *hose = pci_bus_to_host(bus);
13635dfd
BH		 421 int i, is_pcie = 0, no_link;
422
423 /* The root complex bridge comes up with bogus resources,
424 * we copy the PHB ones in.
425 *
426 * With the current generic PCI code, the PHB bus no longer
427 * has bus->resource[0..4] set, so things are a bit more
428 * tricky.
429 */
430
431 if (fsl_pcie_bus_fixup)
432 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
433 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
434
435 if (bus->parent == hose->bus && (is_pcie || no_link)) {
436 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
72b122cc 437 struct resource *res = bus->resource[i];
13635dfd
BH		 438 struct resource *par;
439
440 if (!res)
441 continue;
442 if (i == 0)
443 par = &hose->io_resource;
444 else if (i < 4)
445 par = &hose->mem_resources[i-1];
446 else par = NULL;
447
448 res->start = par ? par->start : 0;
449 res->end = par ? par->end : 0;
450 res->flags = par ? par->flags : 0;
6c0a11c1
KG		 451 }
452 }
453}
454
52c5affc 455int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
b809b3e8
JL		 456{
457 int len;
458 struct pci_controller *hose;
459 struct resource rsrc;
8efca493 460 const int *bus_range;
59c58c32 461 u8 hdr_type, progif;
52c5affc 462 struct device_node *dev;
34642bbb 463 struct ccsr_pci __iomem *pci;
52c5affc
VS		 464
465 dev = pdev->dev.of_node;
b809b3e8 466
ef1fd2df
PK		 467 if (!of_device_is_available(dev)) {
468 pr_warning("%s: disabled\n", dev->full_name);
469 return -ENODEV;
470 }
471
9ac4dd30 472 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
b809b3e8
JL		 473
474 /* Fetch host bridge registers address */
9ac4dd30
ZR		 475 if (of_address_to_resource(dev, 0, &rsrc)) {
476 printk(KERN_WARNING "Can't get pci register base!");
477 return -ENOMEM;
478 }
b809b3e8
JL		 479
480 /* Get bus range if any */
e2eb6392 481 bus_range = of_get_property(dev, "bus-range", &len);
b809b3e8
JL		 482 if (bus_range == NULL || len < 2 * sizeof(int))
483 printk(KERN_WARNING "Can't get bus-range for %s, assume"
9ac4dd30 484 " bus 0\n", dev->full_name);
b809b3e8 485
0e47ff1c 486 pci_add_flags(PCI_REASSIGN_ALL_BUS);
dbf8471f 487 hose = pcibios_alloc_controller(dev);
b809b3e8
JL		 488 if (!hose)
489 return -ENOMEM;
dbf8471f 490
52c5affc
VS		 491 /* set platform device as the parent */
492 hose->parent = &pdev->dev;
b809b3e8 493 hose->first_busno = bus_range ? bus_range[0] : 0x0;
bf7c036f 494 hose->last_busno = bus_range ? bus_range[1] : 0xff;
b809b3e8 495
34642bbb
KG		 496 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
497 (u64)rsrc.start, (u64)resource_size(&rsrc));
498
499 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
500 if (!hose->private_data)
501 goto no_bridge;
502
b37e1613
RI		 503 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
504 PPC_INDIRECT_TYPE_BIG_ENDIAN);
08871c09 505
34642bbb
KG		 506 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
507 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
508
59c58c32 509 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
b37e1613
RI		 510 /* use fsl_indirect_read_config for PCIe */
511 hose->ops = &fsl_indirect_pcie_ops;
59c58c32
ML		 512 /* For PCIE read HEADER_TYPE to identify controler mode */
513 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
514 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
515 goto no_bridge;
516
517 } else {
518 /* For PCI read PROG to identify controller mode */
519 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
520 if ((progif & 1) == 1)
521 goto no_bridge;
08871c09
PK		 522 }
523
9ac4dd30 524 setup_pci_cmd(hose);
b809b3e8 525
9ac4dd30 526 /* check PCI express link status */
957ecffc 527 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
7659c038 528 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
957ecffc 529 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
34642bbb 530 if (fsl_pcie_check_link(hose))
957ecffc
KG		 531 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
532 }
b809b3e8 533
df3c9019 534 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
9ac4dd30
ZR		 535 "Firmware bus number: %d->%d\n",
536 (unsigned long long)rsrc.start, hose->first_busno,
537 hose->last_busno);
b809b3e8 538
9ac4dd30 539 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
b809b3e8
JL		 540 hose, hose->cfg_addr, hose->cfg_data);
541
542 /* Interpret the "ranges" property */
543 /* This also maps the I/O region and sets isa_io/mem_base */
9ac4dd30 544 pci_process_bridge_OF_ranges(hose, dev, is_primary);
b809b3e8
JL		 545
546 /* Setup PEX window registers */
34642bbb 547 setup_pci_atmu(hose);
b809b3e8
JL		 548
549 return 0;
59c58c32
ML		 550
551no_bridge:
34642bbb 552 iounmap(hose->private_data);
59c58c32
ML		 553 /* unmap cfg_data & cfg_addr separately if not on same page */
554 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
555 ((unsigned long)hose->cfg_addr & PAGE_MASK))
556 iounmap(hose->cfg_data);
557 iounmap(hose->cfg_addr);
558 pcibios_free_controller(hose);
559 return -ENODEV;
b809b3e8 560}
5753c082 561#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
76fe1ffc 562
470788d4 563DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
598804cd 564
470788d4 565#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
598804cd
AV		 566struct mpc83xx_pcie_priv {
567 void __iomem *cfg_type0;
568 void __iomem *cfg_type1;
569 u32 dev_base;
570};
571
b8f44ec2
KG		 572struct pex_inbound_window {
573 u32 ar;
574 u32 tar;
575 u32 barl;
576 u32 barh;
577};
578
598804cd
AV		 579/*
580 * With the convention of u-boot, the PCIE outbound window 0 serves
581 * as configuration transactions outbound.
582 */
583#define PEX_OUTWIN0_BAR 0xCA4
584#define PEX_OUTWIN0_TAL 0xCA8
585#define PEX_OUTWIN0_TAH 0xCAC
b8f44ec2
KG		 586#define PEX_RC_INWIN_BASE 0xE60
587#define PEX_RCIWARn_EN 0x1
598804cd
AV		 588
589static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
590{
8206a110 591 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 592
593 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
594 return PCIBIOS_DEVICE_NOT_FOUND;
595 /*
596 * Workaround for the HW bug: for Type 0 configure transactions the
597 * PCI-E controller does not check the device number bits and just
598 * assumes that the device number bits are 0.
599 */
600 if (bus->number == hose->first_busno ||
601 bus->primary == hose->first_busno) {
602 if (devfn & 0xf8)
603 return PCIBIOS_DEVICE_NOT_FOUND;
604 }
605
606 if (ppc_md.pci_exclude_device) {
607 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
608 return PCIBIOS_DEVICE_NOT_FOUND;
609 }
610
611 return PCIBIOS_SUCCESSFUL;
612}
613
614static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
615 unsigned int devfn, int offset)
616{
8206a110 617 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd 618 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
f93611fa 619 u32 dev_base = bus->number << 24 | devfn << 16;
598804cd
AV		 620 int ret;
621
622 ret = mpc83xx_pcie_exclude_device(bus, devfn);
623 if (ret)
624 return NULL;
625
626 offset &= 0xfff;
627
628 /* Type 0 */
629 if (bus->number == hose->first_busno)
630 return pcie->cfg_type0 + offset;
631
632 if (pcie->dev_base == dev_base)
633 goto mapped;
634
635 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
636
637 pcie->dev_base = dev_base;
638mapped:
639 return pcie->cfg_type1 + offset;
640}
641
642static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
643 int offset, int len, u32 *val)
644{
645 void __iomem *cfg_addr;
646
647 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
648 if (!cfg_addr)
649 return PCIBIOS_DEVICE_NOT_FOUND;
650
651 switch (len) {
652 case 1:
653 *val = in_8(cfg_addr);
654 break;
655 case 2:
656 *val = in_le16(cfg_addr);
657 break;
658 default:
659 *val = in_le32(cfg_addr);
660 break;
661 }
662
663 return PCIBIOS_SUCCESSFUL;
664}
665
666static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
667 int offset, int len, u32 val)
668{
f93611fa 669 struct pci_controller *hose = pci_bus_to_host(bus);
598804cd
AV		 670 void __iomem *cfg_addr;
671
672 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
673 if (!cfg_addr)
674 return PCIBIOS_DEVICE_NOT_FOUND;
675
f93611fa
AV		 676 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
677 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
678 val &= 0xffffff00;
679
598804cd
AV		 680 switch (len) {
681 case 1:
682 out_8(cfg_addr, val);
683 break;
684 case 2:
685 out_le16(cfg_addr, val);
686 break;
687 default:
688 out_le32(cfg_addr, val);
689 break;
690 }
691
692 return PCIBIOS_SUCCESSFUL;
693}
694
695static struct pci_ops mpc83xx_pcie_ops = {
696 .read = mpc83xx_pcie_read_config,
697 .write = mpc83xx_pcie_write_config,
698};
699
700static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
701 struct resource *reg)
702{
703 struct mpc83xx_pcie_priv *pcie;
704 u32 cfg_bar;
705 int ret = -ENOMEM;
706
707 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
708 if (!pcie)
709 return ret;
710
711 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
712 if (!pcie->cfg_type0)
713 goto err0;
714
715 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
716 if (!cfg_bar) {
717 /* PCI-E isn't configured. */
718 ret = -ENODEV;
719 goto err1;
720 }
721
722 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
723 if (!pcie->cfg_type1)
724 goto err1;
725
726 WARN_ON(hose->dn->data);
727 hose->dn->data = pcie;
728 hose->ops = &mpc83xx_pcie_ops;
34642bbb 729 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
598804cd
AV		 730
731 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
732 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
733
34642bbb 734 if (fsl_pcie_check_link(hose))
598804cd
AV		 735 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
736
737 return 0;
738err1:
739 iounmap(pcie->cfg_type0);
740err0:
741 kfree(pcie);
742 return ret;
743
744}
745
76fe1ffc
JR		 746int __init mpc83xx_add_bridge(struct device_node *dev)
747{
598804cd 748 int ret;
76fe1ffc
JR		 749 int len;
750 struct pci_controller *hose;
5b70a097
JR		 751 struct resource rsrc_reg;
752 struct resource rsrc_cfg;
76fe1ffc 753 const int *bus_range;
5b70a097 754 int primary;
76fe1ffc 755
b8f44ec2
KG		 756 is_mpc83xx_pci = 1;
757
598804cd
AV		 758 if (!of_device_is_available(dev)) {
759 pr_warning("%s: disabled by the firmware.\n",
760 dev->full_name);
761 return -ENODEV;
762 }
76fe1ffc
JR		 763 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
764
765 /* Fetch host bridge registers address */
5b70a097
JR		 766 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
767 printk(KERN_WARNING "Can't get pci register base!\n");
768 return -ENOMEM;
769 }
770
771 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
772
773 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
774 printk(KERN_WARNING
775 "No pci config register base in dev tree, "
776 "using default\n");
777 /*
778 * MPC83xx supports up to two host controllers
779 * one at 0x8500 has config space registers at 0x8300
780 * one at 0x8600 has config space registers at 0x8380
781 */
782 if ((rsrc_reg.start & 0xfffff) == 0x8500)
783 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
784 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
785 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
786 }
787 /*
788 * Controller at offset 0x8500 is primary
789 */
790 if ((rsrc_reg.start & 0xfffff) == 0x8500)
791 primary = 1;
792 else
793 primary = 0;
76fe1ffc
JR		 794
795 /* Get bus range if any */
796 bus_range = of_get_property(dev, "bus-range", &len);
797 if (bus_range == NULL || len < 2 * sizeof(int)) {
798 printk(KERN_WARNING "Can't get bus-range for %s, assume"
799 " bus 0\n", dev->full_name);
800 }
801
0e47ff1c 802 pci_add_flags(PCI_REASSIGN_ALL_BUS);
76fe1ffc
JR		 803 hose = pcibios_alloc_controller(dev);
804 if (!hose)
805 return -ENOMEM;
806
807 hose->first_busno = bus_range ? bus_range[0] : 0;
808 hose->last_busno = bus_range ? bus_range[1] : 0xff;
809
598804cd
AV		 810 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
811 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
812 if (ret)
813 goto err0;
814 } else {
b37e1613
RI		 815 setup_indirect_pci(hose, rsrc_cfg.start,
816 rsrc_cfg.start + 4, 0);
598804cd 817 }
76fe1ffc 818
35225802 819 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
76fe1ffc 820 "Firmware bus number: %d->%d\n",
5b70a097 821 (unsigned long long)rsrc_reg.start, hose->first_busno,
76fe1ffc
JR		 822 hose->last_busno);
823
824 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
825 hose, hose->cfg_addr, hose->cfg_data);
826
827 /* Interpret the "ranges" property */
828 /* This also maps the I/O region and sets isa_io/mem_base */
829 pci_process_bridge_OF_ranges(hose, dev, primary);
830
831 return 0;
598804cd
AV		 832err0:
833 pcibios_free_controller(hose);
834 return ret;
76fe1ffc
JR		 835}
836#endif /* CONFIG_PPC_83xx */
b8f44ec2
KG		 837
838u64 fsl_pci_immrbar_base(struct pci_controller *hose)
839{
840#ifdef CONFIG_PPC_83xx
841 if (is_mpc83xx_pci) {
842 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
843 struct pex_inbound_window *in;
844 int i;
845
846 /* Walk the Root Complex Inbound windows to match IMMR base */
847 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
848 for (i = 0; i < 4; i++) {
849 /* not enabled, skip */
850 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
851 continue;
852
853 if (get_immrbase() == in_le32(&in[i].tar))
854 return (u64)in_le32(&in[i].barh) << 32 |
855 in_le32(&in[i].barl);
856 }
857
858 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
859 }
860#endif
861
862#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
863 if (!is_mpc83xx_pci) {
864 u32 base;
865
866 pci_bus_read_config_dword(hose->bus,
867 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
868 return base;
869 }
870#endif
871
872 return 0;
873}
07e4f801 874
4e0e3435
HJ		 875#ifdef CONFIG_E500
876static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
877{
878 unsigned int rd, ra, rb, d;
879
880 rd = get_rt(inst);
881 ra = get_ra(inst);
882 rb = get_rb(inst);
883 d = get_d(inst);
884
885 switch (get_op(inst)) {
886 case 31:
887 switch (get_xop(inst)) {
888 case OP_31_XOP_LWZX:
889 case OP_31_XOP_LWBRX:
890 regs->gpr[rd] = 0xffffffff;
891 break;
892
893 case OP_31_XOP_LWZUX:
894 regs->gpr[rd] = 0xffffffff;
895 regs->gpr[ra] += regs->gpr[rb];
896 break;
897
898 case OP_31_XOP_LBZX:
899 regs->gpr[rd] = 0xff;
900 break;
901
902 case OP_31_XOP_LBZUX:
903 regs->gpr[rd] = 0xff;
904 regs->gpr[ra] += regs->gpr[rb];
905 break;
906
907 case OP_31_XOP_LHZX:
908 case OP_31_XOP_LHBRX:
909 regs->gpr[rd] = 0xffff;
910 break;
911
912 case OP_31_XOP_LHZUX:
913 regs->gpr[rd] = 0xffff;
914 regs->gpr[ra] += regs->gpr[rb];
915 break;
916
917 case OP_31_XOP_LHAX:
918 regs->gpr[rd] = ~0UL;
919 break;
920
921 case OP_31_XOP_LHAUX:
922 regs->gpr[rd] = ~0UL;
923 regs->gpr[ra] += regs->gpr[rb];
924 break;
925
926 default:
927 return 0;
928 }
929 break;
930
931 case OP_LWZ:
932 regs->gpr[rd] = 0xffffffff;
933 break;
934
935 case OP_LWZU:
936 regs->gpr[rd] = 0xffffffff;
937 regs->gpr[ra] += (s16)d;
938 break;
939
940 case OP_LBZ:
941 regs->gpr[rd] = 0xff;
942 break;
943
944 case OP_LBZU:
945 regs->gpr[rd] = 0xff;
946 regs->gpr[ra] += (s16)d;
947 break;
948
949 case OP_LHZ:
950 regs->gpr[rd] = 0xffff;
951 break;
952
953 case OP_LHZU:
954 regs->gpr[rd] = 0xffff;
955 regs->gpr[ra] += (s16)d;
956 break;
957
958 case OP_LHA:
959 regs->gpr[rd] = ~0UL;
960 break;
961
962 case OP_LHAU:
963 regs->gpr[rd] = ~0UL;
964 regs->gpr[ra] += (s16)d;
965 break;
966
967 default:
968 return 0;
969 }
970
971 return 1;
972}
973
974static int is_in_pci_mem_space(phys_addr_t addr)
975{
976 struct pci_controller *hose;
977 struct resource *res;
978 int i;
979
980 list_for_each_entry(hose, &hose_list, list_node) {
981 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
982 continue;
983
984 for (i = 0; i < 3; i++) {
985 res = &hose->mem_resources[i];
986 if ((res->flags & IORESOURCE_MEM) &&
987 addr >= res->start && addr <= res->end)
988 return 1;
989 }
990 }
991 return 0;
992}
993
994int fsl_pci_mcheck_exception(struct pt_regs *regs)
995{
996 u32 inst;
997 int ret;
998 phys_addr_t addr = 0;
999
1000 /* Let KVM/QEMU deal with the exception */
1001 if (regs->msr & MSR_GS)
1002 return 0;
1003
1004#ifdef CONFIG_PHYS_64BIT
1005 addr = mfspr(SPRN_MCARU);
1006 addr <<= 32;
1007#endif
1008 addr += mfspr(SPRN_MCAR);
1009
1010 if (is_in_pci_mem_space(addr)) {
1011 if (user_mode(regs)) {
1012 pagefault_disable();
1013 ret = get_user(regs->nip, &inst);
1014 pagefault_enable();
1015 } else {
1016 ret = probe_kernel_address(regs->nip, inst);
1017 }
1018
1019 if (mcheck_handle_load(regs, inst)) {
1020 regs->nip += 4;
1021 return 1;
1022 }
1023 }
1024
1025 return 0;
1026}
1027#endif
1028
07e4f801
SW		 1029#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
1030static const struct of_device_id pci_ids[] = {
1031 { .compatible = "fsl,mpc8540-pci", },
1032 { .compatible = "fsl,mpc8548-pcie", },
1033 { .compatible = "fsl,mpc8610-pci", },
1034 { .compatible = "fsl,mpc8641-pcie", },
14bdc913
TT		 1035 { .compatible = "fsl,qoriq-pcie-v2.1", },
1036 { .compatible = "fsl,qoriq-pcie-v2.2", },
1037 { .compatible = "fsl,qoriq-pcie-v2.3", },
1038 { .compatible = "fsl,qoriq-pcie-v2.4", },
cc6ea0dd 1039 { .compatible = "fsl,qoriq-pcie-v3.0", },
14bdc913
TT		 1040
1041 /*
1042 * The following entries are for compatibility with older device
1043 * trees.
1044 */
07e4f801 1045 { .compatible = "fsl,p1022-pcie", },
07e4f801 1046 { .compatible = "fsl,p4080-pcie", },
14bdc913 1047
07e4f801
SW		 1048 {},
1049};
1050
1051struct device_node *fsl_pci_primary;
1052
905e75c4 1053void fsl_pci_assign_primary(void)
07e4f801 1054{
905e75c4 1055 struct device_node *np;
07e4f801
SW		 1056
1057 /* Callers can specify the primary bus using other means. */
905e75c4
JH		 1058 if (fsl_pci_primary)
1059 return;
1060
1061 /* If a PCI host bridge contains an ISA node, it's primary. */
1062 np = of_find_node_by_type(NULL, "isa");
1063 while ((fsl_pci_primary = of_get_parent(np))) {
1064 of_node_put(np);
1065 np = fsl_pci_primary;
1066
1067 if (of_match_node(pci_ids, np) && of_device_is_available(np))
1068 return;
07e4f801
SW		 1069 }
1070
905e75c4
JH		 1071 /*
1072 * If there's no PCI host bridge with ISA, arbitrarily
1073 * designate one as primary. This can go away once
1074 * various bugs with primary-less systems are fixed.
1075 */
1076 for_each_matching_node(np, pci_ids) {
1077 if (of_device_is_available(np)) {
1078 fsl_pci_primary = np;
1079 of_node_put(np);
1080 return;
07e4f801
SW		 1081 }
1082 }
905e75c4
JH		 1083}
1084
cad5cef6 1085static int fsl_pci_probe(struct platform_device *pdev)
905e75c4
JH		 1086{
1087 int ret;
1088 struct device_node *node;
4d56dec5 1089#ifdef CONFIG_SWIOTLB
905e75c4 1090 struct pci_controller *hose;
4d56dec5 1091#endif
905e75c4
JH		 1092
1093 node = pdev->dev.of_node;
52c5affc 1094 ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
07e4f801
SW		 1095
1096#ifdef CONFIG_SWIOTLB
905e75c4
JH		 1097 if (ret == 0) {
1098 hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
1099
1100 /*
1101 * if we couldn't map all of DRAM via the dma windows
1102 * we need SWIOTLB to handle buffers located outside of
1103 * dma capable memory region
1104 */
1105 if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur +
1106 hose->dma_window_size)
1107 ppc_swiotlb_enable = 1;
1108 }
07e4f801 1109#endif
905e75c4
JH		 1110
1111 mpc85xx_pci_err_probe(pdev);
1112
1113 return 0;
1114}
1115
a393d897
JH		 1116#ifdef CONFIG_PM
1117static int fsl_pci_resume(struct device *dev)
1118{
1119 struct pci_controller *hose;
1120 struct resource pci_rsrc;
1121
1122 hose = pci_find_hose_for_OF_device(dev->of_node);
1123 if (!hose)
1124 return -ENODEV;
1125
1126 if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
1127 dev_err(dev, "Get pci register base failed.");
1128 return -ENODEV;
1129 }
1130
d5bbe659 1131 setup_pci_atmu(hose);
a393d897
JH		 1132
1133 return 0;
1134}
1135
1136static const struct dev_pm_ops pci_pm_ops = {
1137 .resume = fsl_pci_resume,
1138};
1139
1140#define PCI_PM_OPS (&pci_pm_ops)
1141
1142#else
1143
1144#define PCI_PM_OPS NULL
1145
1146#endif
1147
905e75c4
JH		 1148static struct platform_driver fsl_pci_driver = {
1149 .driver = {
1150 .name = "fsl-pci",
a393d897 1151 .pm = PCI_PM_OPS,
905e75c4
JH		 1152 .of_match_table = pci_ids,
1153 },
1154 .probe = fsl_pci_probe,
1155};
1156
1157static int __init fsl_pci_init(void)
1158{
1159 return platform_driver_register(&fsl_pci_driver);
07e4f801 1160}
905e75c4 1161arch_initcall(fsl_pci_init);
07e4f801 1162#endif
Linux 6.x block layer and io_uring tree(s)