Commit | Line | Data |
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34e36c15 | 1 | /* |
6820fead | 2 | * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. |
34e36c15 JJ |
3 | * |
4 | * Author: Tony Li <tony.li@freescale.com> | |
5 | * Jason Jin <Jason.jin@freescale.com> | |
6 | * | |
7 | * The hwirq alloc and free code reuse from sysdev/mpic_msi.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; version 2 of the | |
12 | * License. | |
13 | * | |
14 | */ | |
15 | #include <linux/irq.h> | |
16 | #include <linux/bootmem.h> | |
34e36c15 JJ |
17 | #include <linux/msi.h> |
18 | #include <linux/pci.h> | |
5a0e3ad6 | 19 | #include <linux/slab.h> |
34e36c15 JJ |
20 | #include <linux/of_platform.h> |
21 | #include <sysdev/fsl_soc.h> | |
22 | #include <asm/prom.h> | |
23 | #include <asm/hw_irq.h> | |
24 | #include <asm/ppc-pci.h> | |
02adac60 | 25 | #include <asm/mpic.h> |
446bc1ff TT |
26 | #include <asm/fsl_hcalls.h> |
27 | ||
34e36c15 | 28 | #include "fsl_msi.h" |
b8f44ec2 | 29 | #include "fsl_pci.h" |
34e36c15 | 30 | |
694a7a36 LY |
31 | LIST_HEAD(msi_head); |
32 | ||
34e36c15 JJ |
33 | struct fsl_msi_feature { |
34 | u32 fsl_pic_ip; | |
2bcd1c0c | 35 | u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */ |
34e36c15 JJ |
36 | }; |
37 | ||
02adac60 LY |
38 | struct fsl_msi_cascade_data { |
39 | struct fsl_msi *msi_data; | |
40 | int index; | |
41 | }; | |
34e36c15 JJ |
42 | |
43 | static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) | |
44 | { | |
45 | return in_be32(base + (reg >> 2)); | |
46 | } | |
47 | ||
34e36c15 JJ |
48 | /* |
49 | * We do not need this actually. The MSIR register has been read once | |
50 | * in the cascade interrupt. So, this MSI interrupt has been acked | |
51 | */ | |
37e16615 | 52 | static void fsl_msi_end_irq(struct irq_data *d) |
34e36c15 JJ |
53 | { |
54 | } | |
55 | ||
56 | static struct irq_chip fsl_msi_chip = { | |
1c9db525 TG |
57 | .irq_mask = mask_msi_irq, |
58 | .irq_unmask = unmask_msi_irq, | |
37e16615 | 59 | .irq_ack = fsl_msi_end_irq, |
fc380c0c | 60 | .name = "FSL-MSI", |
34e36c15 JJ |
61 | }; |
62 | ||
bae1d8f1 | 63 | static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq, |
34e36c15 JJ |
64 | irq_hw_number_t hw) |
65 | { | |
80818813 | 66 | struct fsl_msi *msi_data = h->host_data; |
34e36c15 JJ |
67 | struct irq_chip *chip = &fsl_msi_chip; |
68 | ||
98488db9 | 69 | irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING); |
34e36c15 | 70 | |
ec775d0e TG |
71 | irq_set_chip_data(virq, msi_data); |
72 | irq_set_chip_and_handler(virq, chip, handle_edge_irq); | |
34e36c15 JJ |
73 | |
74 | return 0; | |
75 | } | |
76 | ||
9f70b8eb | 77 | static const struct irq_domain_ops fsl_msi_host_ops = { |
34e36c15 JJ |
78 | .map = fsl_msi_host_map, |
79 | }; | |
80 | ||
34e36c15 JJ |
81 | static int fsl_msi_init_allocator(struct fsl_msi *msi_data) |
82 | { | |
692d1037 | 83 | int rc; |
34e36c15 | 84 | |
7e7ab367 ME |
85 | rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS, |
86 | msi_data->irqhost->of_node); | |
87 | if (rc) | |
88 | return rc; | |
34e36c15 | 89 | |
7e7ab367 ME |
90 | rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap); |
91 | if (rc < 0) { | |
92 | msi_bitmap_free(&msi_data->bitmap); | |
93 | return rc; | |
34e36c15 JJ |
94 | } |
95 | ||
34e36c15 | 96 | return 0; |
34e36c15 JJ |
97 | } |
98 | ||
99 | static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type) | |
100 | { | |
101 | if (type == PCI_CAP_ID_MSIX) | |
102 | pr_debug("fslmsi: MSI-X untested, trying anyway.\n"); | |
103 | ||
104 | return 0; | |
105 | } | |
106 | ||
107 | static void fsl_teardown_msi_irqs(struct pci_dev *pdev) | |
108 | { | |
109 | struct msi_desc *entry; | |
80818813 | 110 | struct fsl_msi *msi_data; |
34e36c15 JJ |
111 | |
112 | list_for_each_entry(entry, &pdev->msi_list, list) { | |
113 | if (entry->irq == NO_IRQ) | |
114 | continue; | |
d1921bcd | 115 | msi_data = irq_get_chip_data(entry->irq); |
ec775d0e | 116 | irq_set_msi_desc(entry->irq, NULL); |
7e7ab367 ME |
117 | msi_bitmap_free_hwirqs(&msi_data->bitmap, |
118 | virq_to_hw(entry->irq), 1); | |
34e36c15 JJ |
119 | irq_dispose_mapping(entry->irq); |
120 | } | |
121 | ||
122 | return; | |
123 | } | |
124 | ||
125 | static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq, | |
80818813 LCB |
126 | struct msi_msg *msg, |
127 | struct fsl_msi *fsl_msi_data) | |
34e36c15 | 128 | { |
80818813 | 129 | struct fsl_msi *msi_data = fsl_msi_data; |
3da34aae | 130 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
2bcd1c0c TT |
131 | u64 address; /* Physical address of the MSIIR */ |
132 | int len; | |
133 | const u64 *reg; | |
134 | ||
135 | /* If the msi-address-64 property exists, then use it */ | |
136 | reg = of_get_property(hose->dn, "msi-address-64", &len); | |
137 | if (reg && (len == sizeof(u64))) | |
138 | address = be64_to_cpup(reg); | |
139 | else | |
140 | address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset; | |
34e36c15 | 141 | |
2bcd1c0c TT |
142 | msg->address_lo = lower_32_bits(address); |
143 | msg->address_hi = upper_32_bits(address); | |
3da34aae | 144 | |
34e36c15 JJ |
145 | msg->data = hwirq; |
146 | ||
147 | pr_debug("%s: allocated srs: %d, ibs: %d\n", | |
148 | __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG); | |
149 | } | |
150 | ||
151 | static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |
152 | { | |
895d603f TT |
153 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
154 | struct device_node *np; | |
155 | phandle phandle = 0; | |
694a7a36 | 156 | int rc, hwirq = -ENOMEM; |
34e36c15 JJ |
157 | unsigned int virq; |
158 | struct msi_desc *entry; | |
159 | struct msi_msg msg; | |
80818813 | 160 | struct fsl_msi *msi_data; |
34e36c15 | 161 | |
895d603f TT |
162 | /* |
163 | * If the PCI node has an fsl,msi property, then we need to use it | |
164 | * to find the specific MSI. | |
165 | */ | |
166 | np = of_parse_phandle(hose->dn, "fsl,msi", 0); | |
167 | if (np) { | |
446bc1ff TT |
168 | if (of_device_is_compatible(np, "fsl,mpic-msi") || |
169 | of_device_is_compatible(np, "fsl,vmpic-msi")) | |
895d603f TT |
170 | phandle = np->phandle; |
171 | else { | |
446bc1ff TT |
172 | dev_err(&pdev->dev, |
173 | "node %s has an invalid fsl,msi phandle %u\n", | |
174 | hose->dn->full_name, np->phandle); | |
895d603f TT |
175 | return -EINVAL; |
176 | } | |
177 | } | |
178 | ||
34e36c15 | 179 | list_for_each_entry(entry, &pdev->msi_list, list) { |
895d603f TT |
180 | /* |
181 | * Loop over all the MSI devices until we find one that has an | |
182 | * available interrupt. | |
183 | */ | |
694a7a36 | 184 | list_for_each_entry(msi_data, &msi_head, list) { |
895d603f TT |
185 | /* |
186 | * If the PCI node has an fsl,msi property, then we | |
187 | * restrict our search to the corresponding MSI node. | |
188 | * The simplest way is to skip over MSI nodes with the | |
189 | * wrong phandle. Under the Freescale hypervisor, this | |
190 | * has the additional benefit of skipping over MSI | |
191 | * nodes that are not mapped in the PAMU. | |
192 | */ | |
193 | if (phandle && (phandle != msi_data->phandle)) | |
194 | continue; | |
195 | ||
694a7a36 LY |
196 | hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1); |
197 | if (hwirq >= 0) | |
198 | break; | |
199 | } | |
80818813 | 200 | |
34e36c15 JJ |
201 | if (hwirq < 0) { |
202 | rc = hwirq; | |
446bc1ff | 203 | dev_err(&pdev->dev, "could not allocate MSI interrupt\n"); |
34e36c15 JJ |
204 | goto out_free; |
205 | } | |
206 | ||
207 | virq = irq_create_mapping(msi_data->irqhost, hwirq); | |
208 | ||
209 | if (virq == NO_IRQ) { | |
446bc1ff | 210 | dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq); |
7e7ab367 | 211 | msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1); |
34e36c15 JJ |
212 | rc = -ENOSPC; |
213 | goto out_free; | |
214 | } | |
d1921bcd | 215 | /* chip_data is msi_data via host->hostdata in host->map() */ |
ec775d0e | 216 | irq_set_msi_desc(virq, entry); |
34e36c15 | 217 | |
80818813 | 218 | fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data); |
34e36c15 JJ |
219 | write_msi_msg(virq, &msg); |
220 | } | |
221 | return 0; | |
222 | ||
223 | out_free: | |
694a7a36 | 224 | /* free by the caller of this function */ |
34e36c15 JJ |
225 | return rc; |
226 | } | |
227 | ||
692d1037 | 228 | static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) |
34e36c15 | 229 | { |
ddaedd1c TG |
230 | struct irq_chip *chip = irq_desc_get_chip(desc); |
231 | struct irq_data *idata = irq_desc_get_irq_data(desc); | |
34e36c15 | 232 | unsigned int cascade_irq; |
02adac60 | 233 | struct fsl_msi *msi_data; |
34e36c15 JJ |
234 | int msir_index = -1; |
235 | u32 msir_value = 0; | |
236 | u32 intr_index; | |
237 | u32 have_shift = 0; | |
02adac60 LY |
238 | struct fsl_msi_cascade_data *cascade_data; |
239 | ||
d1921bcd | 240 | cascade_data = irq_get_handler_data(irq); |
02adac60 | 241 | msi_data = cascade_data->msi_data; |
34e36c15 | 242 | |
239007b8 | 243 | raw_spin_lock(&desc->lock); |
34e36c15 | 244 | if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { |
37e16615 | 245 | if (chip->irq_mask_ack) |
ddaedd1c | 246 | chip->irq_mask_ack(idata); |
34e36c15 | 247 | else { |
ddaedd1c TG |
248 | chip->irq_mask(idata); |
249 | chip->irq_ack(idata); | |
34e36c15 JJ |
250 | } |
251 | } | |
252 | ||
ddaedd1c | 253 | if (unlikely(irqd_irq_inprogress(idata))) |
34e36c15 JJ |
254 | goto unlock; |
255 | ||
02adac60 | 256 | msir_index = cascade_data->index; |
34e36c15 JJ |
257 | |
258 | if (msir_index >= NR_MSI_REG) | |
259 | cascade_irq = NO_IRQ; | |
260 | ||
ddaedd1c | 261 | irqd_set_chained_irq_inprogress(idata); |
80818813 | 262 | switch (msi_data->feature & FSL_PIC_IP_MASK) { |
34e36c15 JJ |
263 | case FSL_PIC_IP_MPIC: |
264 | msir_value = fsl_msi_read(msi_data->msi_regs, | |
265 | msir_index * 0x10); | |
266 | break; | |
267 | case FSL_PIC_IP_IPIC: | |
268 | msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4); | |
269 | break; | |
305bcf26 SW |
270 | #ifdef CONFIG_EPAPR_PARAVIRT |
271 | case FSL_PIC_IP_VMPIC: { | |
272 | unsigned int ret; | |
446bc1ff TT |
273 | ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value); |
274 | if (ret) { | |
275 | pr_err("fsl-msi: fh_vmpic_get_msir() failed for " | |
276 | "irq %u (ret=%u)\n", irq, ret); | |
277 | msir_value = 0; | |
278 | } | |
279 | break; | |
34e36c15 | 280 | } |
305bcf26 SW |
281 | #endif |
282 | } | |
34e36c15 JJ |
283 | |
284 | while (msir_value) { | |
285 | intr_index = ffs(msir_value) - 1; | |
286 | ||
287 | cascade_irq = irq_linear_revmap(msi_data->irqhost, | |
692d1037 AV |
288 | msir_index * IRQS_PER_MSI_REG + |
289 | intr_index + have_shift); | |
34e36c15 JJ |
290 | if (cascade_irq != NO_IRQ) |
291 | generic_handle_irq(cascade_irq); | |
692d1037 AV |
292 | have_shift += intr_index + 1; |
293 | msir_value = msir_value >> (intr_index + 1); | |
34e36c15 | 294 | } |
ddaedd1c | 295 | irqd_clr_chained_irq_inprogress(idata); |
34e36c15 JJ |
296 | |
297 | switch (msi_data->feature & FSL_PIC_IP_MASK) { | |
298 | case FSL_PIC_IP_MPIC: | |
446bc1ff | 299 | case FSL_PIC_IP_VMPIC: |
ddaedd1c | 300 | chip->irq_eoi(idata); |
34e36c15 JJ |
301 | break; |
302 | case FSL_PIC_IP_IPIC: | |
ddaedd1c TG |
303 | if (!irqd_irq_disabled(idata) && chip->irq_unmask) |
304 | chip->irq_unmask(idata); | |
34e36c15 JJ |
305 | break; |
306 | } | |
307 | unlock: | |
239007b8 | 308 | raw_spin_unlock(&desc->lock); |
34e36c15 JJ |
309 | } |
310 | ||
a454dc50 | 311 | static int fsl_of_msi_remove(struct platform_device *ofdev) |
48059993 | 312 | { |
6c4c82e2 | 313 | struct fsl_msi *msi = platform_get_drvdata(ofdev); |
48059993 LY |
314 | int virq, i; |
315 | struct fsl_msi_cascade_data *cascade_data; | |
316 | ||
317 | if (msi->list.prev != NULL) | |
318 | list_del(&msi->list); | |
319 | for (i = 0; i < NR_MSI_REG; i++) { | |
320 | virq = msi->msi_virqs[i]; | |
321 | if (virq != NO_IRQ) { | |
ec775d0e | 322 | cascade_data = irq_get_handler_data(virq); |
48059993 LY |
323 | kfree(cascade_data); |
324 | irq_dispose_mapping(virq); | |
325 | } | |
326 | } | |
327 | if (msi->bitmap.bitmap) | |
328 | msi_bitmap_free(&msi->bitmap); | |
446bc1ff TT |
329 | if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) |
330 | iounmap(msi->msi_regs); | |
48059993 LY |
331 | kfree(msi); |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
cad5cef6 GKH |
336 | static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev, |
337 | int offset, int irq_index) | |
6820fead SW |
338 | { |
339 | struct fsl_msi_cascade_data *cascade_data = NULL; | |
340 | int virt_msir; | |
341 | ||
342 | virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index); | |
343 | if (virt_msir == NO_IRQ) { | |
344 | dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n", | |
345 | __func__, irq_index); | |
346 | return 0; | |
347 | } | |
348 | ||
349 | cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL); | |
350 | if (!cascade_data) { | |
351 | dev_err(&dev->dev, "No memory for MSI cascade data\n"); | |
352 | return -ENOMEM; | |
353 | } | |
354 | ||
355 | msi->msi_virqs[irq_index] = virt_msir; | |
22285118 | 356 | cascade_data->index = offset; |
6820fead | 357 | cascade_data->msi_data = msi; |
ec775d0e TG |
358 | irq_set_handler_data(virt_msir, cascade_data); |
359 | irq_set_chained_handler(virt_msir, fsl_msi_cascade); | |
6820fead SW |
360 | |
361 | return 0; | |
362 | } | |
363 | ||
b1608d69 | 364 | static const struct of_device_id fsl_of_msi_ids[]; |
cad5cef6 | 365 | static int fsl_of_msi_probe(struct platform_device *dev) |
34e36c15 | 366 | { |
b1608d69 | 367 | const struct of_device_id *match; |
34e36c15 JJ |
368 | struct fsl_msi *msi; |
369 | struct resource res; | |
6820fead | 370 | int err, i, j, irq_index, count; |
34e36c15 | 371 | int rc; |
34e36c15 | 372 | const u32 *p; |
f318f1d7 | 373 | const struct fsl_msi_feature *features; |
061ca4ad LY |
374 | int len; |
375 | u32 offset; | |
6820fead | 376 | static const u32 all_avail[] = { 0, NR_MSI_IRQS }; |
34e36c15 | 377 | |
b1608d69 GL |
378 | match = of_match_device(fsl_of_msi_ids, &dev->dev); |
379 | if (!match) | |
00006124 | 380 | return -EINVAL; |
b1608d69 | 381 | features = match->data; |
00006124 | 382 | |
34e36c15 JJ |
383 | printk(KERN_DEBUG "Setting up Freescale MSI support\n"); |
384 | ||
385 | msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL); | |
386 | if (!msi) { | |
387 | dev_err(&dev->dev, "No memory for MSI structure\n"); | |
48059993 | 388 | return -ENOMEM; |
34e36c15 | 389 | } |
6c4c82e2 | 390 | platform_set_drvdata(dev, msi); |
34e36c15 | 391 | |
a8db8cf0 GL |
392 | msi->irqhost = irq_domain_add_linear(dev->dev.of_node, |
393 | NR_MSI_IRQS, &fsl_msi_host_ops, msi); | |
34e36c15 | 394 | |
34e36c15 JJ |
395 | if (msi->irqhost == NULL) { |
396 | dev_err(&dev->dev, "No memory for MSI irqhost\n"); | |
34e36c15 JJ |
397 | err = -ENOMEM; |
398 | goto error_out; | |
399 | } | |
400 | ||
446bc1ff TT |
401 | /* |
402 | * Under the Freescale hypervisor, the msi nodes don't have a 'reg' | |
403 | * property. Instead, we use hypercalls to access the MSI. | |
404 | */ | |
405 | if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) { | |
406 | err = of_address_to_resource(dev->dev.of_node, 0, &res); | |
407 | if (err) { | |
408 | dev_err(&dev->dev, "invalid resource for node %s\n", | |
61c7a080 | 409 | dev->dev.of_node->full_name); |
446bc1ff TT |
410 | goto error_out; |
411 | } | |
34e36c15 | 412 | |
446bc1ff TT |
413 | msi->msi_regs = ioremap(res.start, resource_size(&res)); |
414 | if (!msi->msi_regs) { | |
b53804c7 | 415 | err = -ENOMEM; |
446bc1ff TT |
416 | dev_err(&dev->dev, "could not map node %s\n", |
417 | dev->dev.of_node->full_name); | |
418 | goto error_out; | |
419 | } | |
420 | msi->msiir_offset = | |
421 | features->msiir_offset + (res.start & 0xfffff); | |
34e36c15 JJ |
422 | } |
423 | ||
692d1037 | 424 | msi->feature = features->fsl_pic_ip; |
34e36c15 | 425 | |
895d603f TT |
426 | /* |
427 | * Remember the phandle, so that we can match with any PCI nodes | |
428 | * that have an "fsl,msi" property. | |
429 | */ | |
430 | msi->phandle = dev->dev.of_node->phandle; | |
431 | ||
34e36c15 JJ |
432 | rc = fsl_msi_init_allocator(msi); |
433 | if (rc) { | |
434 | dev_err(&dev->dev, "Error allocating MSI bitmap\n"); | |
435 | goto error_out; | |
436 | } | |
437 | ||
6820fead SW |
438 | p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len); |
439 | if (p && len % (2 * sizeof(u32)) != 0) { | |
440 | dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n", | |
441 | __func__); | |
34e36c15 JJ |
442 | err = -EINVAL; |
443 | goto error_out; | |
444 | } | |
6820fead | 445 | |
22285118 | 446 | if (!p) { |
6820fead | 447 | p = all_avail; |
22285118 TT |
448 | len = sizeof(all_avail); |
449 | } | |
6820fead SW |
450 | |
451 | for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) { | |
452 | if (p[i * 2] % IRQS_PER_MSI_REG || | |
453 | p[i * 2 + 1] % IRQS_PER_MSI_REG) { | |
454 | printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n", | |
455 | __func__, dev->dev.of_node->full_name, | |
456 | p[i * 2 + 1], p[i * 2]); | |
457 | err = -EINVAL; | |
458 | goto error_out; | |
459 | } | |
460 | ||
461 | offset = p[i * 2] / IRQS_PER_MSI_REG; | |
462 | count = p[i * 2 + 1] / IRQS_PER_MSI_REG; | |
463 | ||
464 | for (j = 0; j < count; j++, irq_index++) { | |
22285118 | 465 | err = fsl_msi_setup_hwirq(msi, dev, offset + j, irq_index); |
6820fead | 466 | if (err) |
02adac60 | 467 | goto error_out; |
34e36c15 JJ |
468 | } |
469 | } | |
470 | ||
694a7a36 | 471 | list_add_tail(&msi->list, &msi_head); |
34e36c15 | 472 | |
80818813 LCB |
473 | /* The multiple setting ppc_md.setup_msi_irqs will not harm things */ |
474 | if (!ppc_md.setup_msi_irqs) { | |
475 | ppc_md.setup_msi_irqs = fsl_setup_msi_irqs; | |
476 | ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs; | |
477 | ppc_md.msi_check_device = fsl_msi_check_device; | |
478 | } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) { | |
479 | dev_err(&dev->dev, "Different MSI driver already installed!\n"); | |
480 | err = -ENODEV; | |
481 | goto error_out; | |
482 | } | |
34e36c15 JJ |
483 | return 0; |
484 | error_out: | |
48059993 | 485 | fsl_of_msi_remove(dev); |
34e36c15 JJ |
486 | return err; |
487 | } | |
488 | ||
489 | static const struct fsl_msi_feature mpic_msi_feature = { | |
490 | .fsl_pic_ip = FSL_PIC_IP_MPIC, | |
491 | .msiir_offset = 0x140, | |
492 | }; | |
493 | ||
494 | static const struct fsl_msi_feature ipic_msi_feature = { | |
495 | .fsl_pic_ip = FSL_PIC_IP_IPIC, | |
496 | .msiir_offset = 0x38, | |
497 | }; | |
498 | ||
446bc1ff TT |
499 | static const struct fsl_msi_feature vmpic_msi_feature = { |
500 | .fsl_pic_ip = FSL_PIC_IP_VMPIC, | |
501 | .msiir_offset = 0, | |
502 | }; | |
503 | ||
34e36c15 JJ |
504 | static const struct of_device_id fsl_of_msi_ids[] = { |
505 | { | |
506 | .compatible = "fsl,mpic-msi", | |
a99cc82b | 507 | .data = &mpic_msi_feature, |
34e36c15 JJ |
508 | }, |
509 | { | |
510 | .compatible = "fsl,ipic-msi", | |
a99cc82b | 511 | .data = &ipic_msi_feature, |
34e36c15 | 512 | }, |
305bcf26 | 513 | #ifdef CONFIG_EPAPR_PARAVIRT |
446bc1ff TT |
514 | { |
515 | .compatible = "fsl,vmpic-msi", | |
a99cc82b | 516 | .data = &vmpic_msi_feature, |
446bc1ff | 517 | }, |
305bcf26 | 518 | #endif |
34e36c15 JJ |
519 | {} |
520 | }; | |
521 | ||
00006124 | 522 | static struct platform_driver fsl_of_msi_driver = { |
4018294b GL |
523 | .driver = { |
524 | .name = "fsl-msi", | |
525 | .owner = THIS_MODULE, | |
526 | .of_match_table = fsl_of_msi_ids, | |
527 | }, | |
34e36c15 | 528 | .probe = fsl_of_msi_probe, |
48059993 | 529 | .remove = fsl_of_msi_remove, |
34e36c15 JJ |
530 | }; |
531 | ||
532 | static __init int fsl_of_msi_init(void) | |
533 | { | |
00006124 | 534 | return platform_driver_register(&fsl_of_msi_driver); |
34e36c15 JJ |
535 | } |
536 | ||
537 | subsys_initcall(fsl_of_msi_init); |