[linux-2.6-block.git] / arch / powerpc / sysdev / fsl_msi.c

/*
 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
 *
 * Author: Tony Li <tony.li@freescale.com>
 *	   Jason Jin <Jason.jin@freescale.com>
 *
 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2 of the
 * License.
 *
 */
#include <linux/irq.h>
#include <linux/bootmem.h>
#include <linux/msi.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
#include <asm/prom.h>
#include <asm/hw_irq.h>
#include <asm/ppc-pci.h>
#include <asm/mpic.h>
#include <asm/fsl_hcalls.h>

#include "fsl_msi.h"
#include "fsl_pci.h"

#define MSIIR_OFFSET_MASK	0xfffff
#define MSIIR_IBS_SHIFT		0
#define MSIIR_SRS_SHIFT		5
#define MSIIR1_IBS_SHIFT	4
#define MSIIR1_SRS_SHIFT	0
#define MSI_SRS_MASK		0xf
#define MSI_IBS_MASK		0x1f

#define msi_hwirq(msi, msir_index, intr_index) \
		((msir_index) << (msi)->srs_shift | \
		 ((intr_index) << (msi)->ibs_shift))

static LIST_HEAD(msi_head);

struct fsl_msi_feature {
	u32 fsl_pic_ip;
	u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
};

struct fsl_msi_cascade_data {
	struct fsl_msi *msi_data;
	int index;
};

static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
{
	return in_be32(base + (reg >> 2));
}

/*
 * We do not need this actually. The MSIR register has been read once
 * in the cascade interrupt. So, this MSI interrupt has been acked
*/
static void fsl_msi_end_irq(struct irq_data *d)
{
}

static struct irq_chip fsl_msi_chip = {
	.irq_mask	= mask_msi_irq,
	.irq_unmask	= unmask_msi_irq,
	.irq_ack	= fsl_msi_end_irq,
	.name		= "FSL-MSI",
};

static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
				irq_hw_number_t hw)
{
	struct fsl_msi *msi_data = h->host_data;
	struct irq_chip *chip = &fsl_msi_chip;

	irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);

	irq_set_chip_data(virq, msi_data);
	irq_set_chip_and_handler(virq, chip, handle_edge_irq);

	return 0;
}

static const struct irq_domain_ops fsl_msi_host_ops = {
	.map = fsl_msi_host_map,
};

static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
{
	int rc, hwirq;

	rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
			      msi_data->irqhost->of_node);
	if (rc)
		return rc;

	/*
	 * Reserve all the hwirqs
	 * The available hwirqs will be released in fsl_msi_setup_hwirq()
	 */
	for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
		msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);

	return 0;
}

static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
{
	if (type == PCI_CAP_ID_MSIX)
		pr_debug("fslmsi: MSI-X untested, trying anyway.\n");

	return 0;
}

static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
{
	struct msi_desc *entry;
	struct fsl_msi *msi_data;

	list_for_each_entry(entry, &pdev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;
		msi_data = irq_get_chip_data(entry->irq);
		irq_set_msi_desc(entry->irq, NULL);
		msi_bitmap_free_hwirqs(&msi_data->bitmap,
				       virq_to_hw(entry->irq), 1);
		irq_dispose_mapping(entry->irq);
	}

	return;
}

static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
				struct msi_msg *msg,
				struct fsl_msi *fsl_msi_data)
{
	struct fsl_msi *msi_data = fsl_msi_data;
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	u64 address; /* Physical address of the MSIIR */
	int len;
	const __be64 *reg;

	/* If the msi-address-64 property exists, then use it */
	reg = of_get_property(hose->dn, "msi-address-64", &len);
	if (reg && (len == sizeof(u64)))
		address = be64_to_cpup(reg);
	else
		address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;

	msg->address_lo = lower_32_bits(address);
	msg->address_hi = upper_32_bits(address);

	msg->data = hwirq;

	pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
		 (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
		 (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
}

static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
{
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	struct device_node *np;
	phandle phandle = 0;
	int rc, hwirq = -ENOMEM;
	unsigned int virq;
	struct msi_desc *entry;
	struct msi_msg msg;
	struct fsl_msi *msi_data;

	/*
	 * If the PCI node has an fsl,msi property, then we need to use it
	 * to find the specific MSI.
	 */
	np = of_parse_phandle(hose->dn, "fsl,msi", 0);
	if (np) {
		if (of_device_is_compatible(np, "fsl,mpic-msi") ||
		    of_device_is_compatible(np, "fsl,vmpic-msi"))
			phandle = np->phandle;
		else {
			dev_err(&pdev->dev,
				"node %s has an invalid fsl,msi phandle %u\n",
				hose->dn->full_name, np->phandle);
			return -EINVAL;
		}
	}

	list_for_each_entry(entry, &pdev->msi_list, list) {
		/*
		 * Loop over all the MSI devices until we find one that has an
		 * available interrupt.
		 */
		list_for_each_entry(msi_data, &msi_head, list) {
			/*
			 * If the PCI node has an fsl,msi property, then we
			 * restrict our search to the corresponding MSI node.
			 * The simplest way is to skip over MSI nodes with the
			 * wrong phandle. Under the Freescale hypervisor, this
			 * has the additional benefit of skipping over MSI
			 * nodes that are not mapped in the PAMU.
			 */
			if (phandle && (phandle != msi_data->phandle))
				continue;

			hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
			if (hwirq >= 0)
				break;
		}

		if (hwirq < 0) {
			rc = hwirq;
			dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
			goto out_free;
		}

		virq = irq_create_mapping(msi_data->irqhost, hwirq);

		if (virq == NO_IRQ) {
			dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
			msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
			rc = -ENOSPC;
			goto out_free;
		}
		/* chip_data is msi_data via host->hostdata in host->map() */
		irq_set_msi_desc(virq, entry);

		fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
		write_msi_msg(virq, &msg);
	}
	return 0;

out_free:
	/* free by the caller of this function */
	return rc;
}

static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct irq_data *idata = irq_desc_get_irq_data(desc);
	unsigned int cascade_irq;
	struct fsl_msi *msi_data;
	int msir_index = -1;
	u32 msir_value = 0;
	u32 intr_index;
	u32 have_shift = 0;
	struct fsl_msi_cascade_data *cascade_data;

	cascade_data = irq_get_handler_data(irq);
	msi_data = cascade_data->msi_data;

	raw_spin_lock(&desc->lock);
	if ((msi_data->feature &  FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
		if (chip->irq_mask_ack)
			chip->irq_mask_ack(idata);
		else {
			chip->irq_mask(idata);
			chip->irq_ack(idata);
		}
	}

	if (unlikely(irqd_irq_inprogress(idata)))
		goto unlock;

	msir_index = cascade_data->index;

	if (msir_index >= NR_MSI_REG_MAX)
		cascade_irq = NO_IRQ;

	irqd_set_chained_irq_inprogress(idata);
	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	case FSL_PIC_IP_MPIC:
		msir_value = fsl_msi_read(msi_data->msi_regs,
			msir_index * 0x10);
		break;
	case FSL_PIC_IP_IPIC:
		msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
		break;
#ifdef CONFIG_EPAPR_PARAVIRT
	case FSL_PIC_IP_VMPIC: {
		unsigned int ret;
		ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
		if (ret) {
			pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
			       "irq %u (ret=%u)\n", irq, ret);
			msir_value = 0;
		}
		break;
	}
#endif
	}

	while (msir_value) {
		intr_index = ffs(msir_value) - 1;

		cascade_irq = irq_linear_revmap(msi_data->irqhost,
				msi_hwirq(msi_data, msir_index,
					  intr_index + have_shift));
		if (cascade_irq != NO_IRQ)
			generic_handle_irq(cascade_irq);
		have_shift += intr_index + 1;
		msir_value = msir_value >> (intr_index + 1);
	}
	irqd_clr_chained_irq_inprogress(idata);

	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	case FSL_PIC_IP_MPIC:
	case FSL_PIC_IP_VMPIC:
		chip->irq_eoi(idata);
		break;
	case FSL_PIC_IP_IPIC:
		if (!irqd_irq_disabled(idata) && chip->irq_unmask)
			chip->irq_unmask(idata);
		break;
	}
unlock:
	raw_spin_unlock(&desc->lock);
}

static int fsl_of_msi_remove(struct platform_device *ofdev)
{
	struct fsl_msi *msi = platform_get_drvdata(ofdev);
	int virq, i;
	struct fsl_msi_cascade_data *cascade_data;

	if (msi->list.prev != NULL)
		list_del(&msi->list);
	for (i = 0; i < NR_MSI_REG_MAX; i++) {
		virq = msi->msi_virqs[i];
		if (virq != NO_IRQ) {
			cascade_data = irq_get_handler_data(virq);
			kfree(cascade_data);
			irq_dispose_mapping(virq);
		}
	}
	if (msi->bitmap.bitmap)
		msi_bitmap_free(&msi->bitmap);
	if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
		iounmap(msi->msi_regs);
	kfree(msi);

	return 0;
}

static struct lock_class_key fsl_msi_irq_class;

static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
			       int offset, int irq_index)
{
	struct fsl_msi_cascade_data *cascade_data = NULL;
	int virt_msir, i;

	virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
	if (virt_msir == NO_IRQ) {
		dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
			__func__, irq_index);
		return 0;
	}

	cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
	if (!cascade_data) {
		dev_err(&dev->dev, "No memory for MSI cascade data\n");
		return -ENOMEM;
	}
	irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
	msi->msi_virqs[irq_index] = virt_msir;
	cascade_data->index = offset;
	cascade_data->msi_data = msi;
	irq_set_handler_data(virt_msir, cascade_data);
	irq_set_chained_handler(virt_msir, fsl_msi_cascade);

	/* Release the hwirqs corresponding to this MSI register */
	for (i = 0; i < IRQS_PER_MSI_REG; i++)
		msi_bitmap_free_hwirqs(&msi->bitmap,
				       msi_hwirq(msi, offset, i), 1);

	return 0;
}

static const struct of_device_id fsl_of_msi_ids[];
static int fsl_of_msi_probe(struct platform_device *dev)
{
	const struct of_device_id *match;
	struct fsl_msi *msi;
	struct resource res, msiir;
	int err, i, j, irq_index, count;
	const u32 *p;
	const struct fsl_msi_feature *features;
	int len;
	u32 offset;

	match = of_match_device(fsl_of_msi_ids, &dev->dev);
	if (!match)
		return -EINVAL;
	features = match->data;

	printk(KERN_DEBUG "Setting up Freescale MSI support\n");

	msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
	if (!msi) {
		dev_err(&dev->dev, "No memory for MSI structure\n");
		return -ENOMEM;
	}
	platform_set_drvdata(dev, msi);

	msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
				      NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);

	if (msi->irqhost == NULL) {
		dev_err(&dev->dev, "No memory for MSI irqhost\n");
		err = -ENOMEM;
		goto error_out;
	}

	/*
	 * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
	 * property.  Instead, we use hypercalls to access the MSI.
	 */
	if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
		err = of_address_to_resource(dev->dev.of_node, 0, &res);
		if (err) {
			dev_err(&dev->dev, "invalid resource for node %s\n",
				dev->dev.of_node->full_name);
			goto error_out;
		}

		msi->msi_regs = ioremap(res.start, resource_size(&res));
		if (!msi->msi_regs) {
			err = -ENOMEM;
			dev_err(&dev->dev, "could not map node %s\n",
				dev->dev.of_node->full_name);
			goto error_out;
		}
		msi->msiir_offset =
			features->msiir_offset + (res.start & 0xfffff);

		/*
		 * First read the MSIIR/MSIIR1 offset from dts
		 * On failure use the hardcode MSIIR offset
		 */
		if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
			msi->msiir_offset = features->msiir_offset +
					    (res.start & MSIIR_OFFSET_MASK);
		else
			msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
	}

	msi->feature = features->fsl_pic_ip;

	/*
	 * Remember the phandle, so that we can match with any PCI nodes
	 * that have an "fsl,msi" property.
	 */
	msi->phandle = dev->dev.of_node->phandle;

	err = fsl_msi_init_allocator(msi);
	if (err) {
		dev_err(&dev->dev, "Error allocating MSI bitmap\n");
		goto error_out;
	}

	p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);

	if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3")) {
		msi->srs_shift = MSIIR1_SRS_SHIFT;
		msi->ibs_shift = MSIIR1_IBS_SHIFT;
		if (p)
			dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
				__func__);

		for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
		     irq_index++) {
			err = fsl_msi_setup_hwirq(msi, dev,
						  irq_index, irq_index);
			if (err)
				goto error_out;
		}
	} else {
		static const u32 all_avail[] =
			{ 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };

		msi->srs_shift = MSIIR_SRS_SHIFT;
		msi->ibs_shift = MSIIR_IBS_SHIFT;

		if (p && len % (2 * sizeof(u32)) != 0) {
			dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
				__func__);
			err = -EINVAL;
			goto error_out;
		}

		if (!p) {
			p = all_avail;
			len = sizeof(all_avail);
		}

		for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
			if (p[i * 2] % IRQS_PER_MSI_REG ||
			    p[i * 2 + 1] % IRQS_PER_MSI_REG) {
				pr_warn("%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
				       __func__, dev->dev.of_node->full_name,
				       p[i * 2 + 1], p[i * 2]);
				err = -EINVAL;
				goto error_out;
			}

			offset = p[i * 2] / IRQS_PER_MSI_REG;
			count = p[i * 2 + 1] / IRQS_PER_MSI_REG;

			for (j = 0; j < count; j++, irq_index++) {
				err = fsl_msi_setup_hwirq(msi, dev, offset + j,
							  irq_index);
				if (err)
					goto error_out;
			}
		}
	}

	list_add_tail(&msi->list, &msi_head);

	/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
	if (!ppc_md.setup_msi_irqs) {
		ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
		ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
		ppc_md.msi_check_device = fsl_msi_check_device;
	} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
		dev_err(&dev->dev, "Different MSI driver already installed!\n");
		err = -ENODEV;
		goto error_out;
	}
	return 0;
error_out:
	fsl_of_msi_remove(dev);
	return err;
}

static const struct fsl_msi_feature mpic_msi_feature = {
	.fsl_pic_ip = FSL_PIC_IP_MPIC,
	.msiir_offset = 0x140,
};

static const struct fsl_msi_feature ipic_msi_feature = {
	.fsl_pic_ip = FSL_PIC_IP_IPIC,
	.msiir_offset = 0x38,
};

static const struct fsl_msi_feature vmpic_msi_feature = {
	.fsl_pic_ip = FSL_PIC_IP_VMPIC,
	.msiir_offset = 0,
};

static const struct of_device_id fsl_of_msi_ids[] = {
	{
		.compatible = "fsl,mpic-msi",
		.data = &mpic_msi_feature,
	},
	{
		.compatible = "fsl,mpic-msi-v4.3",
		.data = &mpic_msi_feature,
	},
	{
		.compatible = "fsl,ipic-msi",
		.data = &ipic_msi_feature,
	},
#ifdef CONFIG_EPAPR_PARAVIRT
	{
		.compatible = "fsl,vmpic-msi",
		.data = &vmpic_msi_feature,
	},
#endif
	{}
};

static struct platform_driver fsl_of_msi_driver = {
	.driver = {
		.name = "fsl-msi",
		.owner = THIS_MODULE,
		.of_match_table = fsl_of_msi_ids,
	},
	.probe = fsl_of_msi_probe,
	.remove = fsl_of_msi_remove,
};

static __init int fsl_of_msi_init(void)
{
	return platform_driver_register(&fsl_of_msi_driver);
}

subsys_initcall(fsl_of_msi_init);
Commit	Line	Data
34e36c15	1	/*
6820fead	2	* Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
34e36c15 JJ	3	*
	4	* Author: Tony Li <tony.li@freescale.com>
	5	* Jason Jin <Jason.jin@freescale.com>
	6	*
	7	* The hwirq alloc and free code reuse from sysdev/mpic_msi.c
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; version 2 of the
	12	* License.
	13	*
	14	*/
	15	#include <linux/irq.h>
	16	#include <linux/bootmem.h>
34e36c15 JJ	17	#include <linux/msi.h>
34e36c15 JJ	18	#include <linux/pci.h>
5a0e3ad6	19	#include <linux/slab.h>
34e36c15 JJ	20	#include <linux/of_platform.h>
	21	#include <sysdev/fsl_soc.h>
	22	#include <asm/prom.h>
	23	#include <asm/hw_irq.h>
	24	#include <asm/ppc-pci.h>
02adac60	25	#include <asm/mpic.h>
446bc1ff TT	26	#include <asm/fsl_hcalls.h>
446bc1ff TT	27
34e36c15	28	#include "fsl_msi.h"
b8f44ec2	29	#include "fsl_pci.h"
34e36c15	30
f31dd944 ML	31	#define MSIIR_OFFSET_MASK 0xfffff
	32	#define MSIIR_IBS_SHIFT 0
	33	#define MSIIR_SRS_SHIFT 5
	34	#define MSIIR1_IBS_SHIFT 4
	35	#define MSIIR1_SRS_SHIFT 0
	36	#define MSI_SRS_MASK 0xf
	37	#define MSI_IBS_MASK 0x1f
	38
	39	#define msi_hwirq(msi, msir_index, intr_index) \
	40	((msir_index) << (msi)->srs_shift \| \
	41	((intr_index) << (msi)->ibs_shift))
	42
6cce76dc	43	static LIST_HEAD(msi_head);
694a7a36	44
34e36c15 JJ	45	struct fsl_msi_feature {
34e36c15 JJ	46	u32 fsl_pic_ip;
2bcd1c0c	47	u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
34e36c15 JJ	48	};
34e36c15 JJ	49
02adac60 LY	50	struct fsl_msi_cascade_data {
	51	struct fsl_msi *msi_data;
	52	int index;
	53	};
34e36c15 JJ	54
	55	static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
	56	{
	57	return in_be32(base + (reg >> 2));
	58	}
	59
34e36c15 JJ	60	/*
	61	* We do not need this actually. The MSIR register has been read once
	62	* in the cascade interrupt. So, this MSI interrupt has been acked
	63	*/
37e16615	64	static void fsl_msi_end_irq(struct irq_data *d)
34e36c15 JJ	65	{
	66	}
	67
	68	static struct irq_chip fsl_msi_chip = {
1c9db525 TG	69	.irq_mask = mask_msi_irq,
1c9db525 TG	70	.irq_unmask = unmask_msi_irq,
37e16615	71	.irq_ack = fsl_msi_end_irq,
fc380c0c	72	.name = "FSL-MSI",
34e36c15 JJ	73	};
34e36c15 JJ	74
bae1d8f1	75	static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
34e36c15 JJ	76	irq_hw_number_t hw)
34e36c15 JJ	77	{
80818813	78	struct fsl_msi *msi_data = h->host_data;
34e36c15 JJ	79	struct irq_chip *chip = &fsl_msi_chip;
34e36c15 JJ	80
98488db9	81	irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
34e36c15	82
ec775d0e TG	83	irq_set_chip_data(virq, msi_data);
ec775d0e TG	84	irq_set_chip_and_handler(virq, chip, handle_edge_irq);
34e36c15 JJ	85
	86	return 0;
	87	}
	88
9f70b8eb	89	static const struct irq_domain_ops fsl_msi_host_ops = {
34e36c15 JJ	90	.map = fsl_msi_host_map,
	91	};
	92
34e36c15 JJ	93	static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
34e36c15 JJ	94	{
f31dd944	95	int rc, hwirq;
34e36c15	96
f31dd944	97	rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
7e7ab367 ME	98	msi_data->irqhost->of_node);
	99	if (rc)
	100	return rc;
34e36c15	101
f31dd944 ML	102	/*
	103	* Reserve all the hwirqs
	104	* The available hwirqs will be released in fsl_msi_setup_hwirq()
	105	*/
	106	for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
	107	msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
34e36c15	108
34e36c15	109	return 0;
34e36c15 JJ	110	}
	111
	112	static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
	113	{
	114	if (type == PCI_CAP_ID_MSIX)
	115	pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
	116
	117	return 0;
	118	}
	119
	120	static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
	121	{
	122	struct msi_desc *entry;
80818813	123	struct fsl_msi *msi_data;
34e36c15 JJ	124
	125	list_for_each_entry(entry, &pdev->msi_list, list) {
	126	if (entry->irq == NO_IRQ)
	127	continue;
d1921bcd	128	msi_data = irq_get_chip_data(entry->irq);
ec775d0e	129	irq_set_msi_desc(entry->irq, NULL);
7e7ab367 ME	130	msi_bitmap_free_hwirqs(&msi_data->bitmap,
7e7ab367 ME	131	virq_to_hw(entry->irq), 1);
34e36c15 JJ	132	irq_dispose_mapping(entry->irq);
	133	}
	134
	135	return;
	136	}
	137
	138	static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
80818813 LCB	139	struct msi_msg *msg,
80818813 LCB	140	struct fsl_msi *fsl_msi_data)
34e36c15	141	{
80818813	142	struct fsl_msi *msi_data = fsl_msi_data;
3da34aae	143	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2bcd1c0c TT	144	u64 address; /* Physical address of the MSIIR */
2bcd1c0c TT	145	int len;
6cce76dc	146	const __be64 *reg;
2bcd1c0c TT	147
	148	/* If the msi-address-64 property exists, then use it */
	149	reg = of_get_property(hose->dn, "msi-address-64", &len);
	150	if (reg && (len == sizeof(u64)))
	151	address = be64_to_cpup(reg);
	152	else
	153	address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
34e36c15	154
2bcd1c0c TT	155	msg->address_lo = lower_32_bits(address);
2bcd1c0c TT	156	msg->address_hi = upper_32_bits(address);
3da34aae	157
34e36c15 JJ	158	msg->data = hwirq;
34e36c15 JJ	159
f31dd944 ML	160	pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
	161	(hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
	162	(hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
34e36c15 JJ	163	}
	164
	165	static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
	166	{
895d603f TT	167	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	168	struct device_node *np;
	169	phandle phandle = 0;
694a7a36	170	int rc, hwirq = -ENOMEM;
34e36c15 JJ	171	unsigned int virq;
	172	struct msi_desc *entry;
	173	struct msi_msg msg;
80818813	174	struct fsl_msi *msi_data;
34e36c15	175
895d603f TT	176	/*
	177	* If the PCI node has an fsl,msi property, then we need to use it
	178	* to find the specific MSI.
	179	*/
	180	np = of_parse_phandle(hose->dn, "fsl,msi", 0);
	181	if (np) {
446bc1ff TT	182	if (of_device_is_compatible(np, "fsl,mpic-msi") \|\|
446bc1ff TT	183	of_device_is_compatible(np, "fsl,vmpic-msi"))
895d603f TT	184	phandle = np->phandle;
895d603f TT	185	else {
446bc1ff TT	186	dev_err(&pdev->dev,
	187	"node %s has an invalid fsl,msi phandle %u\n",
	188	hose->dn->full_name, np->phandle);
895d603f TT	189	return -EINVAL;
	190	}
	191	}
	192
34e36c15	193	list_for_each_entry(entry, &pdev->msi_list, list) {
895d603f TT	194	/*
	195	* Loop over all the MSI devices until we find one that has an
	196	* available interrupt.
	197	*/
694a7a36	198	list_for_each_entry(msi_data, &msi_head, list) {
895d603f TT	199	/*
	200	* If the PCI node has an fsl,msi property, then we
	201	* restrict our search to the corresponding MSI node.
	202	* The simplest way is to skip over MSI nodes with the
	203	* wrong phandle. Under the Freescale hypervisor, this
	204	* has the additional benefit of skipping over MSI
	205	* nodes that are not mapped in the PAMU.
	206	*/
	207	if (phandle && (phandle != msi_data->phandle))
	208	continue;
	209
694a7a36 LY	210	hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
	211	if (hwirq >= 0)
	212	break;
	213	}
80818813	214
34e36c15 JJ	215	if (hwirq < 0) {
34e36c15 JJ	216	rc = hwirq;
446bc1ff	217	dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
34e36c15 JJ	218	goto out_free;
	219	}
	220
	221	virq = irq_create_mapping(msi_data->irqhost, hwirq);
	222
	223	if (virq == NO_IRQ) {
446bc1ff	224	dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
7e7ab367	225	msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
34e36c15 JJ	226	rc = -ENOSPC;
	227	goto out_free;
	228	}
d1921bcd	229	/* chip_data is msi_data via host->hostdata in host->map() */
ec775d0e	230	irq_set_msi_desc(virq, entry);
34e36c15	231
80818813	232	fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
34e36c15 JJ	233	write_msi_msg(virq, &msg);
	234	}
	235	return 0;
	236
	237	out_free:
694a7a36	238	/* free by the caller of this function */
34e36c15 JJ	239	return rc;
	240	}
	241
692d1037	242	static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
34e36c15	243	{
ddaedd1c TG	244	struct irq_chip *chip = irq_desc_get_chip(desc);
ddaedd1c TG	245	struct irq_data *idata = irq_desc_get_irq_data(desc);
34e36c15	246	unsigned int cascade_irq;
02adac60	247	struct fsl_msi *msi_data;
34e36c15 JJ	248	int msir_index = -1;
	249	u32 msir_value = 0;
	250	u32 intr_index;
	251	u32 have_shift = 0;
02adac60 LY	252	struct fsl_msi_cascade_data *cascade_data;
02adac60 LY	253
d1921bcd	254	cascade_data = irq_get_handler_data(irq);
02adac60	255	msi_data = cascade_data->msi_data;
34e36c15	256
239007b8	257	raw_spin_lock(&desc->lock);
34e36c15	258	if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
37e16615	259	if (chip->irq_mask_ack)
ddaedd1c	260	chip->irq_mask_ack(idata);
34e36c15	261	else {
ddaedd1c TG	262	chip->irq_mask(idata);
ddaedd1c TG	263	chip->irq_ack(idata);
34e36c15 JJ	264	}
	265	}
	266
ddaedd1c	267	if (unlikely(irqd_irq_inprogress(idata)))
34e36c15 JJ	268	goto unlock;
34e36c15 JJ	269
02adac60	270	msir_index = cascade_data->index;
34e36c15	271
f31dd944	272	if (msir_index >= NR_MSI_REG_MAX)
34e36c15 JJ	273	cascade_irq = NO_IRQ;
34e36c15 JJ	274
ddaedd1c	275	irqd_set_chained_irq_inprogress(idata);
80818813	276	switch (msi_data->feature & FSL_PIC_IP_MASK) {
34e36c15 JJ	277	case FSL_PIC_IP_MPIC:
	278	msir_value = fsl_msi_read(msi_data->msi_regs,
	279	msir_index * 0x10);
	280	break;
	281	case FSL_PIC_IP_IPIC:
	282	msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
	283	break;
305bcf26 SW	284	#ifdef CONFIG_EPAPR_PARAVIRT
	285	case FSL_PIC_IP_VMPIC: {
	286	unsigned int ret;
446bc1ff TT	287	ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
	288	if (ret) {
	289	pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
	290	"irq %u (ret=%u)\n", irq, ret);
	291	msir_value = 0;
	292	}
	293	break;
34e36c15	294	}
305bcf26 SW	295	#endif
305bcf26 SW	296	}
34e36c15 JJ	297
	298	while (msir_value) {
	299	intr_index = ffs(msir_value) - 1;
	300
	301	cascade_irq = irq_linear_revmap(msi_data->irqhost,
f31dd944 ML	302	msi_hwirq(msi_data, msir_index,
f31dd944 ML	303	intr_index + have_shift));
34e36c15 JJ	304	if (cascade_irq != NO_IRQ)
34e36c15 JJ	305	generic_handle_irq(cascade_irq);
692d1037 AV	306	have_shift += intr_index + 1;
692d1037 AV	307	msir_value = msir_value >> (intr_index + 1);
34e36c15	308	}
ddaedd1c	309	irqd_clr_chained_irq_inprogress(idata);
34e36c15 JJ	310
	311	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	312	case FSL_PIC_IP_MPIC:
446bc1ff	313	case FSL_PIC_IP_VMPIC:
ddaedd1c	314	chip->irq_eoi(idata);
34e36c15 JJ	315	break;
34e36c15 JJ	316	case FSL_PIC_IP_IPIC:
ddaedd1c TG	317	if (!irqd_irq_disabled(idata) && chip->irq_unmask)
ddaedd1c TG	318	chip->irq_unmask(idata);
34e36c15 JJ	319	break;
	320	}
	321	unlock:
239007b8	322	raw_spin_unlock(&desc->lock);
34e36c15 JJ	323	}
34e36c15 JJ	324
a454dc50	325	static int fsl_of_msi_remove(struct platform_device *ofdev)
48059993	326	{
6c4c82e2	327	struct fsl_msi *msi = platform_get_drvdata(ofdev);
48059993 LY	328	int virq, i;
	329	struct fsl_msi_cascade_data *cascade_data;
	330
	331	if (msi->list.prev != NULL)
	332	list_del(&msi->list);
f31dd944	333	for (i = 0; i < NR_MSI_REG_MAX; i++) {
48059993 LY	334	virq = msi->msi_virqs[i];
48059993 LY	335	if (virq != NO_IRQ) {
ec775d0e	336	cascade_data = irq_get_handler_data(virq);
48059993 LY	337	kfree(cascade_data);
	338	irq_dispose_mapping(virq);
	339	}
	340	}
	341	if (msi->bitmap.bitmap)
	342	msi_bitmap_free(&msi->bitmap);
446bc1ff TT	343	if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
446bc1ff TT	344	iounmap(msi->msi_regs);
48059993 LY	345	kfree(msi);
	346
	347	return 0;
	348	}
	349
58631ad1 SAS	350	static struct lock_class_key fsl_msi_irq_class;
58631ad1 SAS	351
cad5cef6 GKH	352	static int fsl_msi_setup_hwirq(struct fsl_msi msi, struct platform_device dev,
cad5cef6 GKH	353	int offset, int irq_index)
6820fead SW	354	{
6820fead SW	355	struct fsl_msi_cascade_data *cascade_data = NULL;
f31dd944	356	int virt_msir, i;
6820fead SW	357
	358	virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
	359	if (virt_msir == NO_IRQ) {
	360	dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
	361	__func__, irq_index);
	362	return 0;
	363	}
	364
	365	cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
	366	if (!cascade_data) {
	367	dev_err(&dev->dev, "No memory for MSI cascade data\n");
	368	return -ENOMEM;
	369	}
58631ad1	370	irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
6820fead	371	msi->msi_virqs[irq_index] = virt_msir;
22285118	372	cascade_data->index = offset;
6820fead	373	cascade_data->msi_data = msi;
ec775d0e TG	374	irq_set_handler_data(virt_msir, cascade_data);
ec775d0e TG	375	irq_set_chained_handler(virt_msir, fsl_msi_cascade);
6820fead	376
f31dd944 ML	377	/* Release the hwirqs corresponding to this MSI register */
	378	for (i = 0; i < IRQS_PER_MSI_REG; i++)
	379	msi_bitmap_free_hwirqs(&msi->bitmap,
	380	msi_hwirq(msi, offset, i), 1);
	381
6820fead SW	382	return 0;
	383	}
	384
b1608d69	385	static const struct of_device_id fsl_of_msi_ids[];
cad5cef6	386	static int fsl_of_msi_probe(struct platform_device *dev)
34e36c15	387	{
b1608d69	388	const struct of_device_id *match;
34e36c15	389	struct fsl_msi *msi;
f31dd944	390	struct resource res, msiir;
6820fead	391	int err, i, j, irq_index, count;
34e36c15	392	const u32 *p;
f318f1d7	393	const struct fsl_msi_feature *features;
061ca4ad LY	394	int len;
061ca4ad LY	395	u32 offset;
34e36c15	396
b1608d69 GL	397	match = of_match_device(fsl_of_msi_ids, &dev->dev);
b1608d69 GL	398	if (!match)
00006124	399	return -EINVAL;
b1608d69	400	features = match->data;
00006124	401
34e36c15 JJ	402	printk(KERN_DEBUG "Setting up Freescale MSI support\n");
	403
	404	msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
	405	if (!msi) {
	406	dev_err(&dev->dev, "No memory for MSI structure\n");
48059993	407	return -ENOMEM;
34e36c15	408	}
6c4c82e2	409	platform_set_drvdata(dev, msi);
34e36c15	410
a8db8cf0	411	msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
f31dd944	412	NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
34e36c15	413
34e36c15 JJ	414	if (msi->irqhost == NULL) {
34e36c15 JJ	415	dev_err(&dev->dev, "No memory for MSI irqhost\n");
34e36c15 JJ	416	err = -ENOMEM;
	417	goto error_out;
	418	}
	419
446bc1ff TT	420	/*
	421	* Under the Freescale hypervisor, the msi nodes don't have a 'reg'
	422	* property. Instead, we use hypercalls to access the MSI.
	423	*/
	424	if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
	425	err = of_address_to_resource(dev->dev.of_node, 0, &res);
	426	if (err) {
	427	dev_err(&dev->dev, "invalid resource for node %s\n",
61c7a080	428	dev->dev.of_node->full_name);
446bc1ff TT	429	goto error_out;
446bc1ff TT	430	}
34e36c15	431
446bc1ff TT	432	msi->msi_regs = ioremap(res.start, resource_size(&res));
446bc1ff TT	433	if (!msi->msi_regs) {
b53804c7	434	err = -ENOMEM;
446bc1ff TT	435	dev_err(&dev->dev, "could not map node %s\n",
	436	dev->dev.of_node->full_name);
	437	goto error_out;
	438	}
	439	msi->msiir_offset =
	440	features->msiir_offset + (res.start & 0xfffff);
f31dd944 ML	441
	442	/*
	443	* First read the MSIIR/MSIIR1 offset from dts
	444	* On failure use the hardcode MSIIR offset
	445	*/
	446	if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
	447	msi->msiir_offset = features->msiir_offset +
	448	(res.start & MSIIR_OFFSET_MASK);
	449	else
	450	msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
34e36c15 JJ	451	}
34e36c15 JJ	452
692d1037	453	msi->feature = features->fsl_pic_ip;
34e36c15	454
895d603f TT	455	/*
	456	* Remember the phandle, so that we can match with any PCI nodes
	457	* that have an "fsl,msi" property.
	458	*/
	459	msi->phandle = dev->dev.of_node->phandle;
	460
f8dc6eb7 WY	461	err = fsl_msi_init_allocator(msi);
f8dc6eb7 WY	462	if (err) {
34e36c15 JJ	463	dev_err(&dev->dev, "Error allocating MSI bitmap\n");
	464	goto error_out;
	465	}
	466
6820fead	467	p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
6820fead	468
f31dd944 ML	469	if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3")) {
	470	msi->srs_shift = MSIIR1_SRS_SHIFT;
	471	msi->ibs_shift = MSIIR1_IBS_SHIFT;
	472	if (p)
	473	dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
	474	__func__);
	475
	476	for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
	477	irq_index++) {
	478	err = fsl_msi_setup_hwirq(msi, dev,
	479	irq_index, irq_index);
	480	if (err)
	481	goto error_out;
	482	}
	483	} else {
	484	static const u32 all_avail[] =
	485	{ 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
6820fead	486
f31dd944 ML	487	msi->srs_shift = MSIIR_SRS_SHIFT;
	488	msi->ibs_shift = MSIIR_IBS_SHIFT;
	489
	490	if (p && len % (2 * sizeof(u32)) != 0) {
	491	dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
	492	__func__);
6820fead SW	493	err = -EINVAL;
	494	goto error_out;
	495	}
	496
f31dd944 ML	497	if (!p) {
	498	p = all_avail;
	499	len = sizeof(all_avail);
	500	}
6820fead	501
f31dd944 ML	502	for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
	503	if (p[i * 2] % IRQS_PER_MSI_REG \|\|
	504	p[i * 2 + 1] % IRQS_PER_MSI_REG) {
	505	pr_warn("%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
	506	__func__, dev->dev.of_node->full_name,
	507	p[i * 2 + 1], p[i * 2]);
	508	err = -EINVAL;
02adac60	509	goto error_out;
f31dd944 ML	510	}
	511
	512	offset = p[i * 2] / IRQS_PER_MSI_REG;
	513	count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
	514
	515	for (j = 0; j < count; j++, irq_index++) {
	516	err = fsl_msi_setup_hwirq(msi, dev, offset + j,
	517	irq_index);
	518	if (err)
	519	goto error_out;
	520	}
34e36c15 JJ	521	}
	522	}
	523
694a7a36	524	list_add_tail(&msi->list, &msi_head);
34e36c15	525
80818813 LCB	526	/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
	527	if (!ppc_md.setup_msi_irqs) {
	528	ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
	529	ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
	530	ppc_md.msi_check_device = fsl_msi_check_device;
	531	} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
	532	dev_err(&dev->dev, "Different MSI driver already installed!\n");
	533	err = -ENODEV;
	534	goto error_out;
	535	}
34e36c15 JJ	536	return 0;
34e36c15 JJ	537	error_out:
48059993	538	fsl_of_msi_remove(dev);
34e36c15 JJ	539	return err;
	540	}
	541
	542	static const struct fsl_msi_feature mpic_msi_feature = {
	543	.fsl_pic_ip = FSL_PIC_IP_MPIC,
	544	.msiir_offset = 0x140,
	545	};
	546
	547	static const struct fsl_msi_feature ipic_msi_feature = {
	548	.fsl_pic_ip = FSL_PIC_IP_IPIC,
	549	.msiir_offset = 0x38,
	550	};
	551
446bc1ff TT	552	static const struct fsl_msi_feature vmpic_msi_feature = {
	553	.fsl_pic_ip = FSL_PIC_IP_VMPIC,
	554	.msiir_offset = 0,
	555	};
	556
34e36c15 JJ	557	static const struct of_device_id fsl_of_msi_ids[] = {
	558	{
	559	.compatible = "fsl,mpic-msi",
a99cc82b	560	.data = &mpic_msi_feature,
34e36c15	561	},
f31dd944 ML	562	{
	563	.compatible = "fsl,mpic-msi-v4.3",
	564	.data = &mpic_msi_feature,
	565	},
34e36c15 JJ	566	{
34e36c15 JJ	567	.compatible = "fsl,ipic-msi",
a99cc82b	568	.data = &ipic_msi_feature,
34e36c15	569	},
305bcf26	570	#ifdef CONFIG_EPAPR_PARAVIRT
446bc1ff TT	571	{
446bc1ff TT	572	.compatible = "fsl,vmpic-msi",
a99cc82b	573	.data = &vmpic_msi_feature,
446bc1ff	574	},
305bcf26	575	#endif
34e36c15 JJ	576	{}
	577	};
	578
00006124	579	static struct platform_driver fsl_of_msi_driver = {
4018294b GL	580	.driver = {
	581	.name = "fsl-msi",
	582	.owner = THIS_MODULE,
	583	.of_match_table = fsl_of_msi_ids,
	584	},
34e36c15	585	.probe = fsl_of_msi_probe,
48059993	586	.remove = fsl_of_msi_remove,
34e36c15 JJ	587	};
	588
	589	static __init int fsl_of_msi_init(void)
	590	{
00006124	591	return platform_driver_register(&fsl_of_msi_driver);
34e36c15 JJ	592	}
	593
	594	subsys_initcall(fsl_of_msi_init);