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1 | /* |
2 | * Copyright 2009-2010 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation | |
5 | * | |
6 | * Author: Vivek Mahajan <vivek.mahajan@freescale.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/of_platform.h> | |
25 | #include <asm/io.h> | |
26 | ||
27 | #include "fsl_85xx_cache_ctlr.h" | |
28 | ||
29 | static char *sram_size; | |
30 | static char *sram_offset; | |
31 | struct mpc85xx_l2ctlr __iomem *l2ctlr; | |
32 | ||
33 | static long get_cache_sram_size(void) | |
34 | { | |
35 | unsigned long val; | |
36 | ||
37 | if (!sram_size || (strict_strtoul(sram_size, 0, &val) < 0)) | |
38 | return -EINVAL; | |
39 | ||
40 | return val; | |
41 | } | |
42 | ||
43 | static long get_cache_sram_offset(void) | |
44 | { | |
45 | unsigned long val; | |
46 | ||
47 | if (!sram_offset || (strict_strtoul(sram_offset, 0, &val) < 0)) | |
48 | return -EINVAL; | |
49 | ||
50 | return val; | |
51 | } | |
52 | ||
53 | static int __init get_size_from_cmdline(char *str) | |
54 | { | |
55 | if (!str) | |
56 | return 0; | |
57 | ||
58 | sram_size = str; | |
59 | return 1; | |
60 | } | |
61 | ||
62 | static int __init get_offset_from_cmdline(char *str) | |
63 | { | |
64 | if (!str) | |
65 | return 0; | |
66 | ||
67 | sram_offset = str; | |
68 | return 1; | |
69 | } | |
70 | ||
71 | __setup("cache-sram-size=", get_size_from_cmdline); | |
72 | __setup("cache-sram-offset=", get_offset_from_cmdline); | |
73 | ||
74 | static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev, | |
75 | const struct of_device_id *match) | |
76 | { | |
77 | long rval; | |
78 | unsigned int rem; | |
79 | unsigned char ways; | |
80 | const unsigned int *prop; | |
81 | unsigned int l2cache_size; | |
82 | struct sram_parameters sram_params; | |
83 | ||
84 | if (!dev->dev.of_node) { | |
85 | dev_err(&dev->dev, "Device's OF-node is NULL\n"); | |
86 | return -EINVAL; | |
87 | } | |
88 | ||
89 | prop = of_get_property(dev->dev.of_node, "cache-size", NULL); | |
90 | if (!prop) { | |
91 | dev_err(&dev->dev, "Missing L2 cache-size\n"); | |
92 | return -EINVAL; | |
93 | } | |
94 | l2cache_size = *prop; | |
95 | ||
96 | sram_params.sram_size = get_cache_sram_size(); | |
97 | if (sram_params.sram_size <= 0) { | |
98 | dev_err(&dev->dev, | |
99 | "Entire L2 as cache, Aborting Cache-SRAM stuff\n"); | |
100 | return -EINVAL; | |
101 | } | |
102 | ||
103 | sram_params.sram_offset = get_cache_sram_offset(); | |
104 | if (sram_params.sram_offset <= 0) { | |
105 | dev_err(&dev->dev, | |
106 | "Entire L2 as cache, provide a valid sram offset\n"); | |
107 | return -EINVAL; | |
108 | } | |
109 | ||
110 | ||
111 | rem = l2cache_size % sram_params.sram_size; | |
112 | ways = LOCK_WAYS_FULL * sram_params.sram_size / l2cache_size; | |
113 | if (rem || (ways & (ways - 1))) { | |
114 | dev_err(&dev->dev, "Illegal cache-sram-size in command line\n"); | |
115 | return -EINVAL; | |
116 | } | |
117 | ||
118 | l2ctlr = of_iomap(dev->dev.of_node, 0); | |
119 | if (!l2ctlr) { | |
120 | dev_err(&dev->dev, "Can't map L2 controller\n"); | |
121 | return -EINVAL; | |
122 | } | |
123 | ||
124 | /* | |
125 | * Write bits[0-17] to srbar0 | |
126 | */ | |
127 | out_be32(&l2ctlr->srbar0, | |
128 | sram_params.sram_offset & L2SRAM_BAR_MSK_LO18); | |
129 | ||
130 | /* | |
131 | * Write bits[18-21] to srbare0 | |
132 | */ | |
133 | #ifdef CONFIG_PHYS_64BIT | |
134 | out_be32(&l2ctlr->srbarea0, | |
135 | (sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4); | |
136 | #endif | |
137 | ||
138 | clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI); | |
139 | ||
140 | switch (ways) { | |
141 | case LOCK_WAYS_EIGHTH: | |
142 | setbits32(&l2ctlr->ctl, | |
143 | L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH); | |
144 | break; | |
145 | ||
146 | case LOCK_WAYS_TWO_EIGHTH: | |
147 | setbits32(&l2ctlr->ctl, | |
148 | L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART); | |
149 | break; | |
150 | ||
151 | case LOCK_WAYS_HALF: | |
152 | setbits32(&l2ctlr->ctl, | |
153 | L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF); | |
154 | break; | |
155 | ||
156 | case LOCK_WAYS_FULL: | |
157 | default: | |
158 | setbits32(&l2ctlr->ctl, | |
159 | L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL); | |
160 | break; | |
161 | } | |
162 | eieio(); | |
163 | ||
164 | rval = instantiate_cache_sram(dev, sram_params); | |
165 | if (rval < 0) { | |
166 | dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n"); | |
167 | iounmap(l2ctlr); | |
168 | return -EINVAL; | |
169 | } | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | static int __devexit mpc85xx_l2ctlr_of_remove(struct platform_device *dev) | |
175 | { | |
176 | BUG_ON(!l2ctlr); | |
177 | ||
178 | iounmap(l2ctlr); | |
179 | remove_cache_sram(dev); | |
180 | dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n"); | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | static struct of_device_id mpc85xx_l2ctlr_of_match[] = { | |
186 | { | |
187 | .compatible = "fsl,p2020-l2-cache-controller", | |
188 | }, | |
189 | { | |
190 | .compatible = "fsl,p2010-l2-cache-controller", | |
191 | }, | |
192 | { | |
193 | .compatible = "fsl,p1020-l2-cache-controller", | |
194 | }, | |
195 | { | |
196 | .compatible = "fsl,p1011-l2-cache-controller", | |
197 | }, | |
198 | { | |
199 | .compatible = "fsl,p1013-l2-cache-controller", | |
200 | }, | |
201 | { | |
202 | .compatible = "fsl,p1022-l2-cache-controller", | |
203 | }, | |
204 | {}, | |
205 | }; | |
206 | ||
207 | static struct of_platform_driver mpc85xx_l2ctlr_of_platform_driver = { | |
208 | .driver = { | |
209 | .name = "fsl-l2ctlr", | |
210 | .owner = THIS_MODULE, | |
211 | .of_match_table = mpc85xx_l2ctlr_of_match, | |
212 | }, | |
213 | .probe = mpc85xx_l2ctlr_of_probe, | |
214 | .remove = __devexit_p(mpc85xx_l2ctlr_of_remove), | |
215 | }; | |
216 | ||
217 | static __init int mpc85xx_l2ctlr_of_init(void) | |
218 | { | |
219 | return of_register_platform_driver(&mpc85xx_l2ctlr_of_platform_driver); | |
220 | } | |
221 | ||
222 | static void __exit mpc85xx_l2ctlr_of_exit(void) | |
223 | { | |
224 | of_unregister_platform_driver(&mpc85xx_l2ctlr_of_platform_driver); | |
225 | } | |
226 | ||
227 | subsys_initcall(mpc85xx_l2ctlr_of_init); | |
228 | module_exit(mpc85xx_l2ctlr_of_exit); | |
229 | ||
230 | MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init"); | |
231 | MODULE_LICENSE("GPL v2"); |