Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1beb6a7d | 2 | * arch/powerpc/sysdev/dart_iommu.c |
1da177e4 | 3 | * |
91f14480 | 4 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
1beb6a7d BH |
5 | * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>, |
6 | * IBM Corporation | |
1da177e4 LT |
7 | * |
8 | * Based on pSeries_iommu.c: | |
9 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation | |
91f14480 | 10 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
1da177e4 | 11 | * |
1beb6a7d BH |
12 | * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu. |
13 | * | |
1da177e4 | 14 | * |
1da177e4 LT |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
1beb6a7d | 19 | * |
1da177e4 LT |
20 | * This program is distributed in the hope that it will be useful, |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
1beb6a7d | 24 | * |
1da177e4 LT |
25 | * You should have received a copy of the GNU General Public License |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/init.h> |
31 | #include <linux/types.h> | |
1da177e4 LT |
32 | #include <linux/mm.h> |
33 | #include <linux/spinlock.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/dma-mapping.h> | |
37 | #include <linux/vmalloc.h> | |
7e11580b | 38 | #include <linux/suspend.h> |
95f72d1e | 39 | #include <linux/memblock.h> |
5a0e3ad6 | 40 | #include <linux/gfp.h> |
514c6032 | 41 | #include <linux/kmemleak.h> |
1da177e4 LT |
42 | #include <asm/io.h> |
43 | #include <asm/prom.h> | |
1da177e4 LT |
44 | #include <asm/iommu.h> |
45 | #include <asm/pci-bridge.h> | |
46 | #include <asm/machdep.h> | |
1da177e4 | 47 | #include <asm/cacheflush.h> |
d387899f | 48 | #include <asm/ppc-pci.h> |
1da177e4 | 49 | |
9933f299 DG |
50 | #include "dart.h" |
51 | ||
c40785ad BH |
52 | /* DART table address and size */ |
53 | static u32 *dart_tablebase; | |
1da177e4 LT |
54 | static unsigned long dart_tablesize; |
55 | ||
1da177e4 | 56 | /* Mapped base address for the dart */ |
6fa2ffe9 | 57 | static unsigned int __iomem *dart; |
1da177e4 LT |
58 | |
59 | /* Dummy val that entries are set to when unused */ | |
60 | static unsigned int dart_emptyval; | |
61 | ||
1beb6a7d BH |
62 | static struct iommu_table iommu_table_dart; |
63 | static int iommu_table_dart_inited; | |
1da177e4 | 64 | static int dart_dirty; |
1beb6a7d | 65 | static int dart_is_u4; |
1da177e4 | 66 | |
8fb07c04 BH |
67 | #define DART_U4_BYPASS_BASE 0x8000000000ull |
68 | ||
1da177e4 LT |
69 | #define DBG(...) |
70 | ||
d900bd73 AB |
71 | static DEFINE_SPINLOCK(invalidate_lock); |
72 | ||
1da177e4 LT |
73 | static inline void dart_tlb_invalidate_all(void) |
74 | { | |
75 | unsigned long l = 0; | |
1beb6a7d | 76 | unsigned int reg, inv_bit; |
1da177e4 | 77 | unsigned long limit; |
d900bd73 AB |
78 | unsigned long flags; |
79 | ||
80 | spin_lock_irqsave(&invalidate_lock, flags); | |
1da177e4 LT |
81 | |
82 | DBG("dart: flush\n"); | |
83 | ||
84 | /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the | |
85 | * control register and wait for it to clear. | |
86 | * | |
87 | * Gotcha: Sometimes, the DART won't detect that the bit gets | |
88 | * set. If so, clear it and set it again. | |
1beb6a7d | 89 | */ |
1da177e4 LT |
90 | |
91 | limit = 0; | |
92 | ||
1beb6a7d | 93 | inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB; |
1da177e4 | 94 | retry: |
1da177e4 | 95 | l = 0; |
1beb6a7d BH |
96 | reg = DART_IN(DART_CNTL); |
97 | reg |= inv_bit; | |
98 | DART_OUT(DART_CNTL, reg); | |
99 | ||
100 | while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit)) | |
1da177e4 | 101 | l++; |
1beb6a7d | 102 | if (l == (1L << limit)) { |
1da177e4 LT |
103 | if (limit < 4) { |
104 | limit++; | |
feb76c7b OJ |
105 | reg = DART_IN(DART_CNTL); |
106 | reg &= ~inv_bit; | |
1beb6a7d | 107 | DART_OUT(DART_CNTL, reg); |
1da177e4 LT |
108 | goto retry; |
109 | } else | |
1beb6a7d | 110 | panic("DART: TLB did not flush after waiting a long " |
1da177e4 LT |
111 | "time. Buggy U3 ?"); |
112 | } | |
d900bd73 AB |
113 | |
114 | spin_unlock_irqrestore(&invalidate_lock, flags); | |
1da177e4 LT |
115 | } |
116 | ||
feb76c7b OJ |
117 | static inline void dart_tlb_invalidate_one(unsigned long bus_rpn) |
118 | { | |
119 | unsigned int reg; | |
120 | unsigned int l, limit; | |
d900bd73 AB |
121 | unsigned long flags; |
122 | ||
123 | spin_lock_irqsave(&invalidate_lock, flags); | |
feb76c7b OJ |
124 | |
125 | reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE | | |
126 | (bus_rpn & DART_CNTL_U4_IONE_MASK); | |
127 | DART_OUT(DART_CNTL, reg); | |
128 | ||
129 | limit = 0; | |
130 | wait_more: | |
131 | l = 0; | |
132 | while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) { | |
133 | rmb(); | |
134 | l++; | |
135 | } | |
136 | ||
137 | if (l == (1L << limit)) { | |
138 | if (limit < 4) { | |
139 | limit++; | |
140 | goto wait_more; | |
141 | } else | |
142 | panic("DART: TLB did not flush after waiting a long " | |
143 | "time. Buggy U4 ?"); | |
144 | } | |
d900bd73 AB |
145 | |
146 | spin_unlock_irqrestore(&invalidate_lock, flags); | |
feb76c7b OJ |
147 | } |
148 | ||
c40785ad BH |
149 | static void dart_cache_sync(unsigned int *base, unsigned int count) |
150 | { | |
151 | /* | |
152 | * We add 1 to the number of entries to flush, following a | |
153 | * comment in Darwin indicating that the memory controller | |
154 | * can prefetch unmapped memory under some circumstances. | |
155 | */ | |
156 | unsigned long start = (unsigned long)base; | |
157 | unsigned long end = start + (count + 1) * sizeof(unsigned int); | |
158 | unsigned int tmp; | |
159 | ||
160 | /* Perform a standard cache flush */ | |
161 | flush_inval_dcache_range(start, end); | |
162 | ||
163 | /* | |
164 | * Perform the sequence described in the CPC925 manual to | |
165 | * ensure all the data gets to a point the cache incoherent | |
166 | * DART hardware will see. | |
167 | */ | |
168 | asm volatile(" sync;" | |
169 | " isync;" | |
170 | " dcbf 0,%1;" | |
171 | " sync;" | |
172 | " isync;" | |
173 | " lwz %0,0(%1);" | |
174 | " isync" : "=r" (tmp) : "r" (end) : "memory"); | |
175 | } | |
176 | ||
1da177e4 LT |
177 | static void dart_flush(struct iommu_table *tbl) |
178 | { | |
eeac5c14 | 179 | mb(); |
feb76c7b | 180 | if (dart_dirty) { |
1da177e4 | 181 | dart_tlb_invalidate_all(); |
feb76c7b OJ |
182 | dart_dirty = 0; |
183 | } | |
1da177e4 LT |
184 | } |
185 | ||
6490c490 | 186 | static int dart_build(struct iommu_table *tbl, long index, |
1da177e4 | 187 | long npages, unsigned long uaddr, |
4f3dd8a0 | 188 | enum dma_data_direction direction, |
00085f1e | 189 | unsigned long attrs) |
1da177e4 | 190 | { |
c40785ad | 191 | unsigned int *dp, *orig_dp; |
1da177e4 | 192 | unsigned int rpn; |
feb76c7b | 193 | long l; |
1da177e4 LT |
194 | |
195 | DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr); | |
196 | ||
c40785ad | 197 | orig_dp = dp = ((unsigned int*)tbl->it_base) + index; |
1beb6a7d | 198 | |
af901ca1 | 199 | /* On U3, all memory is contiguous, so we can move this |
1da177e4 LT |
200 | * out of the loop. |
201 | */ | |
feb76c7b OJ |
202 | l = npages; |
203 | while (l--) { | |
579468a9 | 204 | rpn = __pa(uaddr) >> DART_PAGE_SHIFT; |
1da177e4 LT |
205 | |
206 | *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); | |
207 | ||
d0035c62 | 208 | uaddr += DART_PAGE_SIZE; |
1da177e4 | 209 | } |
c40785ad | 210 | dart_cache_sync(orig_dp, npages); |
eeac5c14 | 211 | |
feb76c7b OJ |
212 | if (dart_is_u4) { |
213 | rpn = index; | |
feb76c7b OJ |
214 | while (npages--) |
215 | dart_tlb_invalidate_one(rpn++); | |
216 | } else { | |
217 | dart_dirty = 1; | |
218 | } | |
6490c490 | 219 | return 0; |
1da177e4 LT |
220 | } |
221 | ||
222 | ||
223 | static void dart_free(struct iommu_table *tbl, long index, long npages) | |
224 | { | |
c40785ad BH |
225 | unsigned int *dp, *orig_dp; |
226 | long orig_npages = npages; | |
1beb6a7d | 227 | |
1da177e4 LT |
228 | /* We don't worry about flushing the TLB cache. The only drawback of |
229 | * not doing it is that we won't catch buggy device drivers doing | |
230 | * bad DMAs, but then no 32-bit architecture ever does either. | |
231 | */ | |
232 | ||
233 | DBG("dart: free at: %lx, %lx\n", index, npages); | |
234 | ||
c40785ad | 235 | orig_dp = dp = ((unsigned int *)tbl->it_base) + index; |
1beb6a7d | 236 | |
1da177e4 LT |
237 | while (npages--) |
238 | *(dp++) = dart_emptyval; | |
1da177e4 | 239 | |
c40785ad BH |
240 | dart_cache_sync(orig_dp, orig_npages); |
241 | } | |
1da177e4 | 242 | |
c40785ad | 243 | static void allocate_dart(void) |
1da177e4 | 244 | { |
c40785ad | 245 | unsigned long tmp; |
1da177e4 | 246 | |
c40785ad BH |
247 | /* 512 pages (2MB) is max DART tablesize. */ |
248 | dart_tablesize = 1UL << 21; | |
1beb6a7d | 249 | |
c40785ad BH |
250 | /* |
251 | * 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we | |
252 | * will blow up an entire large page anyway in the kernel mapping. | |
1da177e4 | 253 | */ |
c40785ad BH |
254 | dart_tablebase = __va(memblock_alloc_base(1UL<<24, |
255 | 1UL<<24, 0x80000000L)); | |
256 | ||
257 | /* There is no point scanning the DART space for leaks*/ | |
258 | kmemleak_no_scan((void *)dart_tablebase); | |
1da177e4 LT |
259 | |
260 | /* Allocate a spare page to map all invalid DART pages. We need to do | |
261 | * that to work around what looks like a problem with the HT bridge | |
262 | * prefetching into invalid pages and corrupting data | |
263 | */ | |
9a8dd708 | 264 | tmp = memblock_phys_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); |
1beb6a7d BH |
265 | dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & |
266 | DARTMAP_RPNMASK); | |
1da177e4 | 267 | |
c40785ad BH |
268 | printk(KERN_INFO "DART table allocated at: %p\n", dart_tablebase); |
269 | } | |
270 | ||
271 | static int __init dart_init(struct device_node *dart_node) | |
272 | { | |
273 | unsigned int i; | |
274 | unsigned long base, size; | |
275 | struct resource r; | |
276 | ||
277 | /* IOMMU disabled by the user ? bail out */ | |
278 | if (iommu_is_off) | |
279 | return -ENODEV; | |
280 | ||
281 | /* | |
282 | * Only use the DART if the machine has more than 1GB of RAM | |
283 | * or if requested with iommu=on on cmdline. | |
284 | * | |
285 | * 1GB of RAM is picked as limit because some default devices | |
286 | * (i.e. Airport Extreme) have 30 bit address range limits. | |
287 | */ | |
288 | ||
289 | if (!iommu_force_on && memblock_end_of_DRAM() <= 0x40000000ull) | |
290 | return -ENODEV; | |
291 | ||
292 | /* Get DART registers */ | |
293 | if (of_address_to_resource(dart_node, 0, &r)) | |
294 | panic("DART: can't get register base ! "); | |
295 | ||
1beb6a7d | 296 | /* Map in DART registers */ |
28f65c11 | 297 | dart = ioremap(r.start, resource_size(&r)); |
1da177e4 | 298 | if (dart == NULL) |
1beb6a7d | 299 | panic("DART: Cannot map registers!"); |
1da177e4 | 300 | |
c40785ad BH |
301 | /* Allocate the DART and dummy page */ |
302 | allocate_dart(); | |
1da177e4 LT |
303 | |
304 | /* Fill initial table */ | |
305 | for (i = 0; i < dart_tablesize/4; i++) | |
c40785ad BH |
306 | dart_tablebase[i] = dart_emptyval; |
307 | ||
308 | /* Push to memory */ | |
309 | dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32)); | |
1da177e4 LT |
310 | |
311 | /* Initialize DART with table base and enable it. */ | |
c40785ad | 312 | base = ((unsigned long)dart_tablebase) >> DART_PAGE_SHIFT; |
1beb6a7d BH |
313 | size = dart_tablesize >> DART_PAGE_SHIFT; |
314 | if (dart_is_u4) { | |
56c8eaee | 315 | size &= DART_SIZE_U4_SIZE_MASK; |
1beb6a7d BH |
316 | DART_OUT(DART_BASE_U4, base); |
317 | DART_OUT(DART_SIZE_U4, size); | |
318 | DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE); | |
319 | } else { | |
56c8eaee | 320 | size &= DART_CNTL_U3_SIZE_MASK; |
1beb6a7d BH |
321 | DART_OUT(DART_CNTL, |
322 | DART_CNTL_U3_ENABLE | | |
323 | (base << DART_CNTL_U3_BASE_SHIFT) | | |
324 | (size << DART_CNTL_U3_SIZE_SHIFT)); | |
325 | } | |
1da177e4 LT |
326 | |
327 | /* Invalidate DART to get rid of possible stale TLBs */ | |
328 | dart_tlb_invalidate_all(); | |
329 | ||
1beb6a7d BH |
330 | printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n", |
331 | dart_is_u4 ? "U4" : "U3"); | |
1da177e4 LT |
332 | |
333 | return 0; | |
334 | } | |
335 | ||
da004c36 AK |
336 | static struct iommu_table_ops iommu_dart_ops = { |
337 | .set = dart_build, | |
338 | .clear = dart_free, | |
339 | .flush = dart_flush, | |
340 | }; | |
341 | ||
1beb6a7d | 342 | static void iommu_table_dart_setup(void) |
1da177e4 | 343 | { |
1beb6a7d BH |
344 | iommu_table_dart.it_busno = 0; |
345 | iommu_table_dart.it_offset = 0; | |
1da177e4 | 346 | /* it_size is in number of entries */ |
5d2efba6 | 347 | iommu_table_dart.it_size = dart_tablesize / sizeof(u32); |
67bfa0ee | 348 | iommu_table_dart.it_page_shift = IOMMU_PAGE_SHIFT_4K; |
1da177e4 LT |
349 | |
350 | /* Initialize the common IOMMU code */ | |
c40785ad | 351 | iommu_table_dart.it_base = (unsigned long)dart_tablebase; |
1beb6a7d BH |
352 | iommu_table_dart.it_index = 0; |
353 | iommu_table_dart.it_blocksize = 1; | |
da004c36 | 354 | iommu_table_dart.it_ops = &iommu_dart_ops; |
ca1588e7 | 355 | iommu_init_table(&iommu_table_dart, -1); |
1da177e4 LT |
356 | |
357 | /* Reserve the last page of the DART to avoid possible prefetch | |
358 | * past the DART mapped area | |
359 | */ | |
1beb6a7d | 360 | set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map); |
1da177e4 LT |
361 | } |
362 | ||
12d04eef | 363 | static void pci_dma_bus_setup_dart(struct pci_bus *bus) |
1da177e4 | 364 | { |
1beb6a7d BH |
365 | if (!iommu_table_dart_inited) { |
366 | iommu_table_dart_inited = 1; | |
367 | iommu_table_dart_setup(); | |
1da177e4 | 368 | } |
1da177e4 LT |
369 | } |
370 | ||
8fb07c04 BH |
371 | static bool dart_device_on_pcie(struct device *dev) |
372 | { | |
373 | struct device_node *np = of_node_get(dev->of_node); | |
374 | ||
375 | while(np) { | |
376 | if (of_device_is_compatible(np, "U4-pcie") || | |
377 | of_device_is_compatible(np, "u4-pcie")) { | |
378 | of_node_put(np); | |
379 | return true; | |
380 | } | |
381 | np = of_get_next_parent(np); | |
382 | } | |
383 | return false; | |
384 | } | |
385 | ||
9f4a68d4 | 386 | static void pci_dma_dev_setup_dart(struct pci_dev *dev) |
8fb07c04 | 387 | { |
9f4a68d4 CH |
388 | if (dart_is_u4 && dart_device_on_pcie(&dev->dev)) |
389 | set_dma_offset(&dev->dev, DART_U4_BYPASS_BASE); | |
390 | set_iommu_table_base(&dev->dev, &iommu_table_dart); | |
391 | } | |
8fb07c04 | 392 | |
9f4a68d4 CH |
393 | static bool iommu_bypass_supported_dart(struct pci_dev *dev, u64 mask) |
394 | { | |
395 | return dart_is_u4 && | |
396 | dart_device_on_pcie(&dev->dev) && | |
397 | mask >= DMA_BIT_MASK(40); | |
8fb07c04 BH |
398 | } |
399 | ||
798248a3 | 400 | void __init iommu_init_early_dart(struct pci_controller_ops *controller_ops) |
1da177e4 LT |
401 | { |
402 | struct device_node *dn; | |
403 | ||
404 | /* Find the DART in the device-tree */ | |
405 | dn = of_find_compatible_node(NULL, "dart", "u3-dart"); | |
1beb6a7d BH |
406 | if (dn == NULL) { |
407 | dn = of_find_compatible_node(NULL, "dart", "u4-dart"); | |
408 | if (dn == NULL) | |
34c4d012 | 409 | return; /* use default direct_dma_ops */ |
1beb6a7d BH |
410 | dart_is_u4 = 1; |
411 | } | |
1da177e4 | 412 | |
8fb07c04 BH |
413 | /* Initialize the DART HW */ |
414 | if (dart_init(dn) != 0) | |
ee69049e | 415 | return; |
8fb07c04 | 416 | |
9f4a68d4 CH |
417 | /* |
418 | * U4 supports a DART bypass, we use it for 64-bit capable devices to | |
419 | * improve performance. However, that only works for devices connected | |
420 | * to the U4 own PCIe interface, not bridged through hypertransport. | |
421 | * We need the device to support at least 40 bits of addresses. | |
422 | */ | |
771e569e DA |
423 | controller_ops->dma_dev_setup = pci_dma_dev_setup_dart; |
424 | controller_ops->dma_bus_setup = pci_dma_bus_setup_dart; | |
9f4a68d4 | 425 | controller_ops->iommu_bypass_supported = iommu_bypass_supported_dart; |
771e569e | 426 | |
8fb07c04 BH |
427 | /* Setup pci_dma ops */ |
428 | set_pci_dma_ops(&dma_iommu_ops); | |
1da177e4 LT |
429 | } |
430 | ||
7e11580b | 431 | #ifdef CONFIG_PM |
7e11580b JB |
432 | static void iommu_dart_restore(void) |
433 | { | |
c40785ad | 434 | dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32)); |
7e11580b JB |
435 | dart_tlb_invalidate_all(); |
436 | } | |
437 | ||
438 | static int __init iommu_init_late_dart(void) | |
439 | { | |
7e11580b JB |
440 | if (!dart_tablebase) |
441 | return 0; | |
442 | ||
7e11580b JB |
443 | ppc_md.iommu_restore = iommu_dart_restore; |
444 | ||
445 | return 0; | |
446 | } | |
447 | ||
448 | late_initcall(iommu_init_late_dart); | |
c40785ad | 449 | #endif /* CONFIG_PM */ |