Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1beb6a7d | 2 | * arch/powerpc/sysdev/dart_iommu.c |
1da177e4 | 3 | * |
91f14480 | 4 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
1beb6a7d BH |
5 | * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>, |
6 | * IBM Corporation | |
1da177e4 LT |
7 | * |
8 | * Based on pSeries_iommu.c: | |
9 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation | |
91f14480 | 10 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
1da177e4 | 11 | * |
1beb6a7d BH |
12 | * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu. |
13 | * | |
1da177e4 | 14 | * |
1da177e4 LT |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
1beb6a7d | 19 | * |
1da177e4 LT |
20 | * This program is distributed in the hope that it will be useful, |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
1beb6a7d | 24 | * |
1da177e4 LT |
25 | * You should have received a copy of the GNU General Public License |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/init.h> |
31 | #include <linux/types.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/mm.h> | |
34 | #include <linux/spinlock.h> | |
35 | #include <linux/string.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/dma-mapping.h> | |
38 | #include <linux/vmalloc.h> | |
7e11580b | 39 | #include <linux/suspend.h> |
1da177e4 LT |
40 | #include <asm/io.h> |
41 | #include <asm/prom.h> | |
1da177e4 LT |
42 | #include <asm/iommu.h> |
43 | #include <asm/pci-bridge.h> | |
44 | #include <asm/machdep.h> | |
45 | #include <asm/abs_addr.h> | |
46 | #include <asm/cacheflush.h> | |
47 | #include <asm/lmb.h> | |
d387899f | 48 | #include <asm/ppc-pci.h> |
1da177e4 | 49 | |
9933f299 DG |
50 | #include "dart.h" |
51 | ||
1da177e4 LT |
52 | /* Physical base address and size of the DART table */ |
53 | unsigned long dart_tablebase; /* exported to htab_initialize */ | |
54 | static unsigned long dart_tablesize; | |
55 | ||
56 | /* Virtual base address of the DART table */ | |
57 | static u32 *dart_vbase; | |
7e11580b JB |
58 | #ifdef CONFIG_PM |
59 | static u32 *dart_copy; | |
60 | #endif | |
1da177e4 LT |
61 | |
62 | /* Mapped base address for the dart */ | |
6fa2ffe9 | 63 | static unsigned int __iomem *dart; |
1da177e4 LT |
64 | |
65 | /* Dummy val that entries are set to when unused */ | |
66 | static unsigned int dart_emptyval; | |
67 | ||
1beb6a7d BH |
68 | static struct iommu_table iommu_table_dart; |
69 | static int iommu_table_dart_inited; | |
1da177e4 | 70 | static int dart_dirty; |
1beb6a7d | 71 | static int dart_is_u4; |
1da177e4 LT |
72 | |
73 | #define DBG(...) | |
74 | ||
75 | static inline void dart_tlb_invalidate_all(void) | |
76 | { | |
77 | unsigned long l = 0; | |
1beb6a7d | 78 | unsigned int reg, inv_bit; |
1da177e4 LT |
79 | unsigned long limit; |
80 | ||
81 | DBG("dart: flush\n"); | |
82 | ||
83 | /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the | |
84 | * control register and wait for it to clear. | |
85 | * | |
86 | * Gotcha: Sometimes, the DART won't detect that the bit gets | |
87 | * set. If so, clear it and set it again. | |
1beb6a7d | 88 | */ |
1da177e4 LT |
89 | |
90 | limit = 0; | |
91 | ||
1beb6a7d | 92 | inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB; |
1da177e4 | 93 | retry: |
1da177e4 | 94 | l = 0; |
1beb6a7d BH |
95 | reg = DART_IN(DART_CNTL); |
96 | reg |= inv_bit; | |
97 | DART_OUT(DART_CNTL, reg); | |
98 | ||
99 | while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit)) | |
1da177e4 | 100 | l++; |
1beb6a7d | 101 | if (l == (1L << limit)) { |
1da177e4 LT |
102 | if (limit < 4) { |
103 | limit++; | |
feb76c7b OJ |
104 | reg = DART_IN(DART_CNTL); |
105 | reg &= ~inv_bit; | |
1beb6a7d | 106 | DART_OUT(DART_CNTL, reg); |
1da177e4 LT |
107 | goto retry; |
108 | } else | |
1beb6a7d | 109 | panic("DART: TLB did not flush after waiting a long " |
1da177e4 LT |
110 | "time. Buggy U3 ?"); |
111 | } | |
112 | } | |
113 | ||
feb76c7b OJ |
114 | static inline void dart_tlb_invalidate_one(unsigned long bus_rpn) |
115 | { | |
116 | unsigned int reg; | |
117 | unsigned int l, limit; | |
118 | ||
119 | reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE | | |
120 | (bus_rpn & DART_CNTL_U4_IONE_MASK); | |
121 | DART_OUT(DART_CNTL, reg); | |
122 | ||
123 | limit = 0; | |
124 | wait_more: | |
125 | l = 0; | |
126 | while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) { | |
127 | rmb(); | |
128 | l++; | |
129 | } | |
130 | ||
131 | if (l == (1L << limit)) { | |
132 | if (limit < 4) { | |
133 | limit++; | |
134 | goto wait_more; | |
135 | } else | |
136 | panic("DART: TLB did not flush after waiting a long " | |
137 | "time. Buggy U4 ?"); | |
138 | } | |
139 | } | |
140 | ||
1da177e4 LT |
141 | static void dart_flush(struct iommu_table *tbl) |
142 | { | |
eeac5c14 | 143 | mb(); |
feb76c7b | 144 | if (dart_dirty) { |
1da177e4 | 145 | dart_tlb_invalidate_all(); |
feb76c7b OJ |
146 | dart_dirty = 0; |
147 | } | |
1da177e4 LT |
148 | } |
149 | ||
1beb6a7d | 150 | static void dart_build(struct iommu_table *tbl, long index, |
1da177e4 LT |
151 | long npages, unsigned long uaddr, |
152 | enum dma_data_direction direction) | |
153 | { | |
154 | unsigned int *dp; | |
155 | unsigned int rpn; | |
feb76c7b | 156 | long l; |
1da177e4 LT |
157 | |
158 | DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr); | |
159 | ||
160 | dp = ((unsigned int*)tbl->it_base) + index; | |
1beb6a7d | 161 | |
1da177e4 LT |
162 | /* On U3, all memory is contigous, so we can move this |
163 | * out of the loop. | |
164 | */ | |
feb76c7b OJ |
165 | l = npages; |
166 | while (l--) { | |
d0035c62 | 167 | rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT; |
1da177e4 LT |
168 | |
169 | *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); | |
170 | ||
d0035c62 | 171 | uaddr += DART_PAGE_SIZE; |
1da177e4 LT |
172 | } |
173 | ||
eeac5c14 BH |
174 | /* make sure all updates have reached memory */ |
175 | mb(); | |
176 | in_be32((unsigned __iomem *)dp); | |
177 | mb(); | |
178 | ||
feb76c7b OJ |
179 | if (dart_is_u4) { |
180 | rpn = index; | |
feb76c7b OJ |
181 | while (npages--) |
182 | dart_tlb_invalidate_one(rpn++); | |
183 | } else { | |
184 | dart_dirty = 1; | |
185 | } | |
1da177e4 LT |
186 | } |
187 | ||
188 | ||
189 | static void dart_free(struct iommu_table *tbl, long index, long npages) | |
190 | { | |
191 | unsigned int *dp; | |
1beb6a7d | 192 | |
1da177e4 LT |
193 | /* We don't worry about flushing the TLB cache. The only drawback of |
194 | * not doing it is that we won't catch buggy device drivers doing | |
195 | * bad DMAs, but then no 32-bit architecture ever does either. | |
196 | */ | |
197 | ||
198 | DBG("dart: free at: %lx, %lx\n", index, npages); | |
199 | ||
200 | dp = ((unsigned int *)tbl->it_base) + index; | |
1beb6a7d | 201 | |
1da177e4 LT |
202 | while (npages--) |
203 | *(dp++) = dart_emptyval; | |
204 | } | |
205 | ||
206 | ||
109b60f0 | 207 | static int __init dart_init(struct device_node *dart_node) |
1da177e4 | 208 | { |
1da177e4 | 209 | unsigned int i; |
1beb6a7d BH |
210 | unsigned long tmp, base, size; |
211 | struct resource r; | |
1da177e4 LT |
212 | |
213 | if (dart_tablebase == 0 || dart_tablesize == 0) { | |
1beb6a7d BH |
214 | printk(KERN_INFO "DART: table not allocated, using " |
215 | "direct DMA\n"); | |
1da177e4 LT |
216 | return -ENODEV; |
217 | } | |
218 | ||
1beb6a7d BH |
219 | if (of_address_to_resource(dart_node, 0, &r)) |
220 | panic("DART: can't get register base ! "); | |
221 | ||
1da177e4 LT |
222 | /* Make sure nothing from the DART range remains in the CPU cache |
223 | * from a previous mapping that existed before the kernel took | |
224 | * over | |
225 | */ | |
1beb6a7d BH |
226 | flush_dcache_phys_range(dart_tablebase, |
227 | dart_tablebase + dart_tablesize); | |
1da177e4 LT |
228 | |
229 | /* Allocate a spare page to map all invalid DART pages. We need to do | |
230 | * that to work around what looks like a problem with the HT bridge | |
231 | * prefetching into invalid pages and corrupting data | |
232 | */ | |
d0035c62 | 233 | tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); |
1beb6a7d BH |
234 | dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & |
235 | DARTMAP_RPNMASK); | |
1da177e4 | 236 | |
1beb6a7d BH |
237 | /* Map in DART registers */ |
238 | dart = ioremap(r.start, r.end - r.start + 1); | |
1da177e4 | 239 | if (dart == NULL) |
1beb6a7d | 240 | panic("DART: Cannot map registers!"); |
1da177e4 | 241 | |
1beb6a7d | 242 | /* Map in DART table */ |
1da177e4 LT |
243 | dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize); |
244 | ||
245 | /* Fill initial table */ | |
246 | for (i = 0; i < dart_tablesize/4; i++) | |
247 | dart_vbase[i] = dart_emptyval; | |
248 | ||
249 | /* Initialize DART with table base and enable it. */ | |
1beb6a7d BH |
250 | base = dart_tablebase >> DART_PAGE_SHIFT; |
251 | size = dart_tablesize >> DART_PAGE_SHIFT; | |
252 | if (dart_is_u4) { | |
56c8eaee | 253 | size &= DART_SIZE_U4_SIZE_MASK; |
1beb6a7d BH |
254 | DART_OUT(DART_BASE_U4, base); |
255 | DART_OUT(DART_SIZE_U4, size); | |
256 | DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE); | |
257 | } else { | |
56c8eaee | 258 | size &= DART_CNTL_U3_SIZE_MASK; |
1beb6a7d BH |
259 | DART_OUT(DART_CNTL, |
260 | DART_CNTL_U3_ENABLE | | |
261 | (base << DART_CNTL_U3_BASE_SHIFT) | | |
262 | (size << DART_CNTL_U3_SIZE_SHIFT)); | |
263 | } | |
1da177e4 LT |
264 | |
265 | /* Invalidate DART to get rid of possible stale TLBs */ | |
266 | dart_tlb_invalidate_all(); | |
267 | ||
1beb6a7d BH |
268 | printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n", |
269 | dart_is_u4 ? "U4" : "U3"); | |
1da177e4 LT |
270 | |
271 | return 0; | |
272 | } | |
273 | ||
1beb6a7d | 274 | static void iommu_table_dart_setup(void) |
1da177e4 | 275 | { |
1beb6a7d BH |
276 | iommu_table_dart.it_busno = 0; |
277 | iommu_table_dart.it_offset = 0; | |
1da177e4 | 278 | /* it_size is in number of entries */ |
5d2efba6 | 279 | iommu_table_dart.it_size = dart_tablesize / sizeof(u32); |
1da177e4 LT |
280 | |
281 | /* Initialize the common IOMMU code */ | |
1beb6a7d BH |
282 | iommu_table_dart.it_base = (unsigned long)dart_vbase; |
283 | iommu_table_dart.it_index = 0; | |
284 | iommu_table_dart.it_blocksize = 1; | |
ca1588e7 | 285 | iommu_init_table(&iommu_table_dart, -1); |
1da177e4 LT |
286 | |
287 | /* Reserve the last page of the DART to avoid possible prefetch | |
288 | * past the DART mapped area | |
289 | */ | |
1beb6a7d | 290 | set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map); |
1da177e4 LT |
291 | } |
292 | ||
12d04eef | 293 | static void pci_dma_dev_setup_dart(struct pci_dev *dev) |
1da177e4 | 294 | { |
1da177e4 LT |
295 | /* We only have one iommu table on the mac for now, which makes |
296 | * things simple. Setup all PCI devices to point to this table | |
1da177e4 | 297 | */ |
12d04eef | 298 | dev->dev.archdata.dma_data = &iommu_table_dart; |
1da177e4 LT |
299 | } |
300 | ||
12d04eef | 301 | static void pci_dma_bus_setup_dart(struct pci_bus *bus) |
1da177e4 LT |
302 | { |
303 | struct device_node *dn; | |
304 | ||
1beb6a7d BH |
305 | if (!iommu_table_dart_inited) { |
306 | iommu_table_dart_inited = 1; | |
307 | iommu_table_dart_setup(); | |
1da177e4 LT |
308 | } |
309 | ||
310 | dn = pci_bus_to_OF_node(bus); | |
311 | ||
312 | if (dn) | |
1beb6a7d | 313 | PCI_DN(dn)->iommu_table = &iommu_table_dart; |
1da177e4 LT |
314 | } |
315 | ||
109b60f0 | 316 | void __init iommu_init_early_dart(void) |
1da177e4 LT |
317 | { |
318 | struct device_node *dn; | |
319 | ||
320 | /* Find the DART in the device-tree */ | |
321 | dn = of_find_compatible_node(NULL, "dart", "u3-dart"); | |
1beb6a7d BH |
322 | if (dn == NULL) { |
323 | dn = of_find_compatible_node(NULL, "dart", "u4-dart"); | |
324 | if (dn == NULL) | |
325 | goto bail; | |
326 | dart_is_u4 = 1; | |
327 | } | |
1da177e4 LT |
328 | |
329 | /* Setup low level TCE operations for the core IOMMU code */ | |
330 | ppc_md.tce_build = dart_build; | |
331 | ppc_md.tce_free = dart_free; | |
332 | ppc_md.tce_flush = dart_flush; | |
333 | ||
334 | /* Initialize the DART HW */ | |
1beb6a7d | 335 | if (dart_init(dn) == 0) { |
12d04eef BH |
336 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_dart; |
337 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_dart; | |
1da177e4 LT |
338 | |
339 | /* Setup pci_dma ops */ | |
98747770 | 340 | set_pci_dma_ops(&dma_iommu_ops); |
1beb6a7d | 341 | return; |
1da177e4 | 342 | } |
1beb6a7d BH |
343 | |
344 | bail: | |
345 | /* If init failed, use direct iommu and null setup functions */ | |
12d04eef BH |
346 | ppc_md.pci_dma_dev_setup = NULL; |
347 | ppc_md.pci_dma_bus_setup = NULL; | |
1beb6a7d BH |
348 | |
349 | /* Setup pci_dma ops */ | |
98747770 | 350 | set_pci_dma_ops(&dma_direct_ops); |
1da177e4 LT |
351 | } |
352 | ||
7e11580b JB |
353 | #ifdef CONFIG_PM |
354 | static void iommu_dart_save(void) | |
355 | { | |
356 | memcpy(dart_copy, dart_vbase, 2*1024*1024); | |
357 | } | |
358 | ||
359 | static void iommu_dart_restore(void) | |
360 | { | |
361 | memcpy(dart_vbase, dart_copy, 2*1024*1024); | |
362 | dart_tlb_invalidate_all(); | |
363 | } | |
364 | ||
365 | static int __init iommu_init_late_dart(void) | |
366 | { | |
367 | unsigned long tbasepfn; | |
368 | struct page *p; | |
369 | ||
370 | /* if no dart table exists then we won't need to save it | |
371 | * and the area has also not been reserved */ | |
372 | if (!dart_tablebase) | |
373 | return 0; | |
374 | ||
375 | tbasepfn = __pa(dart_tablebase) >> PAGE_SHIFT; | |
376 | register_nosave_region_late(tbasepfn, | |
377 | tbasepfn + ((1<<24) >> PAGE_SHIFT)); | |
378 | ||
379 | /* For suspend we need to copy the dart contents because | |
380 | * it is not part of the regular mapping (see above) and | |
381 | * thus not saved automatically. The memory for this copy | |
382 | * must be allocated early because we need 2 MB. */ | |
383 | p = alloc_pages(GFP_KERNEL, 21 - PAGE_SHIFT); | |
384 | BUG_ON(!p); | |
385 | dart_copy = page_address(p); | |
386 | ||
387 | ppc_md.iommu_save = iommu_dart_save; | |
388 | ppc_md.iommu_restore = iommu_dart_restore; | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | late_initcall(iommu_init_late_dart); | |
394 | #endif | |
1da177e4 | 395 | |
1beb6a7d | 396 | void __init alloc_dart_table(void) |
1da177e4 | 397 | { |
28897731 | 398 | /* Only reserve DART space if machine has more than 1GB of RAM |
1da177e4 | 399 | * or if requested with iommu=on on cmdline. |
28897731 OJ |
400 | * |
401 | * 1GB of RAM is picked as limit because some default devices | |
402 | * (i.e. Airport Extreme) have 30 bit address range limits. | |
1da177e4 | 403 | */ |
28897731 OJ |
404 | |
405 | if (iommu_is_off) | |
406 | return; | |
407 | ||
408 | if (!iommu_force_on && lmb_end_of_DRAM() <= 0x40000000ull) | |
1da177e4 LT |
409 | return; |
410 | ||
411 | /* 512 pages (2MB) is max DART tablesize. */ | |
412 | dart_tablesize = 1UL << 21; | |
413 | /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we | |
414 | * will blow up an entire large page anyway in the kernel mapping | |
415 | */ | |
416 | dart_tablebase = (unsigned long) | |
417 | abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L)); | |
418 | ||
1beb6a7d | 419 | printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase); |
1da177e4 | 420 | } |