Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1beb6a7d | 2 | * arch/powerpc/sysdev/dart_iommu.c |
1da177e4 | 3 | * |
91f14480 | 4 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
1beb6a7d BH |
5 | * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>, |
6 | * IBM Corporation | |
1da177e4 LT |
7 | * |
8 | * Based on pSeries_iommu.c: | |
9 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation | |
91f14480 | 10 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
1da177e4 | 11 | * |
1beb6a7d BH |
12 | * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu. |
13 | * | |
1da177e4 | 14 | * |
1da177e4 LT |
15 | * This program is free software; you can redistribute it and/or modify |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
1beb6a7d | 19 | * |
1da177e4 LT |
20 | * This program is distributed in the hope that it will be useful, |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
1beb6a7d | 24 | * |
1da177e4 LT |
25 | * You should have received a copy of the GNU General Public License |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
28 | */ | |
29 | ||
1da177e4 LT |
30 | #include <linux/init.h> |
31 | #include <linux/types.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/mm.h> | |
34 | #include <linux/spinlock.h> | |
35 | #include <linux/string.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/dma-mapping.h> | |
38 | #include <linux/vmalloc.h> | |
7e11580b | 39 | #include <linux/suspend.h> |
d9b2b2a2 | 40 | #include <linux/lmb.h> |
1da177e4 LT |
41 | #include <asm/io.h> |
42 | #include <asm/prom.h> | |
1da177e4 LT |
43 | #include <asm/iommu.h> |
44 | #include <asm/pci-bridge.h> | |
45 | #include <asm/machdep.h> | |
46 | #include <asm/abs_addr.h> | |
47 | #include <asm/cacheflush.h> | |
d387899f | 48 | #include <asm/ppc-pci.h> |
1da177e4 | 49 | |
9933f299 DG |
50 | #include "dart.h" |
51 | ||
1da177e4 LT |
52 | /* Physical base address and size of the DART table */ |
53 | unsigned long dart_tablebase; /* exported to htab_initialize */ | |
54 | static unsigned long dart_tablesize; | |
55 | ||
56 | /* Virtual base address of the DART table */ | |
57 | static u32 *dart_vbase; | |
7e11580b JB |
58 | #ifdef CONFIG_PM |
59 | static u32 *dart_copy; | |
60 | #endif | |
1da177e4 LT |
61 | |
62 | /* Mapped base address for the dart */ | |
6fa2ffe9 | 63 | static unsigned int __iomem *dart; |
1da177e4 LT |
64 | |
65 | /* Dummy val that entries are set to when unused */ | |
66 | static unsigned int dart_emptyval; | |
67 | ||
1beb6a7d BH |
68 | static struct iommu_table iommu_table_dart; |
69 | static int iommu_table_dart_inited; | |
1da177e4 | 70 | static int dart_dirty; |
1beb6a7d | 71 | static int dart_is_u4; |
1da177e4 LT |
72 | |
73 | #define DBG(...) | |
74 | ||
75 | static inline void dart_tlb_invalidate_all(void) | |
76 | { | |
77 | unsigned long l = 0; | |
1beb6a7d | 78 | unsigned int reg, inv_bit; |
1da177e4 LT |
79 | unsigned long limit; |
80 | ||
81 | DBG("dart: flush\n"); | |
82 | ||
83 | /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the | |
84 | * control register and wait for it to clear. | |
85 | * | |
86 | * Gotcha: Sometimes, the DART won't detect that the bit gets | |
87 | * set. If so, clear it and set it again. | |
1beb6a7d | 88 | */ |
1da177e4 LT |
89 | |
90 | limit = 0; | |
91 | ||
1beb6a7d | 92 | inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB; |
1da177e4 | 93 | retry: |
1da177e4 | 94 | l = 0; |
1beb6a7d BH |
95 | reg = DART_IN(DART_CNTL); |
96 | reg |= inv_bit; | |
97 | DART_OUT(DART_CNTL, reg); | |
98 | ||
99 | while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit)) | |
1da177e4 | 100 | l++; |
1beb6a7d | 101 | if (l == (1L << limit)) { |
1da177e4 LT |
102 | if (limit < 4) { |
103 | limit++; | |
feb76c7b OJ |
104 | reg = DART_IN(DART_CNTL); |
105 | reg &= ~inv_bit; | |
1beb6a7d | 106 | DART_OUT(DART_CNTL, reg); |
1da177e4 LT |
107 | goto retry; |
108 | } else | |
1beb6a7d | 109 | panic("DART: TLB did not flush after waiting a long " |
1da177e4 LT |
110 | "time. Buggy U3 ?"); |
111 | } | |
112 | } | |
113 | ||
feb76c7b OJ |
114 | static inline void dart_tlb_invalidate_one(unsigned long bus_rpn) |
115 | { | |
116 | unsigned int reg; | |
117 | unsigned int l, limit; | |
118 | ||
119 | reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE | | |
120 | (bus_rpn & DART_CNTL_U4_IONE_MASK); | |
121 | DART_OUT(DART_CNTL, reg); | |
122 | ||
123 | limit = 0; | |
124 | wait_more: | |
125 | l = 0; | |
126 | while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) { | |
127 | rmb(); | |
128 | l++; | |
129 | } | |
130 | ||
131 | if (l == (1L << limit)) { | |
132 | if (limit < 4) { | |
133 | limit++; | |
134 | goto wait_more; | |
135 | } else | |
136 | panic("DART: TLB did not flush after waiting a long " | |
137 | "time. Buggy U4 ?"); | |
138 | } | |
139 | } | |
140 | ||
1da177e4 LT |
141 | static void dart_flush(struct iommu_table *tbl) |
142 | { | |
eeac5c14 | 143 | mb(); |
feb76c7b | 144 | if (dart_dirty) { |
1da177e4 | 145 | dart_tlb_invalidate_all(); |
feb76c7b OJ |
146 | dart_dirty = 0; |
147 | } | |
1da177e4 LT |
148 | } |
149 | ||
6490c490 | 150 | static int dart_build(struct iommu_table *tbl, long index, |
1da177e4 | 151 | long npages, unsigned long uaddr, |
4f3dd8a0 MN |
152 | enum dma_data_direction direction, |
153 | struct dma_attrs *attrs) | |
1da177e4 LT |
154 | { |
155 | unsigned int *dp; | |
156 | unsigned int rpn; | |
feb76c7b | 157 | long l; |
1da177e4 LT |
158 | |
159 | DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr); | |
160 | ||
161 | dp = ((unsigned int*)tbl->it_base) + index; | |
1beb6a7d | 162 | |
1da177e4 LT |
163 | /* On U3, all memory is contigous, so we can move this |
164 | * out of the loop. | |
165 | */ | |
feb76c7b OJ |
166 | l = npages; |
167 | while (l--) { | |
d0035c62 | 168 | rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT; |
1da177e4 LT |
169 | |
170 | *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); | |
171 | ||
d0035c62 | 172 | uaddr += DART_PAGE_SIZE; |
1da177e4 LT |
173 | } |
174 | ||
eeac5c14 BH |
175 | /* make sure all updates have reached memory */ |
176 | mb(); | |
177 | in_be32((unsigned __iomem *)dp); | |
178 | mb(); | |
179 | ||
feb76c7b OJ |
180 | if (dart_is_u4) { |
181 | rpn = index; | |
feb76c7b OJ |
182 | while (npages--) |
183 | dart_tlb_invalidate_one(rpn++); | |
184 | } else { | |
185 | dart_dirty = 1; | |
186 | } | |
6490c490 | 187 | return 0; |
1da177e4 LT |
188 | } |
189 | ||
190 | ||
191 | static void dart_free(struct iommu_table *tbl, long index, long npages) | |
192 | { | |
193 | unsigned int *dp; | |
1beb6a7d | 194 | |
1da177e4 LT |
195 | /* We don't worry about flushing the TLB cache. The only drawback of |
196 | * not doing it is that we won't catch buggy device drivers doing | |
197 | * bad DMAs, but then no 32-bit architecture ever does either. | |
198 | */ | |
199 | ||
200 | DBG("dart: free at: %lx, %lx\n", index, npages); | |
201 | ||
202 | dp = ((unsigned int *)tbl->it_base) + index; | |
1beb6a7d | 203 | |
1da177e4 LT |
204 | while (npages--) |
205 | *(dp++) = dart_emptyval; | |
206 | } | |
207 | ||
208 | ||
109b60f0 | 209 | static int __init dart_init(struct device_node *dart_node) |
1da177e4 | 210 | { |
1da177e4 | 211 | unsigned int i; |
1beb6a7d BH |
212 | unsigned long tmp, base, size; |
213 | struct resource r; | |
1da177e4 LT |
214 | |
215 | if (dart_tablebase == 0 || dart_tablesize == 0) { | |
1beb6a7d BH |
216 | printk(KERN_INFO "DART: table not allocated, using " |
217 | "direct DMA\n"); | |
1da177e4 LT |
218 | return -ENODEV; |
219 | } | |
220 | ||
1beb6a7d BH |
221 | if (of_address_to_resource(dart_node, 0, &r)) |
222 | panic("DART: can't get register base ! "); | |
223 | ||
1da177e4 LT |
224 | /* Make sure nothing from the DART range remains in the CPU cache |
225 | * from a previous mapping that existed before the kernel took | |
226 | * over | |
227 | */ | |
1beb6a7d BH |
228 | flush_dcache_phys_range(dart_tablebase, |
229 | dart_tablebase + dart_tablesize); | |
1da177e4 LT |
230 | |
231 | /* Allocate a spare page to map all invalid DART pages. We need to do | |
232 | * that to work around what looks like a problem with the HT bridge | |
233 | * prefetching into invalid pages and corrupting data | |
234 | */ | |
d0035c62 | 235 | tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); |
1beb6a7d BH |
236 | dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & |
237 | DARTMAP_RPNMASK); | |
1da177e4 | 238 | |
1beb6a7d BH |
239 | /* Map in DART registers */ |
240 | dart = ioremap(r.start, r.end - r.start + 1); | |
1da177e4 | 241 | if (dart == NULL) |
1beb6a7d | 242 | panic("DART: Cannot map registers!"); |
1da177e4 | 243 | |
1beb6a7d | 244 | /* Map in DART table */ |
1da177e4 LT |
245 | dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize); |
246 | ||
247 | /* Fill initial table */ | |
248 | for (i = 0; i < dart_tablesize/4; i++) | |
249 | dart_vbase[i] = dart_emptyval; | |
250 | ||
251 | /* Initialize DART with table base and enable it. */ | |
1beb6a7d BH |
252 | base = dart_tablebase >> DART_PAGE_SHIFT; |
253 | size = dart_tablesize >> DART_PAGE_SHIFT; | |
254 | if (dart_is_u4) { | |
56c8eaee | 255 | size &= DART_SIZE_U4_SIZE_MASK; |
1beb6a7d BH |
256 | DART_OUT(DART_BASE_U4, base); |
257 | DART_OUT(DART_SIZE_U4, size); | |
258 | DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE); | |
259 | } else { | |
56c8eaee | 260 | size &= DART_CNTL_U3_SIZE_MASK; |
1beb6a7d BH |
261 | DART_OUT(DART_CNTL, |
262 | DART_CNTL_U3_ENABLE | | |
263 | (base << DART_CNTL_U3_BASE_SHIFT) | | |
264 | (size << DART_CNTL_U3_SIZE_SHIFT)); | |
265 | } | |
1da177e4 LT |
266 | |
267 | /* Invalidate DART to get rid of possible stale TLBs */ | |
268 | dart_tlb_invalidate_all(); | |
269 | ||
1beb6a7d BH |
270 | printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n", |
271 | dart_is_u4 ? "U4" : "U3"); | |
1da177e4 LT |
272 | |
273 | return 0; | |
274 | } | |
275 | ||
1beb6a7d | 276 | static void iommu_table_dart_setup(void) |
1da177e4 | 277 | { |
1beb6a7d BH |
278 | iommu_table_dart.it_busno = 0; |
279 | iommu_table_dart.it_offset = 0; | |
1da177e4 | 280 | /* it_size is in number of entries */ |
5d2efba6 | 281 | iommu_table_dart.it_size = dart_tablesize / sizeof(u32); |
1da177e4 LT |
282 | |
283 | /* Initialize the common IOMMU code */ | |
1beb6a7d BH |
284 | iommu_table_dart.it_base = (unsigned long)dart_vbase; |
285 | iommu_table_dart.it_index = 0; | |
286 | iommu_table_dart.it_blocksize = 1; | |
ca1588e7 | 287 | iommu_init_table(&iommu_table_dart, -1); |
1da177e4 LT |
288 | |
289 | /* Reserve the last page of the DART to avoid possible prefetch | |
290 | * past the DART mapped area | |
291 | */ | |
1beb6a7d | 292 | set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map); |
1da177e4 LT |
293 | } |
294 | ||
12d04eef | 295 | static void pci_dma_dev_setup_dart(struct pci_dev *dev) |
1da177e4 | 296 | { |
1da177e4 LT |
297 | /* We only have one iommu table on the mac for now, which makes |
298 | * things simple. Setup all PCI devices to point to this table | |
1da177e4 | 299 | */ |
12d04eef | 300 | dev->dev.archdata.dma_data = &iommu_table_dart; |
1da177e4 LT |
301 | } |
302 | ||
12d04eef | 303 | static void pci_dma_bus_setup_dart(struct pci_bus *bus) |
1da177e4 LT |
304 | { |
305 | struct device_node *dn; | |
306 | ||
1beb6a7d BH |
307 | if (!iommu_table_dart_inited) { |
308 | iommu_table_dart_inited = 1; | |
309 | iommu_table_dart_setup(); | |
1da177e4 LT |
310 | } |
311 | ||
312 | dn = pci_bus_to_OF_node(bus); | |
313 | ||
314 | if (dn) | |
1beb6a7d | 315 | PCI_DN(dn)->iommu_table = &iommu_table_dart; |
1da177e4 LT |
316 | } |
317 | ||
109b60f0 | 318 | void __init iommu_init_early_dart(void) |
1da177e4 LT |
319 | { |
320 | struct device_node *dn; | |
321 | ||
322 | /* Find the DART in the device-tree */ | |
323 | dn = of_find_compatible_node(NULL, "dart", "u3-dart"); | |
1beb6a7d BH |
324 | if (dn == NULL) { |
325 | dn = of_find_compatible_node(NULL, "dart", "u4-dart"); | |
326 | if (dn == NULL) | |
327 | goto bail; | |
328 | dart_is_u4 = 1; | |
329 | } | |
1da177e4 LT |
330 | |
331 | /* Setup low level TCE operations for the core IOMMU code */ | |
332 | ppc_md.tce_build = dart_build; | |
333 | ppc_md.tce_free = dart_free; | |
334 | ppc_md.tce_flush = dart_flush; | |
335 | ||
336 | /* Initialize the DART HW */ | |
1beb6a7d | 337 | if (dart_init(dn) == 0) { |
12d04eef BH |
338 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_dart; |
339 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_dart; | |
1da177e4 LT |
340 | |
341 | /* Setup pci_dma ops */ | |
98747770 | 342 | set_pci_dma_ops(&dma_iommu_ops); |
1beb6a7d | 343 | return; |
1da177e4 | 344 | } |
1beb6a7d BH |
345 | |
346 | bail: | |
347 | /* If init failed, use direct iommu and null setup functions */ | |
12d04eef BH |
348 | ppc_md.pci_dma_dev_setup = NULL; |
349 | ppc_md.pci_dma_bus_setup = NULL; | |
1beb6a7d BH |
350 | |
351 | /* Setup pci_dma ops */ | |
98747770 | 352 | set_pci_dma_ops(&dma_direct_ops); |
1da177e4 LT |
353 | } |
354 | ||
7e11580b JB |
355 | #ifdef CONFIG_PM |
356 | static void iommu_dart_save(void) | |
357 | { | |
358 | memcpy(dart_copy, dart_vbase, 2*1024*1024); | |
359 | } | |
360 | ||
361 | static void iommu_dart_restore(void) | |
362 | { | |
363 | memcpy(dart_vbase, dart_copy, 2*1024*1024); | |
364 | dart_tlb_invalidate_all(); | |
365 | } | |
366 | ||
367 | static int __init iommu_init_late_dart(void) | |
368 | { | |
369 | unsigned long tbasepfn; | |
370 | struct page *p; | |
371 | ||
372 | /* if no dart table exists then we won't need to save it | |
373 | * and the area has also not been reserved */ | |
374 | if (!dart_tablebase) | |
375 | return 0; | |
376 | ||
377 | tbasepfn = __pa(dart_tablebase) >> PAGE_SHIFT; | |
378 | register_nosave_region_late(tbasepfn, | |
379 | tbasepfn + ((1<<24) >> PAGE_SHIFT)); | |
380 | ||
381 | /* For suspend we need to copy the dart contents because | |
382 | * it is not part of the regular mapping (see above) and | |
383 | * thus not saved automatically. The memory for this copy | |
384 | * must be allocated early because we need 2 MB. */ | |
385 | p = alloc_pages(GFP_KERNEL, 21 - PAGE_SHIFT); | |
386 | BUG_ON(!p); | |
387 | dart_copy = page_address(p); | |
388 | ||
389 | ppc_md.iommu_save = iommu_dart_save; | |
390 | ppc_md.iommu_restore = iommu_dart_restore; | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
395 | late_initcall(iommu_init_late_dart); | |
396 | #endif | |
1da177e4 | 397 | |
1beb6a7d | 398 | void __init alloc_dart_table(void) |
1da177e4 | 399 | { |
28897731 | 400 | /* Only reserve DART space if machine has more than 1GB of RAM |
1da177e4 | 401 | * or if requested with iommu=on on cmdline. |
28897731 OJ |
402 | * |
403 | * 1GB of RAM is picked as limit because some default devices | |
404 | * (i.e. Airport Extreme) have 30 bit address range limits. | |
1da177e4 | 405 | */ |
28897731 OJ |
406 | |
407 | if (iommu_is_off) | |
408 | return; | |
409 | ||
410 | if (!iommu_force_on && lmb_end_of_DRAM() <= 0x40000000ull) | |
1da177e4 LT |
411 | return; |
412 | ||
413 | /* 512 pages (2MB) is max DART tablesize. */ | |
414 | dart_tablesize = 1UL << 21; | |
415 | /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we | |
416 | * will blow up an entire large page anyway in the kernel mapping | |
417 | */ | |
418 | dart_tablebase = (unsigned long) | |
419 | abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L)); | |
420 | ||
1beb6a7d | 421 | printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase); |
1da177e4 | 422 | } |