[linux-block.git] / arch / powerpc / sysdev / dart_iommu.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * arch/powerpc/sysdev/dart_iommu.c
 *
 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
 * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>,
 *                    IBM Corporation
 *
 * Based on pSeries_iommu.c:
 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
 *
 * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu.
 */

#include <linux/init.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/vmalloc.h>
#include <linux/suspend.h>
#include <linux/memblock.h>
#include <linux/gfp.h>
#include <linux/kmemleak.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/iommu.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
#include <asm/cacheflush.h>
#include <asm/ppc-pci.h>

#include "dart.h"

/* DART table address and size */
static u32 *dart_tablebase;
static unsigned long dart_tablesize;

/* Mapped base address for the dart */
static unsigned int __iomem *dart;

/* Dummy val that entries are set to when unused */
static unsigned int dart_emptyval;

static struct iommu_table iommu_table_dart;
static int iommu_table_dart_inited;
static int dart_dirty;
static int dart_is_u4;

#define DART_U4_BYPASS_BASE	0x8000000000ull

#define DBG(...)

static DEFINE_SPINLOCK(invalidate_lock);

static inline void dart_tlb_invalidate_all(void)
{
	unsigned long l = 0;
	unsigned int reg, inv_bit;
	unsigned long limit;
	unsigned long flags;

	spin_lock_irqsave(&invalidate_lock, flags);

	DBG("dart: flush\n");

	/* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the
	 * control register and wait for it to clear.
	 *
	 * Gotcha: Sometimes, the DART won't detect that the bit gets
	 * set. If so, clear it and set it again.
	 */

	limit = 0;

	inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB;
retry:
	l = 0;
	reg = DART_IN(DART_CNTL);
	reg |= inv_bit;
	DART_OUT(DART_CNTL, reg);

	while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit))
		l++;
	if (l == (1L << limit)) {
		if (limit < 4) {
			limit++;
			reg = DART_IN(DART_CNTL);
			reg &= ~inv_bit;
			DART_OUT(DART_CNTL, reg);
			goto retry;
		} else
			panic("DART: TLB did not flush after waiting a long "
			      "time. Buggy U3 ?");
	}

	spin_unlock_irqrestore(&invalidate_lock, flags);
}

static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
{
	unsigned int reg;
	unsigned int l, limit;
	unsigned long flags;

	spin_lock_irqsave(&invalidate_lock, flags);

	reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
		(bus_rpn & DART_CNTL_U4_IONE_MASK);
	DART_OUT(DART_CNTL, reg);

	limit = 0;
wait_more:
	l = 0;
	while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
		rmb();
		l++;
	}

	if (l == (1L << limit)) {
		if (limit < 4) {
			limit++;
			goto wait_more;
		} else
			panic("DART: TLB did not flush after waiting a long "
			      "time. Buggy U4 ?");
	}

	spin_unlock_irqrestore(&invalidate_lock, flags);
}

static void dart_cache_sync(unsigned int *base, unsigned int count)
{
	/*
	 * We add 1 to the number of entries to flush, following a
	 * comment in Darwin indicating that the memory controller
	 * can prefetch unmapped memory under some circumstances.
	 */
	unsigned long start = (unsigned long)base;
	unsigned long end = start + (count + 1) * sizeof(unsigned int);
	unsigned int tmp;

	/* Perform a standard cache flush */
	flush_dcache_range(start, end);

	/*
	 * Perform the sequence described in the CPC925 manual to
	 * ensure all the data gets to a point the cache incoherent
	 * DART hardware will see.
	 */
	asm volatile(" sync;"
		     " isync;"
		     " dcbf 0,%1;"
		     " sync;"
		     " isync;"
		     " lwz %0,0(%1);"
		     " isync" : "=r" (tmp) : "r" (end) : "memory");
}

static void dart_flush(struct iommu_table *tbl)
{
	mb();
	if (dart_dirty) {
		dart_tlb_invalidate_all();
		dart_dirty = 0;
	}
}

static int dart_build(struct iommu_table *tbl, long index,
		       long npages, unsigned long uaddr,
		       enum dma_data_direction direction,
		       unsigned long attrs)
{
	unsigned int *dp, *orig_dp;
	unsigned int rpn;
	long l;

	DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);

	orig_dp = dp = ((unsigned int*)tbl->it_base) + index;

	/* On U3, all memory is contiguous, so we can move this
	 * out of the loop.
	 */
	l = npages;
	while (l--) {
		rpn = __pa(uaddr) >> DART_PAGE_SHIFT;

		*(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);

		uaddr += DART_PAGE_SIZE;
	}
	dart_cache_sync(orig_dp, npages);

	if (dart_is_u4) {
		rpn = index;
		while (npages--)
			dart_tlb_invalidate_one(rpn++);
	} else {
		dart_dirty = 1;
	}
	return 0;
}


static void dart_free(struct iommu_table *tbl, long index, long npages)
{
	unsigned int *dp, *orig_dp;
	long orig_npages = npages;

	/* We don't worry about flushing the TLB cache. The only drawback of
	 * not doing it is that we won't catch buggy device drivers doing
	 * bad DMAs, but then no 32-bit architecture ever does either.
	 */

	DBG("dart: free at: %lx, %lx\n", index, npages);

	orig_dp = dp  = ((unsigned int *)tbl->it_base) + index;

	while (npages--)
		*(dp++) = dart_emptyval;

	dart_cache_sync(orig_dp, orig_npages);
}

static void allocate_dart(void)
{
	unsigned long tmp;

	/* 512 pages (2MB) is max DART tablesize. */
	dart_tablesize = 1UL << 21;

	/*
	 * 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
	 * will blow up an entire large page anyway in the kernel mapping.
	 */
	dart_tablebase = memblock_alloc_try_nid_raw(SZ_16M, SZ_16M,
					MEMBLOCK_LOW_LIMIT, SZ_2G,
					NUMA_NO_NODE);
	if (!dart_tablebase)
		panic("Failed to allocate 16MB below 2GB for DART table\n");

	/* There is no point scanning the DART space for leaks*/
	kmemleak_no_scan((void *)dart_tablebase);

	/* Allocate a spare page to map all invalid DART pages. We need to do
	 * that to work around what looks like a problem with the HT bridge
	 * prefetching into invalid pages and corrupting data
	 */
	tmp = memblock_phys_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
	if (!tmp)
		panic("DART: table allocation failed\n");

	dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) &
					 DARTMAP_RPNMASK);

	printk(KERN_INFO "DART table allocated at: %p\n", dart_tablebase);
}

static int __init dart_init(struct device_node *dart_node)
{
	unsigned int i;
	unsigned long base, size;
	struct resource r;

	/* IOMMU disabled by the user ? bail out */
	if (iommu_is_off)
		return -ENODEV;

	/*
	 * Only use the DART if the machine has more than 1GB of RAM
	 * or if requested with iommu=on on cmdline.
	 *
	 * 1GB of RAM is picked as limit because some default devices
	 * (i.e. Airport Extreme) have 30 bit address range limits.
	 */

	if (!iommu_force_on && memblock_end_of_DRAM() <= 0x40000000ull)
		return -ENODEV;

	/* Get DART registers */
	if (of_address_to_resource(dart_node, 0, &r))
		panic("DART: can't get register base ! ");

	/* Map in DART registers */
	dart = ioremap(r.start, resource_size(&r));
	if (dart == NULL)
		panic("DART: Cannot map registers!");

	/* Allocate the DART and dummy page */
	allocate_dart();

	/* Fill initial table */
	for (i = 0; i < dart_tablesize/4; i++)
		dart_tablebase[i] = dart_emptyval;

	/* Push to memory */
	dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32));

	/* Initialize DART with table base and enable it. */
	base = ((unsigned long)dart_tablebase) >> DART_PAGE_SHIFT;
	size = dart_tablesize >> DART_PAGE_SHIFT;
	if (dart_is_u4) {
		size &= DART_SIZE_U4_SIZE_MASK;
		DART_OUT(DART_BASE_U4, base);
		DART_OUT(DART_SIZE_U4, size);
		DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE);
	} else {
		size &= DART_CNTL_U3_SIZE_MASK;
		DART_OUT(DART_CNTL,
			 DART_CNTL_U3_ENABLE |
			 (base << DART_CNTL_U3_BASE_SHIFT) |
			 (size << DART_CNTL_U3_SIZE_SHIFT));
	}

	/* Invalidate DART to get rid of possible stale TLBs */
	dart_tlb_invalidate_all();

	printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n",
	       dart_is_u4 ? "U4" : "U3");

	return 0;
}

static struct iommu_table_ops iommu_dart_ops = {
	.set = dart_build,
	.clear = dart_free,
	.flush = dart_flush,
};

static void iommu_table_dart_setup(void)
{
	iommu_table_dart.it_busno = 0;
	iommu_table_dart.it_offset = 0;
	/* it_size is in number of entries */
	iommu_table_dart.it_size = dart_tablesize / sizeof(u32);
	iommu_table_dart.it_page_shift = IOMMU_PAGE_SHIFT_4K;

	/* Initialize the common IOMMU code */
	iommu_table_dart.it_base = (unsigned long)dart_tablebase;
	iommu_table_dart.it_index = 0;
	iommu_table_dart.it_blocksize = 1;
	iommu_table_dart.it_ops = &iommu_dart_ops;
	iommu_init_table(&iommu_table_dart, -1);

	/* Reserve the last page of the DART to avoid possible prefetch
	 * past the DART mapped area
	 */
	set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map);
}

static void pci_dma_bus_setup_dart(struct pci_bus *bus)
{
	if (!iommu_table_dart_inited) {
		iommu_table_dart_inited = 1;
		iommu_table_dart_setup();
	}
}

static bool dart_device_on_pcie(struct device *dev)
{
	struct device_node *np = of_node_get(dev->of_node);

	while(np) {
		if (of_device_is_compatible(np, "U4-pcie") ||
		    of_device_is_compatible(np, "u4-pcie")) {
			of_node_put(np);
			return true;
		}
		np = of_get_next_parent(np);
	}
	return false;
}

static void pci_dma_dev_setup_dart(struct pci_dev *dev)
{
	if (dart_is_u4 && dart_device_on_pcie(&dev->dev))
		dev->dev.archdata.dma_offset = DART_U4_BYPASS_BASE;
	set_iommu_table_base(&dev->dev, &iommu_table_dart);
}

static bool iommu_bypass_supported_dart(struct pci_dev *dev, u64 mask)
{
	return dart_is_u4 &&
		dart_device_on_pcie(&dev->dev) &&
		mask >= DMA_BIT_MASK(40);
}

void __init iommu_init_early_dart(struct pci_controller_ops *controller_ops)
{
	struct device_node *dn;

	/* Find the DART in the device-tree */
	dn = of_find_compatible_node(NULL, "dart", "u3-dart");
	if (dn == NULL) {
		dn = of_find_compatible_node(NULL, "dart", "u4-dart");
		if (dn == NULL)
			return;	/* use default direct_dma_ops */
		dart_is_u4 = 1;
	}

	/* Initialize the DART HW */
	if (dart_init(dn) != 0)
		return;

	/*
	 * U4 supports a DART bypass, we use it for 64-bit capable devices to
	 * improve performance.  However, that only works for devices connected
	 * to the U4 own PCIe interface, not bridged through hypertransport.
	 * We need the device to support at least 40 bits of addresses.
	 */
	controller_ops->dma_dev_setup = pci_dma_dev_setup_dart;
	controller_ops->dma_bus_setup = pci_dma_bus_setup_dart;
	controller_ops->iommu_bypass_supported = iommu_bypass_supported_dart;

	/* Setup pci_dma ops */
	set_pci_dma_ops(&dma_iommu_ops);
}

#ifdef CONFIG_PM
static void iommu_dart_restore(void)
{
	dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32));
	dart_tlb_invalidate_all();
}

static int __init iommu_init_late_dart(void)
{
	if (!dart_tablebase)
		return 0;

	ppc_md.iommu_restore = iommu_dart_restore;

	return 0;
}

late_initcall(iommu_init_late_dart);
#endif /* CONFIG_PM */
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4	2	/*
1beb6a7d	3	* arch/powerpc/sysdev/dart_iommu.c
1da177e4	4	*
91f14480	5	* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
1beb6a7d BH	6	* Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>,
1beb6a7d BH	7	* IBM Corporation
1da177e4 LT	8	*
	9	* Based on pSeries_iommu.c:
	10	* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
91f14480	11	* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
1da177e4	12	*
1beb6a7d	13	* Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu.
1da177e4 LT	14	*/
1da177e4 LT	15
1da177e4 LT	16	#include <linux/init.h>
1da177e4 LT	17	#include <linux/types.h>
1da177e4 LT	18	#include <linux/mm.h>
	19	#include <linux/spinlock.h>
	20	#include <linux/string.h>
	21	#include <linux/pci.h>
	22	#include <linux/dma-mapping.h>
	23	#include <linux/vmalloc.h>
7e11580b	24	#include <linux/suspend.h>
95f72d1e	25	#include <linux/memblock.h>
5a0e3ad6	26	#include <linux/gfp.h>
514c6032	27	#include <linux/kmemleak.h>
1da177e4 LT	28	#include <asm/io.h>
1da177e4 LT	29	#include <asm/prom.h>
1da177e4 LT	30	#include <asm/iommu.h>
	31	#include <asm/pci-bridge.h>
	32	#include <asm/machdep.h>
1da177e4	33	#include <asm/cacheflush.h>
d387899f	34	#include <asm/ppc-pci.h>
1da177e4	35
9933f299 DG	36	#include "dart.h"
9933f299 DG	37
c40785ad BH	38	/* DART table address and size */
c40785ad BH	39	static u32 *dart_tablebase;
1da177e4 LT	40	static unsigned long dart_tablesize;
1da177e4 LT	41
1da177e4	42	/* Mapped base address for the dart */
6fa2ffe9	43	static unsigned int __iomem *dart;
1da177e4 LT	44
	45	/* Dummy val that entries are set to when unused */
	46	static unsigned int dart_emptyval;
	47
1beb6a7d BH	48	static struct iommu_table iommu_table_dart;
1beb6a7d BH	49	static int iommu_table_dart_inited;
1da177e4	50	static int dart_dirty;
1beb6a7d	51	static int dart_is_u4;
1da177e4	52
8fb07c04 BH	53	#define DART_U4_BYPASS_BASE 0x8000000000ull
8fb07c04 BH	54
1da177e4 LT	55	#define DBG(...)
1da177e4 LT	56
d900bd73 AB	57	static DEFINE_SPINLOCK(invalidate_lock);
d900bd73 AB	58
1da177e4 LT	59	static inline void dart_tlb_invalidate_all(void)
	60	{
	61	unsigned long l = 0;
1beb6a7d	62	unsigned int reg, inv_bit;
1da177e4	63	unsigned long limit;
d900bd73 AB	64	unsigned long flags;
	65
	66	spin_lock_irqsave(&invalidate_lock, flags);
1da177e4 LT	67
	68	DBG("dart: flush\n");
	69
	70	/* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the
	71	* control register and wait for it to clear.
	72	*
	73	* Gotcha: Sometimes, the DART won't detect that the bit gets
	74	* set. If so, clear it and set it again.
1beb6a7d	75	*/
1da177e4 LT	76
	77	limit = 0;
	78
1beb6a7d	79	inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB;
1da177e4	80	retry:
1da177e4	81	l = 0;
1beb6a7d BH	82	reg = DART_IN(DART_CNTL);
	83	reg \|= inv_bit;
	84	DART_OUT(DART_CNTL, reg);
	85
	86	while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit))
1da177e4	87	l++;
1beb6a7d	88	if (l == (1L << limit)) {
1da177e4 LT	89	if (limit < 4) {
1da177e4 LT	90	limit++;
feb76c7b OJ	91	reg = DART_IN(DART_CNTL);
feb76c7b OJ	92	reg &= ~inv_bit;
1beb6a7d	93	DART_OUT(DART_CNTL, reg);
1da177e4 LT	94	goto retry;
1da177e4 LT	95	} else
1beb6a7d	96	panic("DART: TLB did not flush after waiting a long "
1da177e4 LT	97	"time. Buggy U3 ?");
1da177e4 LT	98	}
d900bd73 AB	99
d900bd73 AB	100	spin_unlock_irqrestore(&invalidate_lock, flags);
1da177e4 LT	101	}
1da177e4 LT	102
feb76c7b OJ	103	static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
	104	{
	105	unsigned int reg;
	106	unsigned int l, limit;
d900bd73 AB	107	unsigned long flags;
	108
	109	spin_lock_irqsave(&invalidate_lock, flags);
feb76c7b OJ	110
	111	reg = DART_CNTL_U4_ENABLE \| DART_CNTL_U4_IONE \|
	112	(bus_rpn & DART_CNTL_U4_IONE_MASK);
	113	DART_OUT(DART_CNTL, reg);
	114
	115	limit = 0;
	116	wait_more:
	117	l = 0;
	118	while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
	119	rmb();
	120	l++;
	121	}
	122
	123	if (l == (1L << limit)) {
	124	if (limit < 4) {
	125	limit++;
	126	goto wait_more;
	127	} else
	128	panic("DART: TLB did not flush after waiting a long "
	129	"time. Buggy U4 ?");
	130	}
d900bd73 AB	131
d900bd73 AB	132	spin_unlock_irqrestore(&invalidate_lock, flags);
feb76c7b OJ	133	}
feb76c7b OJ	134
c40785ad BH	135	static void dart_cache_sync(unsigned int *base, unsigned int count)
	136	{
	137	/*
	138	* We add 1 to the number of entries to flush, following a
	139	* comment in Darwin indicating that the memory controller
	140	* can prefetch unmapped memory under some circumstances.
	141	*/
	142	unsigned long start = (unsigned long)base;
	143	unsigned long end = start + (count + 1) * sizeof(unsigned int);
	144	unsigned int tmp;
	145
	146	/* Perform a standard cache flush */
1cfb725f	147	flush_dcache_range(start, end);
c40785ad BH	148
	149	/*
	150	* Perform the sequence described in the CPC925 manual to
	151	* ensure all the data gets to a point the cache incoherent
	152	* DART hardware will see.
	153	*/
	154	asm volatile(" sync;"
	155	" isync;"
	156	" dcbf 0,%1;"
	157	" sync;"
	158	" isync;"
	159	" lwz %0,0(%1);"
	160	" isync" : "=r" (tmp) : "r" (end) : "memory");
	161	}
	162
1da177e4 LT	163	static void dart_flush(struct iommu_table *tbl)
1da177e4 LT	164	{
eeac5c14	165	mb();
feb76c7b	166	if (dart_dirty) {
1da177e4	167	dart_tlb_invalidate_all();
feb76c7b OJ	168	dart_dirty = 0;
feb76c7b OJ	169	}
1da177e4 LT	170	}
1da177e4 LT	171
6490c490	172	static int dart_build(struct iommu_table *tbl, long index,
1da177e4	173	long npages, unsigned long uaddr,
4f3dd8a0	174	enum dma_data_direction direction,
00085f1e	175	unsigned long attrs)
1da177e4	176	{
c40785ad	177	unsigned int dp, orig_dp;
1da177e4	178	unsigned int rpn;
feb76c7b	179	long l;
1da177e4 LT	180
	181	DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
	182
c40785ad	183	orig_dp = dp = ((unsigned int*)tbl->it_base) + index;
1beb6a7d	184
af901ca1	185	/* On U3, all memory is contiguous, so we can move this
1da177e4 LT	186	* out of the loop.
1da177e4 LT	187	*/
feb76c7b OJ	188	l = npages;
feb76c7b OJ	189	while (l--) {
579468a9	190	rpn = __pa(uaddr) >> DART_PAGE_SHIFT;
1da177e4 LT	191
	192	*(dp++) = DARTMAP_VALID \| (rpn & DARTMAP_RPNMASK);
	193
d0035c62	194	uaddr += DART_PAGE_SIZE;
1da177e4	195	}
c40785ad	196	dart_cache_sync(orig_dp, npages);
eeac5c14	197
feb76c7b OJ	198	if (dart_is_u4) {
feb76c7b OJ	199	rpn = index;
feb76c7b OJ	200	while (npages--)
	201	dart_tlb_invalidate_one(rpn++);
	202	} else {
	203	dart_dirty = 1;
	204	}
6490c490	205	return 0;
1da177e4 LT	206	}
	207
	208
	209	static void dart_free(struct iommu_table *tbl, long index, long npages)
	210	{
c40785ad BH	211	unsigned int dp, orig_dp;
c40785ad BH	212	long orig_npages = npages;
1beb6a7d	213
1da177e4 LT	214	/* We don't worry about flushing the TLB cache. The only drawback of
	215	* not doing it is that we won't catch buggy device drivers doing
	216	* bad DMAs, but then no 32-bit architecture ever does either.
	217	*/
	218
	219	DBG("dart: free at: %lx, %lx\n", index, npages);
	220
c40785ad	221	orig_dp = dp = ((unsigned int *)tbl->it_base) + index;
1beb6a7d	222
1da177e4 LT	223	while (npages--)
1da177e4 LT	224	*(dp++) = dart_emptyval;
1da177e4	225
c40785ad BH	226	dart_cache_sync(orig_dp, orig_npages);
c40785ad BH	227	}
1da177e4	228
c40785ad	229	static void allocate_dart(void)
1da177e4	230	{
c40785ad	231	unsigned long tmp;
1da177e4	232
c40785ad BH	233	/* 512 pages (2MB) is max DART tablesize. */
c40785ad BH	234	dart_tablesize = 1UL << 21;
1beb6a7d	235
c40785ad BH	236	/*
	237	* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
	238	* will blow up an entire large page anyway in the kernel mapping.
1da177e4	239	*/
f806714f MR	240	dart_tablebase = memblock_alloc_try_nid_raw(SZ_16M, SZ_16M,
	241	MEMBLOCK_LOW_LIMIT, SZ_2G,
	242	NUMA_NO_NODE);
	243	if (!dart_tablebase)
	244	panic("Failed to allocate 16MB below 2GB for DART table\n");
c40785ad BH	245
	246	/* There is no point scanning the DART space for leaks*/
	247	kmemleak_no_scan((void *)dart_tablebase);
1da177e4 LT	248
	249	/* Allocate a spare page to map all invalid DART pages. We need to do
	250	* that to work around what looks like a problem with the HT bridge
	251	* prefetching into invalid pages and corrupting data
	252	*/
9a8dd708	253	tmp = memblock_phys_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
ecc3e771 MR	254	if (!tmp)
	255	panic("DART: table allocation failed\n");
	256
1beb6a7d BH	257	dart_emptyval = DARTMAP_VALID \| ((tmp >> DART_PAGE_SHIFT) &
1beb6a7d BH	258	DARTMAP_RPNMASK);
1da177e4	259
c40785ad BH	260	printk(KERN_INFO "DART table allocated at: %p\n", dart_tablebase);
	261	}
	262
	263	static int __init dart_init(struct device_node *dart_node)
	264	{
	265	unsigned int i;
	266	unsigned long base, size;
	267	struct resource r;
	268
	269	/* IOMMU disabled by the user ? bail out */
	270	if (iommu_is_off)
	271	return -ENODEV;
	272
	273	/*
	274	* Only use the DART if the machine has more than 1GB of RAM
	275	* or if requested with iommu=on on cmdline.
	276	*
	277	* 1GB of RAM is picked as limit because some default devices
	278	* (i.e. Airport Extreme) have 30 bit address range limits.
	279	*/
	280
	281	if (!iommu_force_on && memblock_end_of_DRAM() <= 0x40000000ull)
	282	return -ENODEV;
	283
	284	/* Get DART registers */
	285	if (of_address_to_resource(dart_node, 0, &r))
	286	panic("DART: can't get register base ! ");
	287
1beb6a7d	288	/* Map in DART registers */
28f65c11	289	dart = ioremap(r.start, resource_size(&r));
1da177e4	290	if (dart == NULL)
1beb6a7d	291	panic("DART: Cannot map registers!");
1da177e4	292
c40785ad BH	293	/* Allocate the DART and dummy page */
c40785ad BH	294	allocate_dart();
1da177e4 LT	295
	296	/* Fill initial table */
	297	for (i = 0; i < dart_tablesize/4; i++)
c40785ad BH	298	dart_tablebase[i] = dart_emptyval;
	299
	300	/* Push to memory */
	301	dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32));
1da177e4 LT	302
1da177e4 LT	303	/* Initialize DART with table base and enable it. */
c40785ad	304	base = ((unsigned long)dart_tablebase) >> DART_PAGE_SHIFT;
1beb6a7d BH	305	size = dart_tablesize >> DART_PAGE_SHIFT;
1beb6a7d BH	306	if (dart_is_u4) {
56c8eaee	307	size &= DART_SIZE_U4_SIZE_MASK;
1beb6a7d BH	308	DART_OUT(DART_BASE_U4, base);
	309	DART_OUT(DART_SIZE_U4, size);
	310	DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE);
	311	} else {
56c8eaee	312	size &= DART_CNTL_U3_SIZE_MASK;
1beb6a7d BH	313	DART_OUT(DART_CNTL,
	314	DART_CNTL_U3_ENABLE \|
	315	(base << DART_CNTL_U3_BASE_SHIFT) \|
	316	(size << DART_CNTL_U3_SIZE_SHIFT));
	317	}
1da177e4 LT	318
	319	/* Invalidate DART to get rid of possible stale TLBs */
	320	dart_tlb_invalidate_all();
	321
1beb6a7d BH	322	printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n",
1beb6a7d BH	323	dart_is_u4 ? "U4" : "U3");
1da177e4 LT	324
	325	return 0;
	326	}
	327
da004c36 AK	328	static struct iommu_table_ops iommu_dart_ops = {
	329	.set = dart_build,
	330	.clear = dart_free,
	331	.flush = dart_flush,
	332	};
	333
1beb6a7d	334	static void iommu_table_dart_setup(void)
1da177e4	335	{
1beb6a7d BH	336	iommu_table_dart.it_busno = 0;
1beb6a7d BH	337	iommu_table_dart.it_offset = 0;
1da177e4	338	/* it_size is in number of entries */
5d2efba6	339	iommu_table_dart.it_size = dart_tablesize / sizeof(u32);
67bfa0ee	340	iommu_table_dart.it_page_shift = IOMMU_PAGE_SHIFT_4K;
1da177e4 LT	341
1da177e4 LT	342	/* Initialize the common IOMMU code */
c40785ad	343	iommu_table_dart.it_base = (unsigned long)dart_tablebase;
1beb6a7d BH	344	iommu_table_dart.it_index = 0;
1beb6a7d BH	345	iommu_table_dart.it_blocksize = 1;
da004c36	346	iommu_table_dart.it_ops = &iommu_dart_ops;
ca1588e7	347	iommu_init_table(&iommu_table_dart, -1);
1da177e4 LT	348
	349	/* Reserve the last page of the DART to avoid possible prefetch
	350	* past the DART mapped area
	351	*/
1beb6a7d	352	set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map);
1da177e4 LT	353	}
1da177e4 LT	354
12d04eef	355	static void pci_dma_bus_setup_dart(struct pci_bus *bus)
1da177e4	356	{
1beb6a7d BH	357	if (!iommu_table_dart_inited) {
	358	iommu_table_dart_inited = 1;
	359	iommu_table_dart_setup();
1da177e4	360	}
1da177e4 LT	361	}
1da177e4 LT	362
8fb07c04 BH	363	static bool dart_device_on_pcie(struct device *dev)
	364	{
	365	struct device_node *np = of_node_get(dev->of_node);
	366
	367	while(np) {
	368	if (of_device_is_compatible(np, "U4-pcie") \|\|
	369	of_device_is_compatible(np, "u4-pcie")) {
	370	of_node_put(np);
	371	return true;
	372	}
	373	np = of_get_next_parent(np);
	374	}
	375	return false;
	376	}
	377
9f4a68d4	378	static void pci_dma_dev_setup_dart(struct pci_dev *dev)
8fb07c04	379	{
9f4a68d4	380	if (dart_is_u4 && dart_device_on_pcie(&dev->dev))
0617fc0c	381	dev->dev.archdata.dma_offset = DART_U4_BYPASS_BASE;
9f4a68d4 CH	382	set_iommu_table_base(&dev->dev, &iommu_table_dart);
9f4a68d4 CH	383	}
8fb07c04	384
9f4a68d4 CH	385	static bool iommu_bypass_supported_dart(struct pci_dev *dev, u64 mask)
	386	{
	387	return dart_is_u4 &&
	388	dart_device_on_pcie(&dev->dev) &&
	389	mask >= DMA_BIT_MASK(40);
8fb07c04 BH	390	}
8fb07c04 BH	391
798248a3	392	void __init iommu_init_early_dart(struct pci_controller_ops *controller_ops)
1da177e4 LT	393	{
	394	struct device_node *dn;
	395
	396	/* Find the DART in the device-tree */
	397	dn = of_find_compatible_node(NULL, "dart", "u3-dart");
1beb6a7d BH	398	if (dn == NULL) {
	399	dn = of_find_compatible_node(NULL, "dart", "u4-dart");
	400	if (dn == NULL)
34c4d012	401	return; /* use default direct_dma_ops */
1beb6a7d BH	402	dart_is_u4 = 1;
1beb6a7d BH	403	}
1da177e4	404
8fb07c04 BH	405	/* Initialize the DART HW */
8fb07c04 BH	406	if (dart_init(dn) != 0)
ee69049e	407	return;
8fb07c04	408
9f4a68d4 CH	409	/*
	410	* U4 supports a DART bypass, we use it for 64-bit capable devices to
	411	* improve performance. However, that only works for devices connected
	412	* to the U4 own PCIe interface, not bridged through hypertransport.
	413	* We need the device to support at least 40 bits of addresses.
	414	*/
771e569e DA	415	controller_ops->dma_dev_setup = pci_dma_dev_setup_dart;
771e569e DA	416	controller_ops->dma_bus_setup = pci_dma_bus_setup_dart;
9f4a68d4	417	controller_ops->iommu_bypass_supported = iommu_bypass_supported_dart;
771e569e	418
8fb07c04 BH	419	/* Setup pci_dma ops */
8fb07c04 BH	420	set_pci_dma_ops(&dma_iommu_ops);
1da177e4 LT	421	}
1da177e4 LT	422
7e11580b	423	#ifdef CONFIG_PM
7e11580b JB	424	static void iommu_dart_restore(void)
7e11580b JB	425	{
c40785ad	426	dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32));
7e11580b JB	427	dart_tlb_invalidate_all();
	428	}
	429
	430	static int __init iommu_init_late_dart(void)
	431	{
7e11580b JB	432	if (!dart_tablebase)
	433	return 0;
	434
7e11580b JB	435	ppc_md.iommu_restore = iommu_dart_restore;
	436
	437	return 0;
	438	}
	439
	440	late_initcall(iommu_init_late_dart);
c40785ad	441	#endif /* CONFIG_PM */