[linux-2.6-block.git] / arch / powerpc / sysdev / cpm_common.c

/*
 * Common CPM code
 *
 * Author: Scott Wood <scottwood@freescale.com>
 *
 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
 *
 * Some parts derived from commproc.c/cpm2_common.c, which is:
 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
 * 2006 (c) MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/of_device.h>
#include <linux/spinlock.h>
#include <linux/export.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/slab.h>

#include <asm/udbg.h>
#include <asm/io.h>
#include <asm/cpm.h>
#include <asm/fixmap.h>
#include <soc/fsl/qe/qe.h>

#include <mm/mmu_decl.h>

#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
#include <linux/of_gpio.h>
#endif

#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
static u32 __iomem *cpm_udbg_txdesc;
static u8 __iomem *cpm_udbg_txbuf;

static void udbg_putc_cpm(char c)
{
	if (c == '\n')
		udbg_putc_cpm('\r');

	while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
		;

	out_8(cpm_udbg_txbuf, c);
	out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
}

void __init udbg_init_cpm(void)
{
#ifdef CONFIG_PPC_8xx
	cpm_udbg_txdesc = (u32 __iomem __force *)
			  (CONFIG_PPC_EARLY_DEBUG_CPM_ADDR - PHYS_IMMR_BASE +
			   VIRT_IMMR_BASE);
	cpm_udbg_txbuf = (u8 __iomem __force *)
			 (in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE +
			  VIRT_IMMR_BASE);
#else
	cpm_udbg_txdesc = (u32 __iomem __force *)
			  CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
	cpm_udbg_txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
#endif

	if (cpm_udbg_txdesc) {
#ifdef CONFIG_CPM2
		setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
#endif
		udbg_putc = udbg_putc_cpm;
	}
}
#endif

#if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)

struct cpm2_ioports {
	u32 dir, par, sor, odr, dat;
	u32 res[3];
};

struct cpm2_gpio32_chip {
	struct of_mm_gpio_chip mm_gc;
	spinlock_t lock;

	/* shadowed data register to clear/set bits safely */
	u32 cpdata;
};

static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
{
	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;

	cpm2_gc->cpdata = in_be32(&iop->dat);
}

static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	u32 pin_mask;

	pin_mask = 1 << (31 - gpio);

	return !!(in_be32(&iop->dat) & pin_mask);
}

static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
	int value)
{
	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;

	if (value)
		cpm2_gc->cpdata |= pin_mask;
	else
		cpm2_gc->cpdata &= ~pin_mask;

	out_be32(&iop->dat, cpm2_gc->cpdata);
}

static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
	unsigned long flags;
	u32 pin_mask = 1 << (31 - gpio);

	spin_lock_irqsave(&cpm2_gc->lock, flags);

	__cpm2_gpio32_set(mm_gc, pin_mask, value);

	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
}

static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	unsigned long flags;
	u32 pin_mask = 1 << (31 - gpio);

	spin_lock_irqsave(&cpm2_gc->lock, flags);

	setbits32(&iop->dir, pin_mask);
	__cpm2_gpio32_set(mm_gc, pin_mask, val);

	spin_unlock_irqrestore(&cpm2_gc->lock, flags);

	return 0;
}

static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	unsigned long flags;
	u32 pin_mask = 1 << (31 - gpio);

	spin_lock_irqsave(&cpm2_gc->lock, flags);

	clrbits32(&iop->dir, pin_mask);

	spin_unlock_irqrestore(&cpm2_gc->lock, flags);

	return 0;
}

int cpm2_gpiochip_add32(struct device_node *np)
{
	struct cpm2_gpio32_chip *cpm2_gc;
	struct of_mm_gpio_chip *mm_gc;
	struct gpio_chip *gc;

	cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
	if (!cpm2_gc)
		return -ENOMEM;

	spin_lock_init(&cpm2_gc->lock);

	mm_gc = &cpm2_gc->mm_gc;
	gc = &mm_gc->gc;

	mm_gc->save_regs = cpm2_gpio32_save_regs;
	gc->ngpio = 32;
	gc->direction_input = cpm2_gpio32_dir_in;
	gc->direction_output = cpm2_gpio32_dir_out;
	gc->get = cpm2_gpio32_get;
	gc->set = cpm2_gpio32_set;

	return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc);
}
#endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
Commit	Line	Data
c374e00e SW	1	/*
	2	* Common CPM code
	3	*
	4	* Author: Scott Wood <scottwood@freescale.com>
	5	*
1661e5bd	6	* Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
c374e00e	7	*
15f8c604 SW	8	* Some parts derived from commproc.c/cpm2_common.c, which is:
	9	* Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
	10	* Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
	11	* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
	12	* 2006 (c) MontaVista Software, Inc.
	13	* Vitaly Bordug <vbordug@ru.mvista.com>
	14	*
c374e00e SW	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of version 2 of the GNU General Public License as
	17	* published by the Free Software Foundation.
	18	*/
	19
	20	#include <linux/init.h>
15f8c604	21	#include <linux/of_device.h>
e193325e	22	#include <linux/spinlock.h>
66b15db6	23	#include <linux/export.h>
e193325e	24	#include <linux/of.h>
26a2056e	25	#include <linux/of_address.h>
5a0e3ad6	26	#include <linux/slab.h>
15f8c604	27
c374e00e SW	28	#include <asm/udbg.h>
c374e00e SW	29	#include <asm/io.h>
15f8c604	30	#include <asm/cpm.h>
f86ef74e	31	#include <asm/fixmap.h>
7aa1aa6e	32	#include <soc/fsl/qe/qe.h>
15f8c604	33
c374e00e SW	34	#include <mm/mmu_decl.h>
c374e00e SW	35
e193325e LP	36	#if defined(CONFIG_CPM2) \|\| defined(CONFIG_8xx_GPIO)
	37	#include <linux/of_gpio.h>
	38	#endif
	39
c374e00e	40	#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
f86ef74e CL	41	static u32 __iomem *cpm_udbg_txdesc;
f86ef74e CL	42	static u8 __iomem *cpm_udbg_txbuf;
c374e00e SW	43
	44	static void udbg_putc_cpm(char c)
	45	{
c374e00e	46	if (c == '\n')
5e82eb33	47	udbg_putc_cpm('\r');
c374e00e SW	48
	49	while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
	50	;
	51
f86ef74e	52	out_8(cpm_udbg_txbuf, c);
c374e00e SW	53	out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
	54	}
	55
	56	void __init udbg_init_cpm(void)
	57	{
f86ef74e CL	58	#ifdef CONFIG_PPC_8xx
	59	cpm_udbg_txdesc = (u32 __iomem __force *)
	60	(CONFIG_PPC_EARLY_DEBUG_CPM_ADDR - PHYS_IMMR_BASE +
	61	VIRT_IMMR_BASE);
	62	cpm_udbg_txbuf = (u8 __iomem __force *)
	63	(in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE +
	64	VIRT_IMMR_BASE);
	65	#else
	66	cpm_udbg_txdesc = (u32 __iomem __force *)
	67	CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
	68	cpm_udbg_txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
	69	#endif
	70
c374e00e SW	71	if (cpm_udbg_txdesc) {
c374e00e SW	72	#ifdef CONFIG_CPM2
8d1cf34e	73	setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
c374e00e SW	74	#endif
	75	udbg_putc = udbg_putc_cpm;
	76	}
	77	}
	78	#endif
15f8c604	79
e193325e LP	80	#if defined(CONFIG_CPM2) \|\| defined(CONFIG_8xx_GPIO)
	81
	82	struct cpm2_ioports {
	83	u32 dir, par, sor, odr, dat;
	84	u32 res[3];
	85	};
	86
	87	struct cpm2_gpio32_chip {
	88	struct of_mm_gpio_chip mm_gc;
	89	spinlock_t lock;
	90
	91	/* shadowed data register to clear/set bits safely */
	92	u32 cpdata;
	93	};
	94
e193325e LP	95	static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
e193325e LP	96	{
a14a2d48	97	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
e193325e LP	98	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	99
	100	cpm2_gc->cpdata = in_be32(&iop->dat);
	101	}
	102
	103	static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
	104	{
	105	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
	106	struct cpm2_ioports __iomem *iop = mm_gc->regs;
	107	u32 pin_mask;
	108
	109	pin_mask = 1 << (31 - gpio);
	110
	111	return !!(in_be32(&iop->dat) & pin_mask);
	112	}
	113
639d6445 LP	114	static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
639d6445 LP	115	int value)
e193325e	116	{
a14a2d48	117	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
e193325e	118	struct cpm2_ioports __iomem *iop = mm_gc->regs;
e193325e LP	119
	120	if (value)
	121	cpm2_gc->cpdata \|= pin_mask;
	122	else
	123	cpm2_gc->cpdata &= ~pin_mask;
	124
	125	out_be32(&iop->dat, cpm2_gc->cpdata);
639d6445 LP	126	}
	127
	128	static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
	129	{
	130	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
a14a2d48	131	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
639d6445 LP	132	unsigned long flags;
	133	u32 pin_mask = 1 << (31 - gpio);
	134
	135	spin_lock_irqsave(&cpm2_gc->lock, flags);
	136
	137	__cpm2_gpio32_set(mm_gc, pin_mask, value);
e193325e LP	138
	139	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
	140	}
	141
	142	static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
	143	{
	144	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
a14a2d48	145	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
e193325e	146	struct cpm2_ioports __iomem *iop = mm_gc->regs;
639d6445 LP	147	unsigned long flags;
639d6445 LP	148	u32 pin_mask = 1 << (31 - gpio);
e193325e	149
639d6445	150	spin_lock_irqsave(&cpm2_gc->lock, flags);
e193325e LP	151
e193325e LP	152	setbits32(&iop->dir, pin_mask);
639d6445	153	__cpm2_gpio32_set(mm_gc, pin_mask, val);
e193325e	154
639d6445	155	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
e193325e LP	156
	157	return 0;
	158	}
	159
	160	static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
	161	{
	162	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
a14a2d48	163	struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
e193325e	164	struct cpm2_ioports __iomem *iop = mm_gc->regs;
639d6445 LP	165	unsigned long flags;
639d6445 LP	166	u32 pin_mask = 1 << (31 - gpio);
e193325e	167
639d6445	168	spin_lock_irqsave(&cpm2_gc->lock, flags);
e193325e LP	169
	170	clrbits32(&iop->dir, pin_mask);
	171
639d6445 LP	172	spin_unlock_irqrestore(&cpm2_gc->lock, flags);
639d6445 LP	173
e193325e LP	174	return 0;
	175	}
	176
	177	int cpm2_gpiochip_add32(struct device_node *np)
	178	{
	179	struct cpm2_gpio32_chip *cpm2_gc;
	180	struct of_mm_gpio_chip *mm_gc;
e193325e LP	181	struct gpio_chip *gc;
	182
	183	cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
	184	if (!cpm2_gc)
	185	return -ENOMEM;
	186
	187	spin_lock_init(&cpm2_gc->lock);
	188
	189	mm_gc = &cpm2_gc->mm_gc;
a19e3da5	190	gc = &mm_gc->gc;
e193325e LP	191
e193325e LP	192	mm_gc->save_regs = cpm2_gpio32_save_regs;
e193325e LP	193	gc->ngpio = 32;
	194	gc->direction_input = cpm2_gpio32_dir_in;
	195	gc->direction_output = cpm2_gpio32_dir_out;
	196	gc->get = cpm2_gpio32_get;
	197	gc->set = cpm2_gpio32_set;
	198
a14a2d48	199	return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc);
e193325e LP	200	}
e193325e LP	201	#endif /* CONFIG_CPM2 \|\| CONFIG_8xx_GPIO */