[linux-block.git] / arch / powerpc / sysdev / cpm2.c

/*
 * General Purpose functions for the global management of the
 * 8260 Communication Processor Module.
 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
 *	2.3.99 Updates
 *
 * 2006 (c) MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 * 	Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/*
 *
 * In addition to the individual control of the communication
 * channels, there are a few functions that globally affect the
 * communication processor.
 *
 * Buffer descriptors must be allocated from the dual ported memory
 * space.  The allocator for that is here.  When the communication
 * process is reset, we reclaim the memory available.  There is
 * currently no deallocator for this memory.
 */
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/page.h>
#include <asm/cpm2.h>
#include <asm/rheap.h>

#include <sysdev/fsl_soc.h>

cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */

/* We allocate this here because it is used almost exclusively for
 * the communication processor devices.
 */
cpm2_map_t __iomem *cpm2_immr;
EXPORT_SYMBOL(cpm2_immr);

#define CPM_MAP_SIZE	(0x40000)	/* 256k - the PQ3 reserve this amount
					   of space for CPM as it is larger
					   than on PQ2 */

void __init cpm2_reset(void)
{
#ifdef CONFIG_PPC_85xx
	cpm2_immr = ioremap(get_immrbase() + 0x80000, CPM_MAP_SIZE);
#else
	cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
#endif

	/* Tell everyone where the comm processor resides.
	 */
	cpmp = &cpm2_immr->im_cpm;

#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
	/* Reset the CPM.
	 */
	cpm_command(CPM_CR_RST, 0);
#endif
}

static DEFINE_SPINLOCK(cmd_lock);

#define MAX_CR_CMD_LOOPS        10000

int cpm_command(u32 command, u8 opcode)
{
	int i, ret;
	unsigned long flags;

	spin_lock_irqsave(&cmd_lock, flags);

	ret = 0;
	out_be32(&cpmp->cp_cpcr, command | opcode | CPM_CR_FLG);
	for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
		if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
			goto out;

	printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
	ret = -EIO;
out:
	spin_unlock_irqrestore(&cmd_lock, flags);
	return ret;
}
EXPORT_SYMBOL(cpm_command);

/* Set a baud rate generator.  This needs lots of work.  There are
 * eight BRGs, which can be connected to the CPM channels or output
 * as clocks.  The BRGs are in two different block of internal
 * memory mapped space.
 * The baud rate clock is the system clock divided by something.
 * It was set up long ago during the initial boot phase and is
 * given to us.
 * Baud rate clocks are zero-based in the driver code (as that maps
 * to port numbers).  Documentation uses 1-based numbering.
 */
void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
{
	u32 __iomem *bp;
	u32 val;

	/* This is good enough to get SMCs running.....
	*/
	if (brg < 4) {
		bp = &cpm2_immr->im_brgc1;
	} else {
		bp = &cpm2_immr->im_brgc5;
		brg -= 4;
	}
	bp += brg;
	/* Round the clock divider to the nearest integer. */
	val = (((clk * 2 / rate) - 1) & ~1) | CPM_BRG_EN | src;
	if (div16)
		val |= CPM_BRG_DIV16;

	out_be32(bp, val);
}
EXPORT_SYMBOL(__cpm2_setbrg);

int __init cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
{
	int ret = 0;
	int shift;
	int i, bits = 0;
	u32 __iomem *reg;
	u32 mask = 7;

	u8 clk_map[][3] = {
		{CPM_CLK_FCC1, CPM_BRG5, 0},
		{CPM_CLK_FCC1, CPM_BRG6, 1},
		{CPM_CLK_FCC1, CPM_BRG7, 2},
		{CPM_CLK_FCC1, CPM_BRG8, 3},
		{CPM_CLK_FCC1, CPM_CLK9, 4},
		{CPM_CLK_FCC1, CPM_CLK10, 5},
		{CPM_CLK_FCC1, CPM_CLK11, 6},
		{CPM_CLK_FCC1, CPM_CLK12, 7},
		{CPM_CLK_FCC2, CPM_BRG5, 0},
		{CPM_CLK_FCC2, CPM_BRG6, 1},
		{CPM_CLK_FCC2, CPM_BRG7, 2},
		{CPM_CLK_FCC2, CPM_BRG8, 3},
		{CPM_CLK_FCC2, CPM_CLK13, 4},
		{CPM_CLK_FCC2, CPM_CLK14, 5},
		{CPM_CLK_FCC2, CPM_CLK15, 6},
		{CPM_CLK_FCC2, CPM_CLK16, 7},
		{CPM_CLK_FCC3, CPM_BRG5, 0},
		{CPM_CLK_FCC3, CPM_BRG6, 1},
		{CPM_CLK_FCC3, CPM_BRG7, 2},
		{CPM_CLK_FCC3, CPM_BRG8, 3},
		{CPM_CLK_FCC3, CPM_CLK13, 4},
		{CPM_CLK_FCC3, CPM_CLK14, 5},
		{CPM_CLK_FCC3, CPM_CLK15, 6},
		{CPM_CLK_FCC3, CPM_CLK16, 7},
		{CPM_CLK_SCC1, CPM_BRG1, 0},
		{CPM_CLK_SCC1, CPM_BRG2, 1},
		{CPM_CLK_SCC1, CPM_BRG3, 2},
		{CPM_CLK_SCC1, CPM_BRG4, 3},
		{CPM_CLK_SCC1, CPM_CLK11, 4},
		{CPM_CLK_SCC1, CPM_CLK12, 5},
		{CPM_CLK_SCC1, CPM_CLK3, 6},
		{CPM_CLK_SCC1, CPM_CLK4, 7},
		{CPM_CLK_SCC2, CPM_BRG1, 0},
		{CPM_CLK_SCC2, CPM_BRG2, 1},
		{CPM_CLK_SCC2, CPM_BRG3, 2},
		{CPM_CLK_SCC2, CPM_BRG4, 3},
		{CPM_CLK_SCC2, CPM_CLK11, 4},
		{CPM_CLK_SCC2, CPM_CLK12, 5},
		{CPM_CLK_SCC2, CPM_CLK3, 6},
		{CPM_CLK_SCC2, CPM_CLK4, 7},
		{CPM_CLK_SCC3, CPM_BRG1, 0},
		{CPM_CLK_SCC3, CPM_BRG2, 1},
		{CPM_CLK_SCC3, CPM_BRG3, 2},
		{CPM_CLK_SCC3, CPM_BRG4, 3},
		{CPM_CLK_SCC3, CPM_CLK5, 4},
		{CPM_CLK_SCC3, CPM_CLK6, 5},
		{CPM_CLK_SCC3, CPM_CLK7, 6},
		{CPM_CLK_SCC3, CPM_CLK8, 7},
		{CPM_CLK_SCC4, CPM_BRG1, 0},
		{CPM_CLK_SCC4, CPM_BRG2, 1},
		{CPM_CLK_SCC4, CPM_BRG3, 2},
		{CPM_CLK_SCC4, CPM_BRG4, 3},
		{CPM_CLK_SCC4, CPM_CLK5, 4},
		{CPM_CLK_SCC4, CPM_CLK6, 5},
		{CPM_CLK_SCC4, CPM_CLK7, 6},
		{CPM_CLK_SCC4, CPM_CLK8, 7},
	};

	switch (target) {
	case CPM_CLK_SCC1:
		reg = &cpm2_immr->im_cpmux.cmx_scr;
		shift = 24;
		break;
	case CPM_CLK_SCC2:
		reg = &cpm2_immr->im_cpmux.cmx_scr;
		shift = 16;
		break;
	case CPM_CLK_SCC3:
		reg = &cpm2_immr->im_cpmux.cmx_scr;
		shift = 8;
		break;
	case CPM_CLK_SCC4:
		reg = &cpm2_immr->im_cpmux.cmx_scr;
		shift = 0;
		break;
	case CPM_CLK_FCC1:
		reg = &cpm2_immr->im_cpmux.cmx_fcr;
		shift = 24;
		break;
	case CPM_CLK_FCC2:
		reg = &cpm2_immr->im_cpmux.cmx_fcr;
		shift = 16;
		break;
	case CPM_CLK_FCC3:
		reg = &cpm2_immr->im_cpmux.cmx_fcr;
		shift = 8;
		break;
	default:
		printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
		return -EINVAL;
	}

	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
		if (clk_map[i][0] == target && clk_map[i][1] == clock) {
			bits = clk_map[i][2];
			break;
		}
	}
	if (i == ARRAY_SIZE(clk_map))
	    ret = -EINVAL;

	bits <<= shift;
	mask <<= shift;

	if (mode == CPM_CLK_RTX) {
		bits |= bits << 3;
		mask |= mask << 3;
	} else if (mode == CPM_CLK_RX) {
		bits <<= 3;
		mask <<= 3;
	}

	out_be32(reg, (in_be32(reg) & ~mask) | bits);

	return ret;
}

int __init cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
{
	int ret = 0;
	int shift;
	int i, bits = 0;
	u8 __iomem *reg;
	u8 mask = 3;

	u8 clk_map[][3] = {
		{CPM_CLK_SMC1, CPM_BRG1, 0},
		{CPM_CLK_SMC1, CPM_BRG7, 1},
		{CPM_CLK_SMC1, CPM_CLK7, 2},
		{CPM_CLK_SMC1, CPM_CLK9, 3},
		{CPM_CLK_SMC2, CPM_BRG2, 0},
		{CPM_CLK_SMC2, CPM_BRG8, 1},
		{CPM_CLK_SMC2, CPM_CLK4, 2},
		{CPM_CLK_SMC2, CPM_CLK15, 3},
	};

	switch (target) {
	case CPM_CLK_SMC1:
		reg = &cpm2_immr->im_cpmux.cmx_smr;
		mask = 3;
		shift = 4;
		break;
	case CPM_CLK_SMC2:
		reg = &cpm2_immr->im_cpmux.cmx_smr;
		mask = 3;
		shift = 0;
		break;
	default:
		printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
		return -EINVAL;
	}

	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
		if (clk_map[i][0] == target && clk_map[i][1] == clock) {
			bits = clk_map[i][2];
			break;
		}
	}
	if (i == ARRAY_SIZE(clk_map))
	    ret = -EINVAL;

	bits <<= shift;
	mask <<= shift;

	out_8(reg, (in_8(reg) & ~mask) | bits);

	return ret;
}

struct cpm2_ioports {
	u32 dir, par, sor, odr, dat;
	u32 res[3];
};

void __init cpm2_set_pin(int port, int pin, int flags)
{
	struct cpm2_ioports __iomem *iop =
		(struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;

	pin = 1 << (31 - pin);

	if (flags & CPM_PIN_OUTPUT)
		setbits32(&iop[port].dir, pin);
	else
		clrbits32(&iop[port].dir, pin);

	if (!(flags & CPM_PIN_GPIO))
		setbits32(&iop[port].par, pin);
	else
		clrbits32(&iop[port].par, pin);

	if (flags & CPM_PIN_SECONDARY)
		setbits32(&iop[port].sor, pin);
	else
		clrbits32(&iop[port].sor, pin);

	if (flags & CPM_PIN_OPENDRAIN)
		setbits32(&iop[port].odr, pin);
	else
		clrbits32(&iop[port].odr, pin);
}
Commit	Line	Data
b0c110b4 VB	1	/*
	2	* General Purpose functions for the global management of the
	3	* 8260 Communication Processor Module.
	4	* Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
	5	* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
	6	* 2.3.99 Updates
	7	*
	8	* 2006 (c) MontaVista Software, Inc.
	9	* Vitaly Bordug <vbordug@ru.mvista.com>
	10	* Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
	11	*
	12	* This file is licensed under the terms of the GNU General Public License
	13	* version 2. This program is licensed "as is" without any warranty of any
	14	* kind, whether express or implied.
	15	*/
	16
	17	/*
	18	*
	19	* In addition to the individual control of the communication
	20	* channels, there are a few functions that globally affect the
	21	* communication processor.
	22	*
	23	* Buffer descriptors must be allocated from the dual ported memory
	24	* space. The allocator for that is here. When the communication
	25	* process is reset, we reclaim the memory available. There is
	26	* currently no deallocator for this memory.
	27	*/
	28	#include <linux/errno.h>
	29	#include <linux/sched.h>
	30	#include <linux/kernel.h>
	31	#include <linux/param.h>
	32	#include <linux/string.h>
	33	#include <linux/mm.h>
	34	#include <linux/interrupt.h>
	35	#include <linux/module.h>
449012da SW	36	#include <linux/of.h>
449012da SW	37
b0c110b4 VB	38	#include <asm/io.h>
b0c110b4 VB	39	#include <asm/irq.h>
b0c110b4	40	#include <asm/page.h>
b0c110b4 VB	41	#include <asm/cpm2.h>
b0c110b4 VB	42	#include <asm/rheap.h>
b0c110b4 VB	43
	44	#include <sysdev/fsl_soc.h>
	45
449012da	46	cpm_cpm2_t __iomem cpmp; / Pointer to comm processor space */
b0c110b4 VB	47
	48	/* We allocate this here because it is used almost exclusively for
	49	* the communication processor devices.
	50	*/
449012da	51	cpm2_map_t __iomem *cpm2_immr;
6e27cca9	52	EXPORT_SYMBOL(cpm2_immr);
b0c110b4 VB	53
	54	#define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
	55	of space for CPM as it is larger
	56	than on PQ2 */
	57
cd2150bc	58	void __init cpm2_reset(void)
b0c110b4	59	{
449012da	60	#ifdef CONFIG_PPC_85xx
ca851c78	61	cpm2_immr = ioremap(get_immrbase() + 0x80000, CPM_MAP_SIZE);
449012da SW	62	#else
	63	cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
	64	#endif
b0c110b4	65
b0c110b4 VB	66	/* Tell everyone where the comm processor resides.
	67	*/
	68	cpmp = &cpm2_immr->im_cpm;
872a15de LP	69
	70	#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
	71	/* Reset the CPM.
	72	*/
	73	cpm_command(CPM_CR_RST, 0);
	74	#endif
b0c110b4 VB	75	}
b0c110b4 VB	76
362f9b6f JF	77	static DEFINE_SPINLOCK(cmd_lock);
	78
	79	#define MAX_CR_CMD_LOOPS 10000
	80
	81	int cpm_command(u32 command, u8 opcode)
	82	{
	83	int i, ret;
	84	unsigned long flags;
	85
	86	spin_lock_irqsave(&cmd_lock, flags);
	87
	88	ret = 0;
	89	out_be32(&cpmp->cp_cpcr, command \| opcode \| CPM_CR_FLG);
	90	for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
	91	if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
	92	goto out;
	93
e48b1b45	94	printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
362f9b6f JF	95	ret = -EIO;
	96	out:
	97	spin_unlock_irqrestore(&cmd_lock, flags);
	98	return ret;
	99	}
	100	EXPORT_SYMBOL(cpm_command);
	101
b0c110b4 VB	102	/* Set a baud rate generator. This needs lots of work. There are
	103	* eight BRGs, which can be connected to the CPM channels or output
	104	* as clocks. The BRGs are in two different block of internal
	105	* memory mapped space.
	106	* The baud rate clock is the system clock divided by something.
	107	* It was set up long ago during the initial boot phase and is
738f9dca	108	* given to us.
b0c110b4 VB	109	* Baud rate clocks are zero-based in the driver code (as that maps
	110	* to port numbers). Documentation uses 1-based numbering.
	111	*/
dddb8d31	112	void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
b0c110b4	113	{
449012da	114	u32 __iomem *bp;
dddb8d31	115	u32 val;
b0c110b4 VB	116
	117	/* This is good enough to get SMCs running.....
	118	*/
	119	if (brg < 4) {
7768716d	120	bp = &cpm2_immr->im_brgc1;
b0c110b4	121	} else {
7768716d	122	bp = &cpm2_immr->im_brgc5;
b0c110b4 VB	123	brg -= 4;
	124	}
	125	bp += brg;
7b890994 LP	126	/* Round the clock divider to the nearest integer. */
7b890994 LP	127	val = (((clk * 2 / rate) - 1) & ~1) \| CPM_BRG_EN \| src;
b0c110b4	128	if (div16)
449012da	129	val \|= CPM_BRG_DIV16;
fc8e50e3	130
449012da	131	out_be32(bp, val);
b0c110b4	132	}
dddb8d31	133	EXPORT_SYMBOL(__cpm2_setbrg);
b0c110b4	134
6c552983	135	int __init cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
d3465c92 VB	136	{
	137	int ret = 0;
	138	int shift;
	139	int i, bits = 0;
449012da	140	u32 __iomem *reg;
d3465c92	141	u32 mask = 7;
2652d4ec SW	142
2652d4ec SW	143	u8 clk_map[][3] = {
d3465c92 VB	144	{CPM_CLK_FCC1, CPM_BRG5, 0},
	145	{CPM_CLK_FCC1, CPM_BRG6, 1},
	146	{CPM_CLK_FCC1, CPM_BRG7, 2},
	147	{CPM_CLK_FCC1, CPM_BRG8, 3},
	148	{CPM_CLK_FCC1, CPM_CLK9, 4},
	149	{CPM_CLK_FCC1, CPM_CLK10, 5},
	150	{CPM_CLK_FCC1, CPM_CLK11, 6},
	151	{CPM_CLK_FCC1, CPM_CLK12, 7},
	152	{CPM_CLK_FCC2, CPM_BRG5, 0},
	153	{CPM_CLK_FCC2, CPM_BRG6, 1},
	154	{CPM_CLK_FCC2, CPM_BRG7, 2},
	155	{CPM_CLK_FCC2, CPM_BRG8, 3},
	156	{CPM_CLK_FCC2, CPM_CLK13, 4},
	157	{CPM_CLK_FCC2, CPM_CLK14, 5},
	158	{CPM_CLK_FCC2, CPM_CLK15, 6},
	159	{CPM_CLK_FCC2, CPM_CLK16, 7},
	160	{CPM_CLK_FCC3, CPM_BRG5, 0},
	161	{CPM_CLK_FCC3, CPM_BRG6, 1},
	162	{CPM_CLK_FCC3, CPM_BRG7, 2},
	163	{CPM_CLK_FCC3, CPM_BRG8, 3},
	164	{CPM_CLK_FCC3, CPM_CLK13, 4},
	165	{CPM_CLK_FCC3, CPM_CLK14, 5},
	166	{CPM_CLK_FCC3, CPM_CLK15, 6},
2652d4ec SW	167	{CPM_CLK_FCC3, CPM_CLK16, 7},
	168	{CPM_CLK_SCC1, CPM_BRG1, 0},
	169	{CPM_CLK_SCC1, CPM_BRG2, 1},
	170	{CPM_CLK_SCC1, CPM_BRG3, 2},
	171	{CPM_CLK_SCC1, CPM_BRG4, 3},
	172	{CPM_CLK_SCC1, CPM_CLK11, 4},
	173	{CPM_CLK_SCC1, CPM_CLK12, 5},
	174	{CPM_CLK_SCC1, CPM_CLK3, 6},
	175	{CPM_CLK_SCC1, CPM_CLK4, 7},
	176	{CPM_CLK_SCC2, CPM_BRG1, 0},
	177	{CPM_CLK_SCC2, CPM_BRG2, 1},
	178	{CPM_CLK_SCC2, CPM_BRG3, 2},
	179	{CPM_CLK_SCC2, CPM_BRG4, 3},
	180	{CPM_CLK_SCC2, CPM_CLK11, 4},
	181	{CPM_CLK_SCC2, CPM_CLK12, 5},
	182	{CPM_CLK_SCC2, CPM_CLK3, 6},
	183	{CPM_CLK_SCC2, CPM_CLK4, 7},
	184	{CPM_CLK_SCC3, CPM_BRG1, 0},
	185	{CPM_CLK_SCC3, CPM_BRG2, 1},
	186	{CPM_CLK_SCC3, CPM_BRG3, 2},
	187	{CPM_CLK_SCC3, CPM_BRG4, 3},
	188	{CPM_CLK_SCC3, CPM_CLK5, 4},
	189	{CPM_CLK_SCC3, CPM_CLK6, 5},
	190	{CPM_CLK_SCC3, CPM_CLK7, 6},
	191	{CPM_CLK_SCC3, CPM_CLK8, 7},
	192	{CPM_CLK_SCC4, CPM_BRG1, 0},
	193	{CPM_CLK_SCC4, CPM_BRG2, 1},
	194	{CPM_CLK_SCC4, CPM_BRG3, 2},
	195	{CPM_CLK_SCC4, CPM_BRG4, 3},
	196	{CPM_CLK_SCC4, CPM_CLK5, 4},
	197	{CPM_CLK_SCC4, CPM_CLK6, 5},
	198	{CPM_CLK_SCC4, CPM_CLK7, 6},
	199	{CPM_CLK_SCC4, CPM_CLK8, 7},
	200	};
d3465c92	201
d3465c92 VB	202	switch (target) {
d3465c92 VB	203	case CPM_CLK_SCC1:
7768716d	204	reg = &cpm2_immr->im_cpmux.cmx_scr;
d3465c92	205	shift = 24;
025306f3	206	break;
d3465c92	207	case CPM_CLK_SCC2:
7768716d	208	reg = &cpm2_immr->im_cpmux.cmx_scr;
d3465c92 VB	209	shift = 16;
	210	break;
	211	case CPM_CLK_SCC3:
7768716d	212	reg = &cpm2_immr->im_cpmux.cmx_scr;
d3465c92 VB	213	shift = 8;
	214	break;
	215	case CPM_CLK_SCC4:
7768716d	216	reg = &cpm2_immr->im_cpmux.cmx_scr;
d3465c92 VB	217	shift = 0;
	218	break;
	219	case CPM_CLK_FCC1:
7768716d	220	reg = &cpm2_immr->im_cpmux.cmx_fcr;
d3465c92 VB	221	shift = 24;
	222	break;
	223	case CPM_CLK_FCC2:
7768716d	224	reg = &cpm2_immr->im_cpmux.cmx_fcr;
d3465c92 VB	225	shift = 16;
	226	break;
	227	case CPM_CLK_FCC3:
7768716d	228	reg = &cpm2_immr->im_cpmux.cmx_fcr;
d3465c92 VB	229	shift = 8;
	230	break;
	231	default:
	232	printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
	233	return -EINVAL;
	234	}
	235
2652d4ec	236	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
d3465c92 VB	237	if (clk_map[i][0] == target && clk_map[i][1] == clock) {
	238	bits = clk_map[i][2];
	239	break;
	240	}
	241	}
2652d4ec	242	if (i == ARRAY_SIZE(clk_map))
d3465c92 VB	243	ret = -EINVAL;
	244
	245	bits <<= shift;
	246	mask <<= shift;
2652d4ec	247
1cca2d2b WO	248	if (mode == CPM_CLK_RTX) {
	249	bits \|= bits << 3;
	250	mask \|= mask << 3;
	251	} else if (mode == CPM_CLK_RX) {
	252	bits <<= 3;
	253	mask <<= 3;
	254	}
	255
d3465c92 VB	256	out_be32(reg, (in_be32(reg) & ~mask) \| bits);
d3465c92 VB	257
d3465c92 VB	258	return ret;
	259	}
	260
6c552983	261	int __init cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
2652d4ec SW	262	{
	263	int ret = 0;
	264	int shift;
	265	int i, bits = 0;
2652d4ec SW	266	u8 __iomem *reg;
	267	u8 mask = 3;
	268
	269	u8 clk_map[][3] = {
	270	{CPM_CLK_SMC1, CPM_BRG1, 0},
	271	{CPM_CLK_SMC1, CPM_BRG7, 1},
	272	{CPM_CLK_SMC1, CPM_CLK7, 2},
	273	{CPM_CLK_SMC1, CPM_CLK9, 3},
	274	{CPM_CLK_SMC2, CPM_BRG2, 0},
	275	{CPM_CLK_SMC2, CPM_BRG8, 1},
	276	{CPM_CLK_SMC2, CPM_CLK4, 2},
	277	{CPM_CLK_SMC2, CPM_CLK15, 3},
	278	};
	279
2652d4ec SW	280	switch (target) {
2652d4ec SW	281	case CPM_CLK_SMC1:
7768716d	282	reg = &cpm2_immr->im_cpmux.cmx_smr;
2652d4ec SW	283	mask = 3;
	284	shift = 4;
	285	break;
	286	case CPM_CLK_SMC2:
7768716d	287	reg = &cpm2_immr->im_cpmux.cmx_smr;
2652d4ec SW	288	mask = 3;
	289	shift = 0;
	290	break;
	291	default:
	292	printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
	293	return -EINVAL;
	294	}
	295
	296	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
	297	if (clk_map[i][0] == target && clk_map[i][1] == clock) {
	298	bits = clk_map[i][2];
	299	break;
	300	}
	301	}
	302	if (i == ARRAY_SIZE(clk_map))
	303	ret = -EINVAL;
	304
	305	bits <<= shift;
	306	mask <<= shift;
	307
	308	out_8(reg, (in_8(reg) & ~mask) \| bits);
	309
2652d4ec SW	310	return ret;
	311	}
	312
7f21f529 SW	313	struct cpm2_ioports {
	314	u32 dir, par, sor, odr, dat;
	315	u32 res[3];
	316	};
	317
6c552983	318	void __init cpm2_set_pin(int port, int pin, int flags)
7f21f529 SW	319	{
	320	struct cpm2_ioports __iomem *iop =
	321	(struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
	322
	323	pin = 1 << (31 - pin);
	324
	325	if (flags & CPM_PIN_OUTPUT)
	326	setbits32(&iop[port].dir, pin);
	327	else
	328	clrbits32(&iop[port].dir, pin);
	329
	330	if (!(flags & CPM_PIN_GPIO))
	331	setbits32(&iop[port].par, pin);
	332	else
	333	clrbits32(&iop[port].par, pin);
	334
	335	if (flags & CPM_PIN_SECONDARY)
	336	setbits32(&iop[port].sor, pin);
	337	else
	338	clrbits32(&iop[port].sor, pin);
	339
	340	if (flags & CPM_PIN_OPENDRAIN)
	341	setbits32(&iop[port].odr, pin);
	342	else
	343	clrbits32(&iop[port].odr, pin);
	344	}