[linux-2.6-block.git] / arch / powerpc / sysdev / cpm2.c

/*
 * General Purpose functions for the global management of the
 * 8260 Communication Processor Module.
 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
 *	2.3.99 Updates
 *
 * 2006 (c) MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 * 	Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/*
 *
 * In addition to the individual control of the communication
 * channels, there are a few functions that globally affect the
 * communication processor.
 *
 * Buffer descriptors must be allocated from the dual ported memory
 * space.  The allocator for that is here.  When the communication
 * process is reset, we reclaim the memory available.  There is
 * currently no deallocator for this memory.
 */
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mpc8260.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/cpm2.h>
#include <asm/rheap.h>
#include <asm/fs_pd.h>

#include <sysdev/fsl_soc.h>

#ifndef CONFIG_PPC_CPM_NEW_BINDING
static void cpm2_dpinit(void);
#endif

cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */

/* We allocate this here because it is used almost exclusively for
 * the communication processor devices.
 */
cpm2_map_t __iomem *cpm2_immr;

#define CPM_MAP_SIZE	(0x40000)	/* 256k - the PQ3 reserve this amount
					   of space for CPM as it is larger
					   than on PQ2 */

void __init cpm2_reset(void)
{
#ifdef CONFIG_PPC_85xx
	cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
#else
	cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
#endif

	/* Reclaim the DP memory for our use.
	 */
#ifdef CONFIG_PPC_CPM_NEW_BINDING
	cpm_muram_init();
#else
	cpm2_dpinit();
#endif

	/* Tell everyone where the comm processor resides.
	 */
	cpmp = &cpm2_immr->im_cpm;
}

static DEFINE_SPINLOCK(cmd_lock);

#define MAX_CR_CMD_LOOPS        10000

int cpm_command(u32 command, u8 opcode)
{
	int i, ret;
	unsigned long flags;

	spin_lock_irqsave(&cmd_lock, flags);

	ret = 0;
	out_be32(&cpmp->cp_cpcr, command | opcode | CPM_CR_FLG);
	for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
		if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
			goto out;

	printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
	ret = -EIO;
out:
	spin_unlock_irqrestore(&cmd_lock, flags);
	return ret;
}
EXPORT_SYMBOL(cpm_command);

/* Set a baud rate generator.  This needs lots of work.  There are
 * eight BRGs, which can be connected to the CPM channels or output
 * as clocks.  The BRGs are in two different block of internal
 * memory mapped space.
 * The baud rate clock is the system clock divided by something.
 * It was set up long ago during the initial boot phase and is
 * is given to us.
 * Baud rate clocks are zero-based in the driver code (as that maps
 * to port numbers).  Documentation uses 1-based numbering.
 */
#define BRG_INT_CLK	(get_brgfreq())
#define BRG_UART_CLK	(BRG_INT_CLK/16)

/* This function is used by UARTS, or anything else that uses a 16x
 * oversampled clock.
 */
void
cpm_setbrg(uint brg, uint rate)
{
	u32 __iomem *bp;

	/* This is good enough to get SMCs running.....
	*/
	if (brg < 4) {
		bp = cpm2_map_size(im_brgc1, 16);
	} else {
		bp = cpm2_map_size(im_brgc5, 16);
		brg -= 4;
	}
	bp += brg;
	out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);

	cpm2_unmap(bp);
}

/* This function is used to set high speed synchronous baud rate
 * clocks.
 */
void
cpm2_fastbrg(uint brg, uint rate, int div16)
{
	u32 __iomem *bp;
	u32 val;

	if (brg < 4) {
		bp = cpm2_map_size(im_brgc1, 16);
	} else {
		bp = cpm2_map_size(im_brgc5, 16);
		brg -= 4;
	}
	bp += brg;
	val = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
	if (div16)
		val |= CPM_BRG_DIV16;

	out_be32(bp, val);
	cpm2_unmap(bp);
}

int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
{
	int ret = 0;
	int shift;
	int i, bits = 0;
	cpmux_t __iomem *im_cpmux;
	u32 __iomem *reg;
	u32 mask = 7;

	u8 clk_map[][3] = {
		{CPM_CLK_FCC1, CPM_BRG5, 0},
		{CPM_CLK_FCC1, CPM_BRG6, 1},
		{CPM_CLK_FCC1, CPM_BRG7, 2},
		{CPM_CLK_FCC1, CPM_BRG8, 3},
		{CPM_CLK_FCC1, CPM_CLK9, 4},
		{CPM_CLK_FCC1, CPM_CLK10, 5},
		{CPM_CLK_FCC1, CPM_CLK11, 6},
		{CPM_CLK_FCC1, CPM_CLK12, 7},
		{CPM_CLK_FCC2, CPM_BRG5, 0},
		{CPM_CLK_FCC2, CPM_BRG6, 1},
		{CPM_CLK_FCC2, CPM_BRG7, 2},
		{CPM_CLK_FCC2, CPM_BRG8, 3},
		{CPM_CLK_FCC2, CPM_CLK13, 4},
		{CPM_CLK_FCC2, CPM_CLK14, 5},
		{CPM_CLK_FCC2, CPM_CLK15, 6},
		{CPM_CLK_FCC2, CPM_CLK16, 7},
		{CPM_CLK_FCC3, CPM_BRG5, 0},
		{CPM_CLK_FCC3, CPM_BRG6, 1},
		{CPM_CLK_FCC3, CPM_BRG7, 2},
		{CPM_CLK_FCC3, CPM_BRG8, 3},
		{CPM_CLK_FCC3, CPM_CLK13, 4},
		{CPM_CLK_FCC3, CPM_CLK14, 5},
		{CPM_CLK_FCC3, CPM_CLK15, 6},
		{CPM_CLK_FCC3, CPM_CLK16, 7},
		{CPM_CLK_SCC1, CPM_BRG1, 0},
		{CPM_CLK_SCC1, CPM_BRG2, 1},
		{CPM_CLK_SCC1, CPM_BRG3, 2},
		{CPM_CLK_SCC1, CPM_BRG4, 3},
		{CPM_CLK_SCC1, CPM_CLK11, 4},
		{CPM_CLK_SCC1, CPM_CLK12, 5},
		{CPM_CLK_SCC1, CPM_CLK3, 6},
		{CPM_CLK_SCC1, CPM_CLK4, 7},
		{CPM_CLK_SCC2, CPM_BRG1, 0},
		{CPM_CLK_SCC2, CPM_BRG2, 1},
		{CPM_CLK_SCC2, CPM_BRG3, 2},
		{CPM_CLK_SCC2, CPM_BRG4, 3},
		{CPM_CLK_SCC2, CPM_CLK11, 4},
		{CPM_CLK_SCC2, CPM_CLK12, 5},
		{CPM_CLK_SCC2, CPM_CLK3, 6},
		{CPM_CLK_SCC2, CPM_CLK4, 7},
		{CPM_CLK_SCC3, CPM_BRG1, 0},
		{CPM_CLK_SCC3, CPM_BRG2, 1},
		{CPM_CLK_SCC3, CPM_BRG3, 2},
		{CPM_CLK_SCC3, CPM_BRG4, 3},
		{CPM_CLK_SCC3, CPM_CLK5, 4},
		{CPM_CLK_SCC3, CPM_CLK6, 5},
		{CPM_CLK_SCC3, CPM_CLK7, 6},
		{CPM_CLK_SCC3, CPM_CLK8, 7},
		{CPM_CLK_SCC4, CPM_BRG1, 0},
		{CPM_CLK_SCC4, CPM_BRG2, 1},
		{CPM_CLK_SCC4, CPM_BRG3, 2},
		{CPM_CLK_SCC4, CPM_BRG4, 3},
		{CPM_CLK_SCC4, CPM_CLK5, 4},
		{CPM_CLK_SCC4, CPM_CLK6, 5},
		{CPM_CLK_SCC4, CPM_CLK7, 6},
		{CPM_CLK_SCC4, CPM_CLK8, 7},
	};

	im_cpmux = cpm2_map(im_cpmux);

	switch (target) {
	case CPM_CLK_SCC1:
		reg = &im_cpmux->cmx_scr;
		shift = 24;
	case CPM_CLK_SCC2:
		reg = &im_cpmux->cmx_scr;
		shift = 16;
		break;
	case CPM_CLK_SCC3:
		reg = &im_cpmux->cmx_scr;
		shift = 8;
		break;
	case CPM_CLK_SCC4:
		reg = &im_cpmux->cmx_scr;
		shift = 0;
		break;
	case CPM_CLK_FCC1:
		reg = &im_cpmux->cmx_fcr;
		shift = 24;
		break;
	case CPM_CLK_FCC2:
		reg = &im_cpmux->cmx_fcr;
		shift = 16;
		break;
	case CPM_CLK_FCC3:
		reg = &im_cpmux->cmx_fcr;
		shift = 8;
		break;
	default:
		printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
		return -EINVAL;
	}

	if (mode == CPM_CLK_RX)
		shift += 3;

	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
		if (clk_map[i][0] == target && clk_map[i][1] == clock) {
			bits = clk_map[i][2];
			break;
		}
	}
	if (i == ARRAY_SIZE(clk_map))
	    ret = -EINVAL;

	bits <<= shift;
	mask <<= shift;

	out_be32(reg, (in_be32(reg) & ~mask) | bits);

	cpm2_unmap(im_cpmux);
	return ret;
}

int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
{
	int ret = 0;
	int shift;
	int i, bits = 0;
	cpmux_t __iomem *im_cpmux;
	u8 __iomem *reg;
	u8 mask = 3;

	u8 clk_map[][3] = {
		{CPM_CLK_SMC1, CPM_BRG1, 0},
		{CPM_CLK_SMC1, CPM_BRG7, 1},
		{CPM_CLK_SMC1, CPM_CLK7, 2},
		{CPM_CLK_SMC1, CPM_CLK9, 3},
		{CPM_CLK_SMC2, CPM_BRG2, 0},
		{CPM_CLK_SMC2, CPM_BRG8, 1},
		{CPM_CLK_SMC2, CPM_CLK4, 2},
		{CPM_CLK_SMC2, CPM_CLK15, 3},
	};

	im_cpmux = cpm2_map(im_cpmux);

	switch (target) {
	case CPM_CLK_SMC1:
		reg = &im_cpmux->cmx_smr;
		mask = 3;
		shift = 4;
		break;
	case CPM_CLK_SMC2:
		reg = &im_cpmux->cmx_smr;
		mask = 3;
		shift = 0;
		break;
	default:
		printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
		return -EINVAL;
	}

	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
		if (clk_map[i][0] == target && clk_map[i][1] == clock) {
			bits = clk_map[i][2];
			break;
		}
	}
	if (i == ARRAY_SIZE(clk_map))
	    ret = -EINVAL;

	bits <<= shift;
	mask <<= shift;

	out_8(reg, (in_8(reg) & ~mask) | bits);

	cpm2_unmap(im_cpmux);
	return ret;
}

#ifndef CONFIG_PPC_CPM_NEW_BINDING
/*
 * dpalloc / dpfree bits.
 */
static spinlock_t cpm_dpmem_lock;
/* 16 blocks should be enough to satisfy all requests
 * until the memory subsystem goes up... */
static rh_block_t cpm_boot_dpmem_rh_block[16];
static rh_info_t cpm_dpmem_info;
static u8 __iomem *im_dprambase;

static void cpm2_dpinit(void)
{
	spin_lock_init(&cpm_dpmem_lock);

	/* initialize the info header */
	rh_init(&cpm_dpmem_info, 1,
			sizeof(cpm_boot_dpmem_rh_block) /
			sizeof(cpm_boot_dpmem_rh_block[0]),
			cpm_boot_dpmem_rh_block);

	im_dprambase = cpm2_immr;

	/* Attach the usable dpmem area */
	/* XXX: This is actually crap. CPM_DATAONLY_BASE and
	 * CPM_DATAONLY_SIZE is only a subset of the available dpram. It
	 * varies with the processor and the microcode patches activated.
	 * But the following should be at least safe.
	 */
	rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
}

/* This function returns an index into the DPRAM area.
 */
unsigned long cpm_dpalloc(uint size, uint align)
{
	unsigned long start;
	unsigned long flags;

	spin_lock_irqsave(&cpm_dpmem_lock, flags);
	cpm_dpmem_info.alignment = align;
	start = rh_alloc(&cpm_dpmem_info, size, "commproc");
	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);

	return (uint)start;
}
EXPORT_SYMBOL(cpm_dpalloc);

int cpm_dpfree(unsigned long offset)
{
	int ret;
	unsigned long flags;

	spin_lock_irqsave(&cpm_dpmem_lock, flags);
	ret = rh_free(&cpm_dpmem_info, offset);
	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);

	return ret;
}
EXPORT_SYMBOL(cpm_dpfree);

/* not sure if this is ever needed */
unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
{
	unsigned long start;
	unsigned long flags;

	spin_lock_irqsave(&cpm_dpmem_lock, flags);
	cpm_dpmem_info.alignment = align;
	start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);

	return start;
}
EXPORT_SYMBOL(cpm_dpalloc_fixed);

void cpm_dpdump(void)
{
	rh_dump(&cpm_dpmem_info);
}
EXPORT_SYMBOL(cpm_dpdump);

void *cpm_dpram_addr(unsigned long offset)
{
	return (void *)(im_dprambase + offset);
}
EXPORT_SYMBOL(cpm_dpram_addr);
#endif /* !CONFIG_PPC_CPM_NEW_BINDING */

struct cpm2_ioports {
	u32 dir, par, sor, odr, dat;
	u32 res[3];
};

void cpm2_set_pin(int port, int pin, int flags)
{
	struct cpm2_ioports __iomem *iop =
		(struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;

	pin = 1 << (31 - pin);

	if (flags & CPM_PIN_OUTPUT)
		setbits32(&iop[port].dir, pin);
	else
		clrbits32(&iop[port].dir, pin);

	if (!(flags & CPM_PIN_GPIO))
		setbits32(&iop[port].par, pin);
	else
		clrbits32(&iop[port].par, pin);

	if (flags & CPM_PIN_SECONDARY)
		setbits32(&iop[port].sor, pin);
	else
		clrbits32(&iop[port].sor, pin);

	if (flags & CPM_PIN_OPENDRAIN)
		setbits32(&iop[port].odr, pin);
	else
		clrbits32(&iop[port].odr, pin);
}
Commit	Line	Data
b0c110b4 VB	1	/*
	2	* General Purpose functions for the global management of the
	3	* 8260 Communication Processor Module.
	4	* Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
	5	* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
	6	* 2.3.99 Updates
	7	*
	8	* 2006 (c) MontaVista Software, Inc.
	9	* Vitaly Bordug <vbordug@ru.mvista.com>
	10	* Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
	11	*
	12	* This file is licensed under the terms of the GNU General Public License
	13	* version 2. This program is licensed "as is" without any warranty of any
	14	* kind, whether express or implied.
	15	*/
	16
	17	/*
	18	*
	19	* In addition to the individual control of the communication
	20	* channels, there are a few functions that globally affect the
	21	* communication processor.
	22	*
	23	* Buffer descriptors must be allocated from the dual ported memory
	24	* space. The allocator for that is here. When the communication
	25	* process is reset, we reclaim the memory available. There is
	26	* currently no deallocator for this memory.
	27	*/
	28	#include <linux/errno.h>
	29	#include <linux/sched.h>
	30	#include <linux/kernel.h>
	31	#include <linux/param.h>
	32	#include <linux/string.h>
	33	#include <linux/mm.h>
	34	#include <linux/interrupt.h>
	35	#include <linux/module.h>
449012da SW	36	#include <linux/of.h>
449012da SW	37
b0c110b4 VB	38	#include <asm/io.h>
	39	#include <asm/irq.h>
	40	#include <asm/mpc8260.h>
	41	#include <asm/page.h>
	42	#include <asm/pgtable.h>
	43	#include <asm/cpm2.h>
	44	#include <asm/rheap.h>
	45	#include <asm/fs_pd.h>
	46
	47	#include <sysdev/fsl_soc.h>
	48
15f8c604	49	#ifndef CONFIG_PPC_CPM_NEW_BINDING
b0c110b4	50	static void cpm2_dpinit(void);
15f8c604 SW	51	#endif
15f8c604 SW	52
449012da	53	cpm_cpm2_t __iomem cpmp; / Pointer to comm processor space */
b0c110b4 VB	54
	55	/* We allocate this here because it is used almost exclusively for
	56	* the communication processor devices.
	57	*/
449012da	58	cpm2_map_t __iomem *cpm2_immr;
b0c110b4 VB	59
	60	#define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
	61	of space for CPM as it is larger
	62	than on PQ2 */
	63
cd2150bc	64	void __init cpm2_reset(void)
b0c110b4	65	{
449012da SW	66	#ifdef CONFIG_PPC_85xx
	67	cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
	68	#else
	69	cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
	70	#endif
b0c110b4 VB	71
	72	/* Reclaim the DP memory for our use.
	73	*/
15f8c604 SW	74	#ifdef CONFIG_PPC_CPM_NEW_BINDING
	75	cpm_muram_init();
	76	#else
b0c110b4	77	cpm2_dpinit();
15f8c604	78	#endif
b0c110b4 VB	79
	80	/* Tell everyone where the comm processor resides.
	81	*/
	82	cpmp = &cpm2_immr->im_cpm;
	83	}
	84
362f9b6f JF	85	static DEFINE_SPINLOCK(cmd_lock);
	86
	87	#define MAX_CR_CMD_LOOPS 10000
	88
	89	int cpm_command(u32 command, u8 opcode)
	90	{
	91	int i, ret;
	92	unsigned long flags;
	93
	94	spin_lock_irqsave(&cmd_lock, flags);
	95
	96	ret = 0;
	97	out_be32(&cpmp->cp_cpcr, command \| opcode \| CPM_CR_FLG);
	98	for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
	99	if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
	100	goto out;
	101
e48b1b45	102	printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
362f9b6f JF	103	ret = -EIO;
	104	out:
	105	spin_unlock_irqrestore(&cmd_lock, flags);
	106	return ret;
	107	}
	108	EXPORT_SYMBOL(cpm_command);
	109
b0c110b4 VB	110	/* Set a baud rate generator. This needs lots of work. There are
	111	* eight BRGs, which can be connected to the CPM channels or output
	112	* as clocks. The BRGs are in two different block of internal
	113	* memory mapped space.
	114	* The baud rate clock is the system clock divided by something.
	115	* It was set up long ago during the initial boot phase and is
	116	* is given to us.
	117	* Baud rate clocks are zero-based in the driver code (as that maps
	118	* to port numbers). Documentation uses 1-based numbering.
	119	*/
	120	#define BRG_INT_CLK (get_brgfreq())
	121	#define BRG_UART_CLK (BRG_INT_CLK/16)
	122
	123	/* This function is used by UARTS, or anything else that uses a 16x
	124	* oversampled clock.
	125	*/
	126	void
	127	cpm_setbrg(uint brg, uint rate)
	128	{
449012da	129	u32 __iomem *bp;
b0c110b4 VB	130
	131	/* This is good enough to get SMCs running.....
	132	*/
	133	if (brg < 4) {
fc8e50e3	134	bp = cpm2_map_size(im_brgc1, 16);
b0c110b4	135	} else {
fc8e50e3	136	bp = cpm2_map_size(im_brgc5, 16);
b0c110b4 VB	137	brg -= 4;
	138	}
	139	bp += brg;
83fcdb4b	140	out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) \| CPM_BRG_EN);
fc8e50e3 VB	141
fc8e50e3 VB	142	cpm2_unmap(bp);
b0c110b4 VB	143	}
	144
	145	/* This function is used to set high speed synchronous baud rate
	146	* clocks.
	147	*/
	148	void
	149	cpm2_fastbrg(uint brg, uint rate, int div16)
	150	{
449012da SW	151	u32 __iomem *bp;
449012da SW	152	u32 val;
b0c110b4 VB	153
b0c110b4 VB	154	if (brg < 4) {
fc8e50e3	155	bp = cpm2_map_size(im_brgc1, 16);
b5677d84	156	} else {
fc8e50e3	157	bp = cpm2_map_size(im_brgc5, 16);
b0c110b4 VB	158	brg -= 4;
	159	}
	160	bp += brg;
449012da	161	val = ((BRG_INT_CLK / rate) << 1) \| CPM_BRG_EN;
b0c110b4	162	if (div16)
449012da	163	val \|= CPM_BRG_DIV16;
fc8e50e3	164
449012da	165	out_be32(bp, val);
fc8e50e3	166	cpm2_unmap(bp);
b0c110b4 VB	167	}
b0c110b4 VB	168
d3465c92 VB	169	int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
	170	{
	171	int ret = 0;
	172	int shift;
	173	int i, bits = 0;
449012da SW	174	cpmux_t __iomem *im_cpmux;
449012da SW	175	u32 __iomem *reg;
d3465c92	176	u32 mask = 7;
2652d4ec SW	177
2652d4ec SW	178	u8 clk_map[][3] = {
d3465c92 VB	179	{CPM_CLK_FCC1, CPM_BRG5, 0},
	180	{CPM_CLK_FCC1, CPM_BRG6, 1},
	181	{CPM_CLK_FCC1, CPM_BRG7, 2},
	182	{CPM_CLK_FCC1, CPM_BRG8, 3},
	183	{CPM_CLK_FCC1, CPM_CLK9, 4},
	184	{CPM_CLK_FCC1, CPM_CLK10, 5},
	185	{CPM_CLK_FCC1, CPM_CLK11, 6},
	186	{CPM_CLK_FCC1, CPM_CLK12, 7},
	187	{CPM_CLK_FCC2, CPM_BRG5, 0},
	188	{CPM_CLK_FCC2, CPM_BRG6, 1},
	189	{CPM_CLK_FCC2, CPM_BRG7, 2},
	190	{CPM_CLK_FCC2, CPM_BRG8, 3},
	191	{CPM_CLK_FCC2, CPM_CLK13, 4},
	192	{CPM_CLK_FCC2, CPM_CLK14, 5},
	193	{CPM_CLK_FCC2, CPM_CLK15, 6},
	194	{CPM_CLK_FCC2, CPM_CLK16, 7},
	195	{CPM_CLK_FCC3, CPM_BRG5, 0},
	196	{CPM_CLK_FCC3, CPM_BRG6, 1},
	197	{CPM_CLK_FCC3, CPM_BRG7, 2},
	198	{CPM_CLK_FCC3, CPM_BRG8, 3},
	199	{CPM_CLK_FCC3, CPM_CLK13, 4},
	200	{CPM_CLK_FCC3, CPM_CLK14, 5},
	201	{CPM_CLK_FCC3, CPM_CLK15, 6},
2652d4ec SW	202	{CPM_CLK_FCC3, CPM_CLK16, 7},
	203	{CPM_CLK_SCC1, CPM_BRG1, 0},
	204	{CPM_CLK_SCC1, CPM_BRG2, 1},
	205	{CPM_CLK_SCC1, CPM_BRG3, 2},
	206	{CPM_CLK_SCC1, CPM_BRG4, 3},
	207	{CPM_CLK_SCC1, CPM_CLK11, 4},
	208	{CPM_CLK_SCC1, CPM_CLK12, 5},
	209	{CPM_CLK_SCC1, CPM_CLK3, 6},
	210	{CPM_CLK_SCC1, CPM_CLK4, 7},
	211	{CPM_CLK_SCC2, CPM_BRG1, 0},
	212	{CPM_CLK_SCC2, CPM_BRG2, 1},
	213	{CPM_CLK_SCC2, CPM_BRG3, 2},
	214	{CPM_CLK_SCC2, CPM_BRG4, 3},
	215	{CPM_CLK_SCC2, CPM_CLK11, 4},
	216	{CPM_CLK_SCC2, CPM_CLK12, 5},
	217	{CPM_CLK_SCC2, CPM_CLK3, 6},
	218	{CPM_CLK_SCC2, CPM_CLK4, 7},
	219	{CPM_CLK_SCC3, CPM_BRG1, 0},
	220	{CPM_CLK_SCC3, CPM_BRG2, 1},
	221	{CPM_CLK_SCC3, CPM_BRG3, 2},
	222	{CPM_CLK_SCC3, CPM_BRG4, 3},
	223	{CPM_CLK_SCC3, CPM_CLK5, 4},
	224	{CPM_CLK_SCC3, CPM_CLK6, 5},
	225	{CPM_CLK_SCC3, CPM_CLK7, 6},
	226	{CPM_CLK_SCC3, CPM_CLK8, 7},
	227	{CPM_CLK_SCC4, CPM_BRG1, 0},
	228	{CPM_CLK_SCC4, CPM_BRG2, 1},
	229	{CPM_CLK_SCC4, CPM_BRG3, 2},
	230	{CPM_CLK_SCC4, CPM_BRG4, 3},
	231	{CPM_CLK_SCC4, CPM_CLK5, 4},
	232	{CPM_CLK_SCC4, CPM_CLK6, 5},
	233	{CPM_CLK_SCC4, CPM_CLK7, 6},
	234	{CPM_CLK_SCC4, CPM_CLK8, 7},
	235	};
d3465c92 VB	236
	237	im_cpmux = cpm2_map(im_cpmux);
	238
	239	switch (target) {
	240	case CPM_CLK_SCC1:
	241	reg = &im_cpmux->cmx_scr;
	242	shift = 24;
	243	case CPM_CLK_SCC2:
	244	reg = &im_cpmux->cmx_scr;
	245	shift = 16;
	246	break;
	247	case CPM_CLK_SCC3:
	248	reg = &im_cpmux->cmx_scr;
	249	shift = 8;
	250	break;
	251	case CPM_CLK_SCC4:
	252	reg = &im_cpmux->cmx_scr;
	253	shift = 0;
	254	break;
	255	case CPM_CLK_FCC1:
	256	reg = &im_cpmux->cmx_fcr;
	257	shift = 24;
	258	break;
	259	case CPM_CLK_FCC2:
	260	reg = &im_cpmux->cmx_fcr;
	261	shift = 16;
	262	break;
	263	case CPM_CLK_FCC3:
	264	reg = &im_cpmux->cmx_fcr;
	265	shift = 8;
	266	break;
	267	default:
	268	printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
	269	return -EINVAL;
	270	}
	271
	272	if (mode == CPM_CLK_RX)
4b218e9b	273	shift += 3;
d3465c92	274
2652d4ec	275	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
d3465c92 VB	276	if (clk_map[i][0] == target && clk_map[i][1] == clock) {
	277	bits = clk_map[i][2];
	278	break;
	279	}
	280	}
2652d4ec	281	if (i == ARRAY_SIZE(clk_map))
d3465c92 VB	282	ret = -EINVAL;
	283
	284	bits <<= shift;
	285	mask <<= shift;
2652d4ec	286
d3465c92 VB	287	out_be32(reg, (in_be32(reg) & ~mask) \| bits);
	288
	289	cpm2_unmap(im_cpmux);
	290	return ret;
	291	}
	292
2652d4ec SW	293	int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
	294	{
	295	int ret = 0;
	296	int shift;
	297	int i, bits = 0;
	298	cpmux_t __iomem *im_cpmux;
	299	u8 __iomem *reg;
	300	u8 mask = 3;
	301
	302	u8 clk_map[][3] = {
	303	{CPM_CLK_SMC1, CPM_BRG1, 0},
	304	{CPM_CLK_SMC1, CPM_BRG7, 1},
	305	{CPM_CLK_SMC1, CPM_CLK7, 2},
	306	{CPM_CLK_SMC1, CPM_CLK9, 3},
	307	{CPM_CLK_SMC2, CPM_BRG2, 0},
	308	{CPM_CLK_SMC2, CPM_BRG8, 1},
	309	{CPM_CLK_SMC2, CPM_CLK4, 2},
	310	{CPM_CLK_SMC2, CPM_CLK15, 3},
	311	};
	312
	313	im_cpmux = cpm2_map(im_cpmux);
	314
	315	switch (target) {
	316	case CPM_CLK_SMC1:
	317	reg = &im_cpmux->cmx_smr;
	318	mask = 3;
	319	shift = 4;
	320	break;
	321	case CPM_CLK_SMC2:
	322	reg = &im_cpmux->cmx_smr;
	323	mask = 3;
	324	shift = 0;
	325	break;
	326	default:
	327	printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
	328	return -EINVAL;
	329	}
	330
	331	for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
	332	if (clk_map[i][0] == target && clk_map[i][1] == clock) {
	333	bits = clk_map[i][2];
	334	break;
	335	}
	336	}
	337	if (i == ARRAY_SIZE(clk_map))
	338	ret = -EINVAL;
	339
	340	bits <<= shift;
	341	mask <<= shift;
	342
	343	out_8(reg, (in_8(reg) & ~mask) \| bits);
	344
	345	cpm2_unmap(im_cpmux);
	346	return ret;
	347	}
	348
15f8c604	349	#ifndef CONFIG_PPC_CPM_NEW_BINDING
b0c110b4 VB	350	/*
	351	* dpalloc / dpfree bits.
	352	*/
	353	static spinlock_t cpm_dpmem_lock;
	354	/* 16 blocks should be enough to satisfy all requests
	355	* until the memory subsystem goes up... */
	356	static rh_block_t cpm_boot_dpmem_rh_block[16];
	357	static rh_info_t cpm_dpmem_info;
449012da	358	static u8 __iomem *im_dprambase;
b0c110b4 VB	359
	360	static void cpm2_dpinit(void)
	361	{
449012da	362	spin_lock_init(&cpm_dpmem_lock);
fc8e50e3	363
b0c110b4 VB	364	/* initialize the info header */
	365	rh_init(&cpm_dpmem_info, 1,
	366	sizeof(cpm_boot_dpmem_rh_block) /
	367	sizeof(cpm_boot_dpmem_rh_block[0]),
	368	cpm_boot_dpmem_rh_block);
	369
15f8c604 SW	370	im_dprambase = cpm2_immr;
15f8c604 SW	371
b0c110b4 VB	372	/* Attach the usable dpmem area */
	373	/* XXX: This is actually crap. CPM_DATAONLY_BASE and
	374	* CPM_DATAONLY_SIZE is only a subset of the available dpram. It
	375	* varies with the processor and the microcode patches activated.
	376	* But the following should be at least safe.
	377	*/
15f8c604	378	rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
b0c110b4 VB	379	}
	380
	381	/* This function returns an index into the DPRAM area.
	382	*/
4c35630c	383	unsigned long cpm_dpalloc(uint size, uint align)
b0c110b4	384	{
4c35630c	385	unsigned long start;
b0c110b4 VB	386	unsigned long flags;
	387
	388	spin_lock_irqsave(&cpm_dpmem_lock, flags);
	389	cpm_dpmem_info.alignment = align;
	390	start = rh_alloc(&cpm_dpmem_info, size, "commproc");
	391	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
	392
	393	return (uint)start;
	394	}
	395	EXPORT_SYMBOL(cpm_dpalloc);
	396
4c35630c	397	int cpm_dpfree(unsigned long offset)
b0c110b4 VB	398	{
	399	int ret;
	400	unsigned long flags;
	401
	402	spin_lock_irqsave(&cpm_dpmem_lock, flags);
4c35630c	403	ret = rh_free(&cpm_dpmem_info, offset);
b0c110b4 VB	404	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
	405
	406	return ret;
	407	}
	408	EXPORT_SYMBOL(cpm_dpfree);
	409
	410	/* not sure if this is ever needed */
4c35630c	411	unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
b0c110b4	412	{
4c35630c	413	unsigned long start;
b0c110b4 VB	414	unsigned long flags;
	415
	416	spin_lock_irqsave(&cpm_dpmem_lock, flags);
	417	cpm_dpmem_info.alignment = align;
4c35630c	418	start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
b0c110b4 VB	419	spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
b0c110b4 VB	420
4c35630c	421	return start;
b0c110b4 VB	422	}
	423	EXPORT_SYMBOL(cpm_dpalloc_fixed);
	424
	425	void cpm_dpdump(void)
	426	{
	427	rh_dump(&cpm_dpmem_info);
	428	}
	429	EXPORT_SYMBOL(cpm_dpdump);
	430
4c35630c	431	void *cpm_dpram_addr(unsigned long offset)
b0c110b4	432	{
fc8e50e3	433	return (void *)(im_dprambase + offset);
b0c110b4 VB	434	}
b0c110b4 VB	435	EXPORT_SYMBOL(cpm_dpram_addr);
15f8c604	436	#endif /* !CONFIG_PPC_CPM_NEW_BINDING */
7f21f529 SW	437
	438	struct cpm2_ioports {
	439	u32 dir, par, sor, odr, dat;
	440	u32 res[3];
	441	};
	442
	443	void cpm2_set_pin(int port, int pin, int flags)
	444	{
	445	struct cpm2_ioports __iomem *iop =
	446	(struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
	447
	448	pin = 1 << (31 - pin);
	449
	450	if (flags & CPM_PIN_OUTPUT)
	451	setbits32(&iop[port].dir, pin);
	452	else
	453	clrbits32(&iop[port].dir, pin);
	454
	455	if (!(flags & CPM_PIN_GPIO))
	456	setbits32(&iop[port].par, pin);
	457	else
	458	clrbits32(&iop[port].par, pin);
	459
	460	if (flags & CPM_PIN_SECONDARY)
	461	setbits32(&iop[port].sor, pin);
	462	else
	463	clrbits32(&iop[port].sor, pin);
	464
	465	if (flags & CPM_PIN_OPENDRAIN)
	466	setbits32(&iop[port].odr, pin);
	467	else
	468	clrbits32(&iop[port].odr, pin);
	469	}