Commit | Line | Data |
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f2a0bd37 VB |
1 | /* |
2 | * General Purpose functions for the global management of the | |
3 | * Communication Processor Module. | |
4 | * Copyright (c) 1997 Dan error_act (dmalek@jlc.net) | |
5 | * | |
6 | * In addition to the individual control of the communication | |
7 | * channels, there are a few functions that globally affect the | |
8 | * communication processor. | |
9 | * | |
10 | * Buffer descriptors must be allocated from the dual ported memory | |
11 | * space. The allocator for that is here. When the communication | |
12 | * process is reset, we reclaim the memory available. There is | |
13 | * currently no deallocator for this memory. | |
14 | * The amount of space available is platform dependent. On the | |
15 | * MBX, the EPPC software loads additional microcode into the | |
16 | * communication processor, and uses some of the DP ram for this | |
17 | * purpose. Current, the first 512 bytes and the last 256 bytes of | |
18 | * memory are used. Right now I am conservative and only use the | |
19 | * memory that can never be used for microcode. If there are | |
20 | * applications that require more DP ram, we can expand the boundaries | |
21 | * but then we have to be careful of any downloaded microcode. | |
22 | */ | |
23 | #include <linux/errno.h> | |
24 | #include <linux/sched.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/param.h> | |
28 | #include <linux/string.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/irq.h> | |
32 | #include <linux/module.h> | |
dc2380ec | 33 | #include <linux/spinlock.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
f2a0bd37 VB |
35 | #include <asm/page.h> |
36 | #include <asm/pgtable.h> | |
37 | #include <asm/8xx_immap.h> | |
b5677d84 | 38 | #include <asm/cpm1.h> |
f2a0bd37 VB |
39 | #include <asm/io.h> |
40 | #include <asm/tlbflush.h> | |
41 | #include <asm/rheap.h> | |
42 | #include <asm/prom.h> | |
15f8c604 | 43 | #include <asm/cpm.h> |
f2a0bd37 VB |
44 | |
45 | #include <asm/fs_pd.h> | |
46 | ||
dc2380ec JF |
47 | #ifdef CONFIG_8xx_GPIO |
48 | #include <linux/of_gpio.h> | |
49 | #endif | |
50 | ||
f2a0bd37 VB |
51 | #define CPM_MAP_SIZE (0x4000) |
52 | ||
fb533d0c SW |
53 | cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */ |
54 | immap_t __iomem *mpc8xx_immr; | |
55 | static cpic8xx_t __iomem *cpic_reg; | |
f2a0bd37 | 56 | |
bae1d8f1 | 57 | static struct irq_domain *cpm_pic_host; |
f2a0bd37 | 58 | |
a2073d54 | 59 | static void cpm_mask_irq(struct irq_data *d) |
f2a0bd37 | 60 | { |
476eb491 | 61 | unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); |
f2a0bd37 VB |
62 | |
63 | clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); | |
64 | } | |
65 | ||
a2073d54 | 66 | static void cpm_unmask_irq(struct irq_data *d) |
f2a0bd37 | 67 | { |
476eb491 | 68 | unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); |
f2a0bd37 VB |
69 | |
70 | setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); | |
71 | } | |
72 | ||
a2073d54 | 73 | static void cpm_end_irq(struct irq_data *d) |
f2a0bd37 | 74 | { |
476eb491 | 75 | unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); |
f2a0bd37 VB |
76 | |
77 | out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec)); | |
78 | } | |
79 | ||
80 | static struct irq_chip cpm_pic = { | |
fc380c0c | 81 | .name = "CPM PIC", |
a2073d54 LB |
82 | .irq_mask = cpm_mask_irq, |
83 | .irq_unmask = cpm_unmask_irq, | |
84 | .irq_eoi = cpm_end_irq, | |
f2a0bd37 VB |
85 | }; |
86 | ||
87 | int cpm_get_irq(void) | |
88 | { | |
89 | int cpm_vec; | |
90 | ||
91 | /* Get the vector by setting the ACK bit and then reading | |
92 | * the register. | |
93 | */ | |
94 | out_be16(&cpic_reg->cpic_civr, 1); | |
95 | cpm_vec = in_be16(&cpic_reg->cpic_civr); | |
96 | cpm_vec >>= 11; | |
97 | ||
98 | return irq_linear_revmap(cpm_pic_host, cpm_vec); | |
99 | } | |
100 | ||
bae1d8f1 | 101 | static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq, |
f2a0bd37 VB |
102 | irq_hw_number_t hw) |
103 | { | |
104 | pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); | |
105 | ||
98488db9 | 106 | irq_set_status_flags(virq, IRQ_LEVEL); |
ec775d0e | 107 | irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); |
f2a0bd37 VB |
108 | return 0; |
109 | } | |
110 | ||
111 | /* The CPM can generate the error interrupt when there is a race condition | |
112 | * between generating and masking interrupts. All we have to do is ACK it | |
113 | * and return. This is a no-op function so we don't need any special | |
114 | * tests in the interrupt handler. | |
115 | */ | |
4b218e9b | 116 | static irqreturn_t cpm_error_interrupt(int irq, void *dev) |
f2a0bd37 VB |
117 | { |
118 | return IRQ_HANDLED; | |
119 | } | |
120 | ||
121 | static struct irqaction cpm_error_irqaction = { | |
122 | .handler = cpm_error_interrupt, | |
e8003404 | 123 | .flags = IRQF_NO_THREAD, |
f2a0bd37 VB |
124 | .name = "error", |
125 | }; | |
126 | ||
9f70b8eb | 127 | static const struct irq_domain_ops cpm_pic_host_ops = { |
f2a0bd37 VB |
128 | .map = cpm_pic_host_map, |
129 | }; | |
130 | ||
131 | unsigned int cpm_pic_init(void) | |
132 | { | |
133 | struct device_node *np = NULL; | |
134 | struct resource res; | |
ef24ba70 | 135 | unsigned int sirq = 0, hwirq, eirq; |
f2a0bd37 VB |
136 | int ret; |
137 | ||
138 | pr_debug("cpm_pic_init\n"); | |
139 | ||
fb533d0c SW |
140 | np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic"); |
141 | if (np == NULL) | |
142 | np = of_find_compatible_node(NULL, "cpm-pic", "CPM"); | |
f2a0bd37 VB |
143 | if (np == NULL) { |
144 | printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n"); | |
145 | return sirq; | |
146 | } | |
fb533d0c | 147 | |
f2a0bd37 VB |
148 | ret = of_address_to_resource(np, 0, &res); |
149 | if (ret) | |
150 | goto end; | |
151 | ||
28f65c11 | 152 | cpic_reg = ioremap(res.start, resource_size(&res)); |
f2a0bd37 VB |
153 | if (cpic_reg == NULL) |
154 | goto end; | |
155 | ||
156 | sirq = irq_of_parse_and_map(np, 0); | |
ef24ba70 | 157 | if (!sirq) |
f2a0bd37 VB |
158 | goto end; |
159 | ||
160 | /* Initialize the CPM interrupt controller. */ | |
476eb491 | 161 | hwirq = (unsigned int)virq_to_hw(sirq); |
f2a0bd37 VB |
162 | out_be32(&cpic_reg->cpic_cicr, |
163 | (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | | |
164 | ((hwirq/2) << 13) | CICR_HP_MASK); | |
165 | ||
166 | out_be32(&cpic_reg->cpic_cimr, 0); | |
167 | ||
a8db8cf0 | 168 | cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL); |
f2a0bd37 VB |
169 | if (cpm_pic_host == NULL) { |
170 | printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n"); | |
ef24ba70 | 171 | sirq = 0; |
f2a0bd37 VB |
172 | goto end; |
173 | } | |
f2a0bd37 VB |
174 | |
175 | /* Install our own error handler. */ | |
fb533d0c SW |
176 | np = of_find_compatible_node(NULL, NULL, "fsl,cpm1"); |
177 | if (np == NULL) | |
178 | np = of_find_node_by_type(NULL, "cpm"); | |
f2a0bd37 VB |
179 | if (np == NULL) { |
180 | printk(KERN_ERR "CPM PIC init: can not find cpm node\n"); | |
181 | goto end; | |
182 | } | |
fb533d0c | 183 | |
4b218e9b | 184 | eirq = irq_of_parse_and_map(np, 0); |
ef24ba70 | 185 | if (!eirq) |
f2a0bd37 VB |
186 | goto end; |
187 | ||
188 | if (setup_irq(eirq, &cpm_error_irqaction)) | |
189 | printk(KERN_ERR "Could not allocate CPM error IRQ!"); | |
190 | ||
191 | setbits32(&cpic_reg->cpic_cicr, CICR_IEN); | |
192 | ||
193 | end: | |
194 | of_node_put(np); | |
195 | return sirq; | |
196 | } | |
197 | ||
15f8c604 | 198 | void __init cpm_reset(void) |
f2a0bd37 | 199 | { |
fb533d0c | 200 | sysconf8xx_t __iomem *siu_conf; |
f2a0bd37 | 201 | |
fb533d0c SW |
202 | mpc8xx_immr = ioremap(get_immrbase(), 0x4000); |
203 | if (!mpc8xx_immr) { | |
204 | printk(KERN_CRIT "Could not map IMMR\n"); | |
205 | return; | |
206 | } | |
f2a0bd37 | 207 | |
fb533d0c SW |
208 | cpmp = &mpc8xx_immr->im_cpm; |
209 | ||
210 | #ifndef CONFIG_PPC_EARLY_DEBUG_CPM | |
f2a0bd37 VB |
211 | /* Perform a reset. |
212 | */ | |
fb533d0c | 213 | out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); |
f2a0bd37 VB |
214 | |
215 | /* Wait for it. | |
216 | */ | |
fb533d0c SW |
217 | while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG); |
218 | #endif | |
f2a0bd37 | 219 | |
fb533d0c SW |
220 | #ifdef CONFIG_UCODE_PATCH |
221 | cpm_load_patch(cpmp); | |
f2a0bd37 VB |
222 | #endif |
223 | ||
224 | /* Set SDMA Bus Request priority 5. | |
225 | * On 860T, this also enables FEC priority 6. I am not sure | |
25985edc | 226 | * this is what we really want for some applications, but the |
f2a0bd37 VB |
227 | * manual recommends it. |
228 | * Bit 25, FAM can also be set to use FEC aggressive mode (860T). | |
229 | */ | |
fb533d0c | 230 | siu_conf = immr_map(im_siu_conf); |
501ea766 CL |
231 | if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */ |
232 | out_be32(&siu_conf->sc_sdcr, 0x40); | |
233 | else | |
234 | out_be32(&siu_conf->sc_sdcr, 1); | |
f2a0bd37 | 235 | immr_unmap(siu_conf); |
f2a0bd37 VB |
236 | } |
237 | ||
362f9b6f JF |
238 | static DEFINE_SPINLOCK(cmd_lock); |
239 | ||
240 | #define MAX_CR_CMD_LOOPS 10000 | |
241 | ||
242 | int cpm_command(u32 command, u8 opcode) | |
243 | { | |
244 | int i, ret; | |
245 | unsigned long flags; | |
246 | ||
247 | if (command & 0xffffff0f) | |
248 | return -EINVAL; | |
249 | ||
250 | spin_lock_irqsave(&cmd_lock, flags); | |
251 | ||
252 | ret = 0; | |
253 | out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8)); | |
254 | for (i = 0; i < MAX_CR_CMD_LOOPS; i++) | |
255 | if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0) | |
256 | goto out; | |
257 | ||
e48b1b45 | 258 | printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__); |
362f9b6f JF |
259 | ret = -EIO; |
260 | out: | |
261 | spin_unlock_irqrestore(&cmd_lock, flags); | |
262 | return ret; | |
263 | } | |
264 | EXPORT_SYMBOL(cpm_command); | |
265 | ||
f2a0bd37 VB |
266 | /* Set a baud rate generator. This needs lots of work. There are |
267 | * four BRGs, any of which can be wired to any channel. | |
268 | * The internal baud rate clock is the system clock divided by 16. | |
269 | * This assumes the baudrate is 16x oversampled by the uart. | |
270 | */ | |
271 | #define BRG_INT_CLK (get_brgfreq()) | |
272 | #define BRG_UART_CLK (BRG_INT_CLK/16) | |
273 | #define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16) | |
274 | ||
275 | void | |
276 | cpm_setbrg(uint brg, uint rate) | |
277 | { | |
fb533d0c | 278 | u32 __iomem *bp; |
f2a0bd37 VB |
279 | |
280 | /* This is good enough to get SMCs running..... | |
281 | */ | |
fb533d0c | 282 | bp = &cpmp->cp_brgc1; |
f2a0bd37 VB |
283 | bp += brg; |
284 | /* The BRG has a 12-bit counter. For really slow baud rates (or | |
285 | * really fast processors), we may have to further divide by 16. | |
286 | */ | |
287 | if (((BRG_UART_CLK / rate) - 1) < 4096) | |
fb533d0c | 288 | out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN); |
f2a0bd37 | 289 | else |
fb533d0c | 290 | out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) | |
b5677d84 | 291 | CPM_BRG_EN | CPM_BRG_DIV16); |
f2a0bd37 VB |
292 | } |
293 | ||
663edbd2 | 294 | struct cpm_ioport16 { |
721c0c8a | 295 | __be16 dir, par, odr_sor, dat, intr; |
663edbd2 SW |
296 | __be16 res[3]; |
297 | }; | |
298 | ||
dc2380ec JF |
299 | struct cpm_ioport32b { |
300 | __be32 dir, par, odr, dat; | |
301 | }; | |
302 | ||
303 | struct cpm_ioport32e { | |
304 | __be32 dir, par, sor, odr, dat; | |
663edbd2 SW |
305 | }; |
306 | ||
307 | static void cpm1_set_pin32(int port, int pin, int flags) | |
308 | { | |
dc2380ec | 309 | struct cpm_ioport32e __iomem *iop; |
663edbd2 SW |
310 | pin = 1 << (31 - pin); |
311 | ||
312 | if (port == CPM_PORTB) | |
dc2380ec | 313 | iop = (struct cpm_ioport32e __iomem *) |
663edbd2 SW |
314 | &mpc8xx_immr->im_cpm.cp_pbdir; |
315 | else | |
dc2380ec | 316 | iop = (struct cpm_ioport32e __iomem *) |
663edbd2 SW |
317 | &mpc8xx_immr->im_cpm.cp_pedir; |
318 | ||
319 | if (flags & CPM_PIN_OUTPUT) | |
320 | setbits32(&iop->dir, pin); | |
321 | else | |
322 | clrbits32(&iop->dir, pin); | |
323 | ||
324 | if (!(flags & CPM_PIN_GPIO)) | |
325 | setbits32(&iop->par, pin); | |
326 | else | |
327 | clrbits32(&iop->par, pin); | |
328 | ||
721c0c8a JF |
329 | if (port == CPM_PORTB) { |
330 | if (flags & CPM_PIN_OPENDRAIN) | |
331 | setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); | |
332 | else | |
333 | clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); | |
334 | } | |
335 | ||
663edbd2 SW |
336 | if (port == CPM_PORTE) { |
337 | if (flags & CPM_PIN_SECONDARY) | |
338 | setbits32(&iop->sor, pin); | |
339 | else | |
340 | clrbits32(&iop->sor, pin); | |
341 | ||
342 | if (flags & CPM_PIN_OPENDRAIN) | |
343 | setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); | |
344 | else | |
345 | clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); | |
346 | } | |
347 | } | |
348 | ||
349 | static void cpm1_set_pin16(int port, int pin, int flags) | |
350 | { | |
351 | struct cpm_ioport16 __iomem *iop = | |
352 | (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport; | |
353 | ||
354 | pin = 1 << (15 - pin); | |
355 | ||
356 | if (port != 0) | |
357 | iop += port - 1; | |
358 | ||
359 | if (flags & CPM_PIN_OUTPUT) | |
360 | setbits16(&iop->dir, pin); | |
361 | else | |
362 | clrbits16(&iop->dir, pin); | |
363 | ||
364 | if (!(flags & CPM_PIN_GPIO)) | |
365 | setbits16(&iop->par, pin); | |
366 | else | |
367 | clrbits16(&iop->par, pin); | |
368 | ||
721c0c8a JF |
369 | if (port == CPM_PORTA) { |
370 | if (flags & CPM_PIN_OPENDRAIN) | |
371 | setbits16(&iop->odr_sor, pin); | |
372 | else | |
373 | clrbits16(&iop->odr_sor, pin); | |
374 | } | |
663edbd2 SW |
375 | if (port == CPM_PORTC) { |
376 | if (flags & CPM_PIN_SECONDARY) | |
721c0c8a | 377 | setbits16(&iop->odr_sor, pin); |
663edbd2 | 378 | else |
721c0c8a | 379 | clrbits16(&iop->odr_sor, pin); |
663edbd2 SW |
380 | } |
381 | } | |
382 | ||
383 | void cpm1_set_pin(enum cpm_port port, int pin, int flags) | |
384 | { | |
385 | if (port == CPM_PORTB || port == CPM_PORTE) | |
386 | cpm1_set_pin32(port, pin, flags); | |
387 | else | |
388 | cpm1_set_pin16(port, pin, flags); | |
389 | } | |
390 | ||
391 | int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode) | |
392 | { | |
393 | int shift; | |
394 | int i, bits = 0; | |
395 | u32 __iomem *reg; | |
396 | u32 mask = 7; | |
397 | ||
398 | u8 clk_map[][3] = { | |
399 | {CPM_CLK_SCC1, CPM_BRG1, 0}, | |
400 | {CPM_CLK_SCC1, CPM_BRG2, 1}, | |
401 | {CPM_CLK_SCC1, CPM_BRG3, 2}, | |
402 | {CPM_CLK_SCC1, CPM_BRG4, 3}, | |
403 | {CPM_CLK_SCC1, CPM_CLK1, 4}, | |
404 | {CPM_CLK_SCC1, CPM_CLK2, 5}, | |
405 | {CPM_CLK_SCC1, CPM_CLK3, 6}, | |
406 | {CPM_CLK_SCC1, CPM_CLK4, 7}, | |
407 | ||
408 | {CPM_CLK_SCC2, CPM_BRG1, 0}, | |
409 | {CPM_CLK_SCC2, CPM_BRG2, 1}, | |
410 | {CPM_CLK_SCC2, CPM_BRG3, 2}, | |
411 | {CPM_CLK_SCC2, CPM_BRG4, 3}, | |
412 | {CPM_CLK_SCC2, CPM_CLK1, 4}, | |
413 | {CPM_CLK_SCC2, CPM_CLK2, 5}, | |
414 | {CPM_CLK_SCC2, CPM_CLK3, 6}, | |
415 | {CPM_CLK_SCC2, CPM_CLK4, 7}, | |
416 | ||
417 | {CPM_CLK_SCC3, CPM_BRG1, 0}, | |
418 | {CPM_CLK_SCC3, CPM_BRG2, 1}, | |
419 | {CPM_CLK_SCC3, CPM_BRG3, 2}, | |
420 | {CPM_CLK_SCC3, CPM_BRG4, 3}, | |
421 | {CPM_CLK_SCC3, CPM_CLK5, 4}, | |
422 | {CPM_CLK_SCC3, CPM_CLK6, 5}, | |
423 | {CPM_CLK_SCC3, CPM_CLK7, 6}, | |
424 | {CPM_CLK_SCC3, CPM_CLK8, 7}, | |
425 | ||
426 | {CPM_CLK_SCC4, CPM_BRG1, 0}, | |
427 | {CPM_CLK_SCC4, CPM_BRG2, 1}, | |
428 | {CPM_CLK_SCC4, CPM_BRG3, 2}, | |
429 | {CPM_CLK_SCC4, CPM_BRG4, 3}, | |
430 | {CPM_CLK_SCC4, CPM_CLK5, 4}, | |
431 | {CPM_CLK_SCC4, CPM_CLK6, 5}, | |
432 | {CPM_CLK_SCC4, CPM_CLK7, 6}, | |
433 | {CPM_CLK_SCC4, CPM_CLK8, 7}, | |
434 | ||
435 | {CPM_CLK_SMC1, CPM_BRG1, 0}, | |
436 | {CPM_CLK_SMC1, CPM_BRG2, 1}, | |
437 | {CPM_CLK_SMC1, CPM_BRG3, 2}, | |
438 | {CPM_CLK_SMC1, CPM_BRG4, 3}, | |
439 | {CPM_CLK_SMC1, CPM_CLK1, 4}, | |
440 | {CPM_CLK_SMC1, CPM_CLK2, 5}, | |
441 | {CPM_CLK_SMC1, CPM_CLK3, 6}, | |
442 | {CPM_CLK_SMC1, CPM_CLK4, 7}, | |
443 | ||
444 | {CPM_CLK_SMC2, CPM_BRG1, 0}, | |
445 | {CPM_CLK_SMC2, CPM_BRG2, 1}, | |
446 | {CPM_CLK_SMC2, CPM_BRG3, 2}, | |
447 | {CPM_CLK_SMC2, CPM_BRG4, 3}, | |
448 | {CPM_CLK_SMC2, CPM_CLK5, 4}, | |
449 | {CPM_CLK_SMC2, CPM_CLK6, 5}, | |
450 | {CPM_CLK_SMC2, CPM_CLK7, 6}, | |
451 | {CPM_CLK_SMC2, CPM_CLK8, 7}, | |
452 | }; | |
453 | ||
454 | switch (target) { | |
455 | case CPM_CLK_SCC1: | |
456 | reg = &mpc8xx_immr->im_cpm.cp_sicr; | |
457 | shift = 0; | |
458 | break; | |
459 | ||
460 | case CPM_CLK_SCC2: | |
461 | reg = &mpc8xx_immr->im_cpm.cp_sicr; | |
462 | shift = 8; | |
463 | break; | |
464 | ||
465 | case CPM_CLK_SCC3: | |
466 | reg = &mpc8xx_immr->im_cpm.cp_sicr; | |
467 | shift = 16; | |
468 | break; | |
469 | ||
470 | case CPM_CLK_SCC4: | |
471 | reg = &mpc8xx_immr->im_cpm.cp_sicr; | |
472 | shift = 24; | |
473 | break; | |
474 | ||
475 | case CPM_CLK_SMC1: | |
476 | reg = &mpc8xx_immr->im_cpm.cp_simode; | |
477 | shift = 12; | |
478 | break; | |
479 | ||
480 | case CPM_CLK_SMC2: | |
481 | reg = &mpc8xx_immr->im_cpm.cp_simode; | |
482 | shift = 28; | |
483 | break; | |
484 | ||
485 | default: | |
486 | printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n"); | |
487 | return -EINVAL; | |
488 | } | |
489 | ||
663edbd2 SW |
490 | for (i = 0; i < ARRAY_SIZE(clk_map); i++) { |
491 | if (clk_map[i][0] == target && clk_map[i][1] == clock) { | |
492 | bits = clk_map[i][2]; | |
493 | break; | |
494 | } | |
495 | } | |
496 | ||
497 | if (i == ARRAY_SIZE(clk_map)) { | |
498 | printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n"); | |
499 | return -EINVAL; | |
500 | } | |
501 | ||
502 | bits <<= shift; | |
503 | mask <<= shift; | |
1cca2d2b WO |
504 | |
505 | if (reg == &mpc8xx_immr->im_cpm.cp_sicr) { | |
506 | if (mode == CPM_CLK_RTX) { | |
507 | bits |= bits << 3; | |
508 | mask |= mask << 3; | |
509 | } else if (mode == CPM_CLK_RX) { | |
510 | bits <<= 3; | |
511 | mask <<= 3; | |
512 | } | |
513 | } | |
514 | ||
663edbd2 SW |
515 | out_be32(reg, (in_be32(reg) & ~mask) | bits); |
516 | ||
517 | return 0; | |
518 | } | |
dc2380ec JF |
519 | |
520 | /* | |
521 | * GPIO LIB API implementation | |
522 | */ | |
523 | #ifdef CONFIG_8xx_GPIO | |
524 | ||
525 | struct cpm1_gpio16_chip { | |
526 | struct of_mm_gpio_chip mm_gc; | |
527 | spinlock_t lock; | |
528 | ||
529 | /* shadowed data register to clear/set bits safely */ | |
530 | u16 cpdata; | |
531 | }; | |
532 | ||
dc2380ec JF |
533 | static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc) |
534 | { | |
41017a75 CL |
535 | struct cpm1_gpio16_chip *cpm1_gc = |
536 | container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc); | |
dc2380ec JF |
537 | struct cpm_ioport16 __iomem *iop = mm_gc->regs; |
538 | ||
539 | cpm1_gc->cpdata = in_be16(&iop->dat); | |
540 | } | |
541 | ||
542 | static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio) | |
543 | { | |
544 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
545 | struct cpm_ioport16 __iomem *iop = mm_gc->regs; | |
546 | u16 pin_mask; | |
547 | ||
548 | pin_mask = 1 << (15 - gpio); | |
549 | ||
550 | return !!(in_be16(&iop->dat) & pin_mask); | |
551 | } | |
552 | ||
f1eaf16a JF |
553 | static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask, |
554 | int value) | |
dc2380ec | 555 | { |
e65078f1 | 556 | struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); |
dc2380ec | 557 | struct cpm_ioport16 __iomem *iop = mm_gc->regs; |
dc2380ec JF |
558 | |
559 | if (value) | |
560 | cpm1_gc->cpdata |= pin_mask; | |
561 | else | |
562 | cpm1_gc->cpdata &= ~pin_mask; | |
563 | ||
564 | out_be16(&iop->dat, cpm1_gc->cpdata); | |
f1eaf16a JF |
565 | } |
566 | ||
567 | static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value) | |
568 | { | |
569 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
e65078f1 | 570 | struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); |
f1eaf16a JF |
571 | unsigned long flags; |
572 | u16 pin_mask = 1 << (15 - gpio); | |
573 | ||
574 | spin_lock_irqsave(&cpm1_gc->lock, flags); | |
575 | ||
576 | __cpm1_gpio16_set(mm_gc, pin_mask, value); | |
dc2380ec JF |
577 | |
578 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); | |
579 | } | |
580 | ||
581 | static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
582 | { | |
583 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
e65078f1 | 584 | struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); |
dc2380ec | 585 | struct cpm_ioport16 __iomem *iop = mm_gc->regs; |
f1eaf16a JF |
586 | unsigned long flags; |
587 | u16 pin_mask = 1 << (15 - gpio); | |
dc2380ec | 588 | |
f1eaf16a | 589 | spin_lock_irqsave(&cpm1_gc->lock, flags); |
dc2380ec JF |
590 | |
591 | setbits16(&iop->dir, pin_mask); | |
f1eaf16a | 592 | __cpm1_gpio16_set(mm_gc, pin_mask, val); |
dc2380ec | 593 | |
f1eaf16a | 594 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); |
dc2380ec JF |
595 | |
596 | return 0; | |
597 | } | |
598 | ||
599 | static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio) | |
600 | { | |
601 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
e65078f1 | 602 | struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); |
dc2380ec | 603 | struct cpm_ioport16 __iomem *iop = mm_gc->regs; |
f1eaf16a JF |
604 | unsigned long flags; |
605 | u16 pin_mask = 1 << (15 - gpio); | |
dc2380ec | 606 | |
f1eaf16a | 607 | spin_lock_irqsave(&cpm1_gc->lock, flags); |
dc2380ec JF |
608 | |
609 | clrbits16(&iop->dir, pin_mask); | |
610 | ||
f1eaf16a JF |
611 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); |
612 | ||
dc2380ec JF |
613 | return 0; |
614 | } | |
615 | ||
616 | int cpm1_gpiochip_add16(struct device_node *np) | |
617 | { | |
618 | struct cpm1_gpio16_chip *cpm1_gc; | |
619 | struct of_mm_gpio_chip *mm_gc; | |
dc2380ec JF |
620 | struct gpio_chip *gc; |
621 | ||
622 | cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); | |
623 | if (!cpm1_gc) | |
624 | return -ENOMEM; | |
625 | ||
626 | spin_lock_init(&cpm1_gc->lock); | |
627 | ||
628 | mm_gc = &cpm1_gc->mm_gc; | |
a19e3da5 | 629 | gc = &mm_gc->gc; |
dc2380ec JF |
630 | |
631 | mm_gc->save_regs = cpm1_gpio16_save_regs; | |
dc2380ec JF |
632 | gc->ngpio = 16; |
633 | gc->direction_input = cpm1_gpio16_dir_in; | |
634 | gc->direction_output = cpm1_gpio16_dir_out; | |
635 | gc->get = cpm1_gpio16_get; | |
636 | gc->set = cpm1_gpio16_set; | |
637 | ||
e65078f1 | 638 | return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc); |
dc2380ec JF |
639 | } |
640 | ||
641 | struct cpm1_gpio32_chip { | |
642 | struct of_mm_gpio_chip mm_gc; | |
643 | spinlock_t lock; | |
644 | ||
645 | /* shadowed data register to clear/set bits safely */ | |
646 | u32 cpdata; | |
647 | }; | |
648 | ||
dc2380ec JF |
649 | static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) |
650 | { | |
41017a75 CL |
651 | struct cpm1_gpio32_chip *cpm1_gc = |
652 | container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc); | |
dc2380ec JF |
653 | struct cpm_ioport32b __iomem *iop = mm_gc->regs; |
654 | ||
655 | cpm1_gc->cpdata = in_be32(&iop->dat); | |
656 | } | |
657 | ||
658 | static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio) | |
659 | { | |
660 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
661 | struct cpm_ioport32b __iomem *iop = mm_gc->regs; | |
662 | u32 pin_mask; | |
663 | ||
664 | pin_mask = 1 << (31 - gpio); | |
665 | ||
666 | return !!(in_be32(&iop->dat) & pin_mask); | |
667 | } | |
668 | ||
f1eaf16a JF |
669 | static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, |
670 | int value) | |
dc2380ec | 671 | { |
e65078f1 | 672 | struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); |
dc2380ec | 673 | struct cpm_ioport32b __iomem *iop = mm_gc->regs; |
dc2380ec JF |
674 | |
675 | if (value) | |
676 | cpm1_gc->cpdata |= pin_mask; | |
677 | else | |
678 | cpm1_gc->cpdata &= ~pin_mask; | |
679 | ||
680 | out_be32(&iop->dat, cpm1_gc->cpdata); | |
f1eaf16a JF |
681 | } |
682 | ||
683 | static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) | |
684 | { | |
685 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
e65078f1 | 686 | struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); |
f1eaf16a JF |
687 | unsigned long flags; |
688 | u32 pin_mask = 1 << (31 - gpio); | |
689 | ||
690 | spin_lock_irqsave(&cpm1_gc->lock, flags); | |
691 | ||
692 | __cpm1_gpio32_set(mm_gc, pin_mask, value); | |
dc2380ec JF |
693 | |
694 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); | |
695 | } | |
696 | ||
697 | static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) | |
698 | { | |
699 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
e65078f1 | 700 | struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); |
dc2380ec | 701 | struct cpm_ioport32b __iomem *iop = mm_gc->regs; |
f1eaf16a JF |
702 | unsigned long flags; |
703 | u32 pin_mask = 1 << (31 - gpio); | |
dc2380ec | 704 | |
f1eaf16a | 705 | spin_lock_irqsave(&cpm1_gc->lock, flags); |
dc2380ec JF |
706 | |
707 | setbits32(&iop->dir, pin_mask); | |
f1eaf16a | 708 | __cpm1_gpio32_set(mm_gc, pin_mask, val); |
dc2380ec | 709 | |
f1eaf16a | 710 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); |
dc2380ec JF |
711 | |
712 | return 0; | |
713 | } | |
714 | ||
715 | static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) | |
716 | { | |
717 | struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); | |
e65078f1 | 718 | struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); |
dc2380ec | 719 | struct cpm_ioport32b __iomem *iop = mm_gc->regs; |
f1eaf16a JF |
720 | unsigned long flags; |
721 | u32 pin_mask = 1 << (31 - gpio); | |
dc2380ec | 722 | |
f1eaf16a | 723 | spin_lock_irqsave(&cpm1_gc->lock, flags); |
dc2380ec JF |
724 | |
725 | clrbits32(&iop->dir, pin_mask); | |
726 | ||
f1eaf16a JF |
727 | spin_unlock_irqrestore(&cpm1_gc->lock, flags); |
728 | ||
dc2380ec JF |
729 | return 0; |
730 | } | |
731 | ||
732 | int cpm1_gpiochip_add32(struct device_node *np) | |
733 | { | |
734 | struct cpm1_gpio32_chip *cpm1_gc; | |
735 | struct of_mm_gpio_chip *mm_gc; | |
dc2380ec JF |
736 | struct gpio_chip *gc; |
737 | ||
738 | cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); | |
739 | if (!cpm1_gc) | |
740 | return -ENOMEM; | |
741 | ||
742 | spin_lock_init(&cpm1_gc->lock); | |
743 | ||
744 | mm_gc = &cpm1_gc->mm_gc; | |
a19e3da5 | 745 | gc = &mm_gc->gc; |
dc2380ec JF |
746 | |
747 | mm_gc->save_regs = cpm1_gpio32_save_regs; | |
dc2380ec JF |
748 | gc->ngpio = 32; |
749 | gc->direction_input = cpm1_gpio32_dir_in; | |
750 | gc->direction_output = cpm1_gpio32_dir_out; | |
751 | gc->get = cpm1_gpio32_get; | |
752 | gc->set = cpm1_gpio32_set; | |
753 | ||
e65078f1 | 754 | return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc); |
dc2380ec JF |
755 | } |
756 | ||
757 | static int cpm_init_par_io(void) | |
758 | { | |
759 | struct device_node *np; | |
760 | ||
761 | for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-a") | |
762 | cpm1_gpiochip_add16(np); | |
763 | ||
764 | for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-b") | |
765 | cpm1_gpiochip_add32(np); | |
766 | ||
767 | for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-c") | |
768 | cpm1_gpiochip_add16(np); | |
769 | ||
770 | for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-d") | |
771 | cpm1_gpiochip_add16(np); | |
772 | ||
773 | /* Port E uses CPM2 layout */ | |
774 | for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank-e") | |
775 | cpm2_gpiochip_add32(np); | |
776 | return 0; | |
777 | } | |
778 | arch_initcall(cpm_init_par_io); | |
779 | ||
780 | #endif /* CONFIG_8xx_GPIO */ |