Commit | Line | Data |
---|---|---|
007e8f51 DG |
1 | /* |
2 | * arch/powerpc/platforms/pseries/xics.c | |
1da177e4 LT |
3 | * |
4 | * Copyright 2000 IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
0ebfff14 BH |
11 | |
12 | #undef DEBUG | |
13 | ||
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/threads.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/irq.h> | |
18 | #include <linux/smp.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/signal.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/gfp.h> | |
23 | #include <linux/radix-tree.h> | |
24 | #include <linux/cpu.h> | |
0ebfff14 | 25 | |
57cfb814 | 26 | #include <asm/firmware.h> |
1da177e4 LT |
27 | #include <asm/prom.h> |
28 | #include <asm/io.h> | |
29 | #include <asm/pgtable.h> | |
30 | #include <asm/smp.h> | |
31 | #include <asm/rtas.h> | |
1da177e4 LT |
32 | #include <asm/hvcall.h> |
33 | #include <asm/machdep.h> | |
2227718c | 34 | #include <asm/i8259.h> |
1da177e4 | 35 | |
007e8f51 | 36 | #include "xics.h" |
b9377ffc | 37 | #include "plpar_wrappers.h" |
007e8f51 | 38 | |
1da177e4 LT |
39 | #define XICS_IPI 2 |
40 | #define XICS_IRQ_SPURIOUS 0 | |
41 | ||
42 | /* Want a priority other than 0. Various HW issues require this. */ | |
43 | #define DEFAULT_PRIORITY 5 | |
44 | ||
007e8f51 | 45 | /* |
1da177e4 | 46 | * Mark IPIs as higher priority so we can take them inside interrupts that |
6714465e | 47 | * arent marked IRQF_DISABLED |
1da177e4 LT |
48 | */ |
49 | #define IPI_PRIORITY 4 | |
50 | ||
51 | struct xics_ipl { | |
52 | union { | |
53 | u32 word; | |
54 | u8 bytes[4]; | |
55 | } xirr_poll; | |
56 | union { | |
57 | u32 word; | |
58 | u8 bytes[4]; | |
59 | } xirr; | |
60 | u32 dummy; | |
61 | union { | |
62 | u32 word; | |
63 | u8 bytes[4]; | |
64 | } qirr; | |
65 | }; | |
66 | ||
67 | static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS]; | |
68 | ||
1da177e4 | 69 | static unsigned int default_server = 0xFF; |
26370322 AB |
70 | static unsigned int default_distrib_server = 0; |
71 | static unsigned int interrupt_server_size = 8; | |
1da177e4 | 72 | |
0ebfff14 BH |
73 | static struct irq_host *xics_host; |
74 | ||
1da177e4 LT |
75 | /* |
76 | * XICS only has a single IPI, so encode the messages per CPU | |
77 | */ | |
78 | struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned; | |
79 | ||
80 | /* RTAS service tokens */ | |
26370322 AB |
81 | static int ibm_get_xive; |
82 | static int ibm_set_xive; | |
83 | static int ibm_int_on; | |
84 | static int ibm_int_off; | |
1da177e4 | 85 | |
1da177e4 | 86 | |
b9e5b4e6 | 87 | /* Direct HW low level accessors */ |
1da177e4 | 88 | |
1da177e4 | 89 | |
0ebfff14 | 90 | static inline unsigned int direct_xirr_info_get(int n_cpu) |
1da177e4 LT |
91 | { |
92 | return in_be32(&xics_per_cpu[n_cpu]->xirr.word); | |
93 | } | |
94 | ||
b9e5b4e6 | 95 | static inline void direct_xirr_info_set(int n_cpu, int value) |
1da177e4 LT |
96 | { |
97 | out_be32(&xics_per_cpu[n_cpu]->xirr.word, value); | |
98 | } | |
99 | ||
b9e5b4e6 | 100 | static inline void direct_cppr_info(int n_cpu, u8 value) |
1da177e4 LT |
101 | { |
102 | out_8(&xics_per_cpu[n_cpu]->xirr.bytes[0], value); | |
103 | } | |
104 | ||
b9e5b4e6 | 105 | static inline void direct_qirr_info(int n_cpu, u8 value) |
1da177e4 LT |
106 | { |
107 | out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value); | |
108 | } | |
109 | ||
1da177e4 | 110 | |
b9e5b4e6 | 111 | /* LPAR low level accessors */ |
1da177e4 | 112 | |
1da177e4 | 113 | |
0ebfff14 | 114 | static inline unsigned int lpar_xirr_info_get(int n_cpu) |
1da177e4 LT |
115 | { |
116 | unsigned long lpar_rc; | |
007e8f51 | 117 | unsigned long return_value; |
1da177e4 LT |
118 | |
119 | lpar_rc = plpar_xirr(&return_value); | |
706c8c93 | 120 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 121 | panic(" bad return code xirr - rc = %lx \n", lpar_rc); |
0ebfff14 | 122 | return (unsigned int)return_value; |
1da177e4 LT |
123 | } |
124 | ||
b9e5b4e6 | 125 | static inline void lpar_xirr_info_set(int n_cpu, int value) |
1da177e4 LT |
126 | { |
127 | unsigned long lpar_rc; | |
128 | unsigned long val64 = value & 0xffffffff; | |
129 | ||
130 | lpar_rc = plpar_eoi(val64); | |
706c8c93 | 131 | if (lpar_rc != H_SUCCESS) |
1da177e4 | 132 | panic("bad return code EOI - rc = %ld, value=%lx\n", lpar_rc, |
007e8f51 | 133 | val64); |
1da177e4 LT |
134 | } |
135 | ||
b9e5b4e6 | 136 | static inline void lpar_cppr_info(int n_cpu, u8 value) |
1da177e4 LT |
137 | { |
138 | unsigned long lpar_rc; | |
139 | ||
140 | lpar_rc = plpar_cppr(value); | |
706c8c93 | 141 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 142 | panic("bad return code cppr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
143 | } |
144 | ||
b9e5b4e6 | 145 | static inline void lpar_qirr_info(int n_cpu , u8 value) |
1da177e4 LT |
146 | { |
147 | unsigned long lpar_rc; | |
148 | ||
149 | lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value); | |
706c8c93 | 150 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 151 | panic("bad return code qirr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
152 | } |
153 | ||
1da177e4 | 154 | |
b9e5b4e6 | 155 | /* High level handlers and init code */ |
1da177e4 | 156 | |
1da177e4 LT |
157 | |
158 | #ifdef CONFIG_SMP | |
0ebfff14 | 159 | static int get_irq_server(unsigned int virq) |
1da177e4 LT |
160 | { |
161 | unsigned int server; | |
162 | /* For the moment only implement delivery to all cpus or one cpu */ | |
0ebfff14 | 163 | cpumask_t cpumask = irq_desc[virq].affinity; |
1da177e4 LT |
164 | cpumask_t tmp = CPU_MASK_NONE; |
165 | ||
166 | if (!distribute_irqs) | |
167 | return default_server; | |
168 | ||
169 | if (cpus_equal(cpumask, CPU_MASK_ALL)) { | |
170 | server = default_distrib_server; | |
171 | } else { | |
172 | cpus_and(tmp, cpu_online_map, cpumask); | |
173 | ||
174 | if (cpus_empty(tmp)) | |
175 | server = default_distrib_server; | |
176 | else | |
177 | server = get_hard_smp_processor_id(first_cpu(tmp)); | |
178 | } | |
179 | ||
180 | return server; | |
181 | ||
182 | } | |
183 | #else | |
0ebfff14 | 184 | static int get_irq_server(unsigned int virq) |
1da177e4 LT |
185 | { |
186 | return default_server; | |
187 | } | |
188 | #endif | |
189 | ||
b9e5b4e6 BH |
190 | |
191 | static void xics_unmask_irq(unsigned int virq) | |
1da177e4 LT |
192 | { |
193 | unsigned int irq; | |
194 | int call_status; | |
195 | unsigned int server; | |
196 | ||
0ebfff14 BH |
197 | pr_debug("xics: unmask virq %d\n", virq); |
198 | ||
199 | irq = (unsigned int)irq_map[virq].hwirq; | |
200 | pr_debug(" -> map to hwirq 0x%x\n", irq); | |
201 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
1da177e4 LT |
202 | return; |
203 | ||
204 | server = get_irq_server(virq); | |
b9e5b4e6 | 205 | |
1da177e4 LT |
206 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, |
207 | DEFAULT_PRIORITY); | |
208 | if (call_status != 0) { | |
26370322 AB |
209 | printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_set_xive " |
210 | "returned %d\n", irq, call_status); | |
211 | printk("set_xive %x, server %x\n", ibm_set_xive, server); | |
1da177e4 LT |
212 | return; |
213 | } | |
214 | ||
215 | /* Now unmask the interrupt (often a no-op) */ | |
216 | call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq); | |
217 | if (call_status != 0) { | |
26370322 AB |
218 | printk(KERN_ERR "xics_enable_irq: irq=%u: ibm_int_on " |
219 | "returned %d\n", irq, call_status); | |
1da177e4 LT |
220 | return; |
221 | } | |
222 | } | |
223 | ||
b9e5b4e6 | 224 | static void xics_mask_real_irq(unsigned int irq) |
1da177e4 LT |
225 | { |
226 | int call_status; | |
1da177e4 LT |
227 | |
228 | if (irq == XICS_IPI) | |
229 | return; | |
230 | ||
231 | call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq); | |
232 | if (call_status != 0) { | |
26370322 AB |
233 | printk(KERN_ERR "xics_disable_real_irq: irq=%u: " |
234 | "ibm_int_off returned %d\n", irq, call_status); | |
1da177e4 LT |
235 | return; |
236 | } | |
237 | ||
1da177e4 | 238 | /* Have to set XIVE to 0xff to be able to remove a slot */ |
673aeb76 MO |
239 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, |
240 | default_server, 0xff); | |
1da177e4 | 241 | if (call_status != 0) { |
26370322 AB |
242 | printk(KERN_ERR "xics_disable_irq: irq=%u: ibm_set_xive(0xff)" |
243 | " returned %d\n", irq, call_status); | |
1da177e4 LT |
244 | return; |
245 | } | |
246 | } | |
247 | ||
b9e5b4e6 | 248 | static void xics_mask_irq(unsigned int virq) |
1da177e4 LT |
249 | { |
250 | unsigned int irq; | |
251 | ||
0ebfff14 BH |
252 | pr_debug("xics: mask virq %d\n", virq); |
253 | ||
254 | irq = (unsigned int)irq_map[virq].hwirq; | |
255 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
256 | return; | |
257 | xics_mask_real_irq(irq); | |
b9e5b4e6 BH |
258 | } |
259 | ||
0ebfff14 | 260 | static unsigned int xics_startup(unsigned int virq) |
b9e5b4e6 BH |
261 | { |
262 | unsigned int irq; | |
263 | ||
0ebfff14 BH |
264 | /* force a reverse mapping of the interrupt so it gets in the cache */ |
265 | irq = (unsigned int)irq_map[virq].hwirq; | |
266 | irq_radix_revmap(xics_host, irq); | |
1da177e4 | 267 | |
0ebfff14 | 268 | /* unmask it */ |
b9e5b4e6 BH |
269 | xics_unmask_irq(virq); |
270 | return 0; | |
271 | } | |
272 | ||
0ebfff14 | 273 | static void xics_eoi_direct(unsigned int virq) |
1da177e4 LT |
274 | { |
275 | int cpu = smp_processor_id(); | |
0ebfff14 | 276 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; |
1da177e4 LT |
277 | |
278 | iosync(); | |
0ebfff14 | 279 | direct_xirr_info_set(cpu, (0xff << 24) | irq); |
1da177e4 LT |
280 | } |
281 | ||
b9e5b4e6 | 282 | |
0ebfff14 | 283 | static void xics_eoi_lpar(unsigned int virq) |
1da177e4 LT |
284 | { |
285 | int cpu = smp_processor_id(); | |
0ebfff14 | 286 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; |
1da177e4 | 287 | |
b9e5b4e6 | 288 | iosync(); |
0ebfff14 | 289 | lpar_xirr_info_set(cpu, (0xff << 24) | irq); |
1da177e4 LT |
290 | } |
291 | ||
0ebfff14 | 292 | static inline unsigned int xics_remap_irq(unsigned int vec) |
1da177e4 | 293 | { |
0ebfff14 | 294 | unsigned int irq; |
1da177e4 | 295 | |
1da177e4 LT |
296 | vec &= 0x00ffffff; |
297 | ||
b9e5b4e6 BH |
298 | if (vec == XICS_IRQ_SPURIOUS) |
299 | return NO_IRQ; | |
0ebfff14 | 300 | irq = irq_radix_revmap(xics_host, vec); |
b9e5b4e6 | 301 | if (likely(irq != NO_IRQ)) |
0ebfff14 | 302 | return irq; |
b9e5b4e6 BH |
303 | |
304 | printk(KERN_ERR "Interrupt %u (real) is invalid," | |
305 | " disabling it.\n", vec); | |
306 | xics_mask_real_irq(vec); | |
307 | return NO_IRQ; | |
1da177e4 LT |
308 | } |
309 | ||
35a84c2f | 310 | static unsigned int xics_get_irq_direct(void) |
b9e5b4e6 BH |
311 | { |
312 | unsigned int cpu = smp_processor_id(); | |
1da177e4 | 313 | |
b9e5b4e6 BH |
314 | return xics_remap_irq(direct_xirr_info_get(cpu)); |
315 | } | |
316 | ||
35a84c2f | 317 | static unsigned int xics_get_irq_lpar(void) |
1da177e4 | 318 | { |
b9e5b4e6 | 319 | unsigned int cpu = smp_processor_id(); |
1da177e4 | 320 | |
b9e5b4e6 BH |
321 | return xics_remap_irq(lpar_xirr_info_get(cpu)); |
322 | } | |
323 | ||
324 | #ifdef CONFIG_SMP | |
1da177e4 | 325 | |
7d12e780 | 326 | static irqreturn_t xics_ipi_dispatch(int cpu) |
b9e5b4e6 | 327 | { |
1da177e4 LT |
328 | WARN_ON(cpu_is_offline(cpu)); |
329 | ||
330 | while (xics_ipi_message[cpu].value) { | |
331 | if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, | |
332 | &xics_ipi_message[cpu].value)) { | |
333 | mb(); | |
7d12e780 | 334 | smp_message_recv(PPC_MSG_CALL_FUNCTION); |
1da177e4 LT |
335 | } |
336 | if (test_and_clear_bit(PPC_MSG_RESCHEDULE, | |
337 | &xics_ipi_message[cpu].value)) { | |
338 | mb(); | |
7d12e780 | 339 | smp_message_recv(PPC_MSG_RESCHEDULE); |
1da177e4 LT |
340 | } |
341 | #if 0 | |
342 | if (test_and_clear_bit(PPC_MSG_MIGRATE_TASK, | |
343 | &xics_ipi_message[cpu].value)) { | |
344 | mb(); | |
7d12e780 | 345 | smp_message_recv(PPC_MSG_MIGRATE_TASK); |
1da177e4 LT |
346 | } |
347 | #endif | |
cc532915 | 348 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
1da177e4 LT |
349 | if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, |
350 | &xics_ipi_message[cpu].value)) { | |
351 | mb(); | |
7d12e780 | 352 | smp_message_recv(PPC_MSG_DEBUGGER_BREAK); |
1da177e4 LT |
353 | } |
354 | #endif | |
355 | } | |
356 | return IRQ_HANDLED; | |
357 | } | |
358 | ||
7d12e780 | 359 | static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id) |
b9e5b4e6 BH |
360 | { |
361 | int cpu = smp_processor_id(); | |
362 | ||
363 | direct_qirr_info(cpu, 0xff); | |
364 | ||
7d12e780 | 365 | return xics_ipi_dispatch(cpu); |
b9e5b4e6 BH |
366 | } |
367 | ||
7d12e780 | 368 | static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id) |
b9e5b4e6 BH |
369 | { |
370 | int cpu = smp_processor_id(); | |
371 | ||
372 | lpar_qirr_info(cpu, 0xff); | |
373 | ||
7d12e780 | 374 | return xics_ipi_dispatch(cpu); |
b9e5b4e6 BH |
375 | } |
376 | ||
1da177e4 LT |
377 | void xics_cause_IPI(int cpu) |
378 | { | |
b9e5b4e6 BH |
379 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
380 | lpar_qirr_info(cpu, IPI_PRIORITY); | |
381 | else | |
382 | direct_qirr_info(cpu, IPI_PRIORITY); | |
1da177e4 | 383 | } |
b9e5b4e6 | 384 | |
6c80a21c | 385 | #endif /* CONFIG_SMP */ |
1da177e4 | 386 | |
b9e5b4e6 BH |
387 | static void xics_set_cpu_priority(int cpu, unsigned char cppr) |
388 | { | |
389 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
390 | lpar_cppr_info(cpu, cppr); | |
391 | else | |
392 | direct_cppr_info(cpu, cppr); | |
393 | iosync(); | |
394 | } | |
395 | ||
396 | static void xics_set_affinity(unsigned int virq, cpumask_t cpumask) | |
397 | { | |
398 | unsigned int irq; | |
399 | int status; | |
400 | int xics_status[2]; | |
401 | unsigned long newmask; | |
402 | cpumask_t tmp = CPU_MASK_NONE; | |
403 | ||
0ebfff14 BH |
404 | irq = (unsigned int)irq_map[virq].hwirq; |
405 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
b9e5b4e6 BH |
406 | return; |
407 | ||
408 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
409 | ||
410 | if (status) { | |
411 | printk(KERN_ERR "xics_set_affinity: irq=%u ibm,get-xive " | |
412 | "returns %d\n", irq, status); | |
413 | return; | |
414 | } | |
415 | ||
416 | /* For the moment only implement delivery to all cpus or one cpu */ | |
417 | if (cpus_equal(cpumask, CPU_MASK_ALL)) { | |
418 | newmask = default_distrib_server; | |
419 | } else { | |
420 | cpus_and(tmp, cpu_online_map, cpumask); | |
421 | if (cpus_empty(tmp)) | |
422 | return; | |
423 | newmask = get_hard_smp_processor_id(first_cpu(tmp)); | |
424 | } | |
425 | ||
426 | status = rtas_call(ibm_set_xive, 3, 1, NULL, | |
427 | irq, newmask, xics_status[1]); | |
428 | ||
429 | if (status) { | |
430 | printk(KERN_ERR "xics_set_affinity: irq=%u ibm,set-xive " | |
431 | "returns %d\n", irq, status); | |
432 | return; | |
433 | } | |
434 | } | |
435 | ||
0ebfff14 BH |
436 | void xics_setup_cpu(void) |
437 | { | |
438 | int cpu = smp_processor_id(); | |
439 | ||
440 | xics_set_cpu_priority(cpu, 0xff); | |
441 | ||
442 | /* | |
443 | * Put the calling processor into the GIQ. This is really only | |
444 | * necessary from a secondary thread as the OF start-cpu interface | |
445 | * performs this function for us on primary threads. | |
446 | * | |
447 | * XXX: undo of teardown on kexec needs this too, as may hotplug | |
448 | */ | |
81b73dd9 | 449 | rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, |
0ebfff14 BH |
450 | (1UL << interrupt_server_size) - 1 - default_distrib_server, 1); |
451 | } | |
452 | ||
453 | ||
b9e5b4e6 BH |
454 | static struct irq_chip xics_pic_direct = { |
455 | .typename = " XICS ", | |
456 | .startup = xics_startup, | |
457 | .mask = xics_mask_irq, | |
458 | .unmask = xics_unmask_irq, | |
459 | .eoi = xics_eoi_direct, | |
460 | .set_affinity = xics_set_affinity | |
461 | }; | |
462 | ||
463 | ||
464 | static struct irq_chip xics_pic_lpar = { | |
465 | .typename = " XICS ", | |
466 | .startup = xics_startup, | |
467 | .mask = xics_mask_irq, | |
468 | .unmask = xics_unmask_irq, | |
469 | .eoi = xics_eoi_lpar, | |
470 | .set_affinity = xics_set_affinity | |
471 | }; | |
472 | ||
473 | ||
0ebfff14 | 474 | static int xics_host_match(struct irq_host *h, struct device_node *node) |
1da177e4 | 475 | { |
0ebfff14 BH |
476 | /* IBM machines have interrupt parents of various funky types for things |
477 | * like vdevices, events, etc... The trick we use here is to match | |
478 | * everything here except the legacy 8259 which is compatible "chrp,iic" | |
479 | */ | |
480 | return !device_is_compatible(node, "chrp,iic"); | |
481 | } | |
1da177e4 | 482 | |
0ebfff14 | 483 | static int xics_host_map_direct(struct irq_host *h, unsigned int virq, |
6e99e458 | 484 | irq_hw_number_t hw) |
0ebfff14 | 485 | { |
6e99e458 | 486 | pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 BH |
487 | |
488 | get_irq_desc(virq)->status |= IRQ_LEVEL; | |
489 | set_irq_chip_and_handler(virq, &xics_pic_direct, handle_fasteoi_irq); | |
490 | return 0; | |
491 | } | |
492 | ||
493 | static int xics_host_map_lpar(struct irq_host *h, unsigned int virq, | |
6e99e458 | 494 | irq_hw_number_t hw) |
0ebfff14 | 495 | { |
6e99e458 | 496 | pr_debug("xics: map_direct virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 BH |
497 | |
498 | get_irq_desc(virq)->status |= IRQ_LEVEL; | |
499 | set_irq_chip_and_handler(virq, &xics_pic_lpar, handle_fasteoi_irq); | |
500 | return 0; | |
501 | } | |
502 | ||
503 | static int xics_host_xlate(struct irq_host *h, struct device_node *ct, | |
504 | u32 *intspec, unsigned int intsize, | |
505 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) | |
506 | ||
507 | { | |
508 | /* Current xics implementation translates everything | |
509 | * to level. It is not technically right for MSIs but this | |
510 | * is irrelevant at this point. We might get smarter in the future | |
6c80a21c | 511 | */ |
0ebfff14 BH |
512 | *out_hwirq = intspec[0]; |
513 | *out_flags = IRQ_TYPE_LEVEL_LOW; | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
518 | static struct irq_host_ops xics_host_direct_ops = { | |
519 | .match = xics_host_match, | |
520 | .map = xics_host_map_direct, | |
521 | .xlate = xics_host_xlate, | |
522 | }; | |
523 | ||
524 | static struct irq_host_ops xics_host_lpar_ops = { | |
525 | .match = xics_host_match, | |
526 | .map = xics_host_map_lpar, | |
527 | .xlate = xics_host_xlate, | |
528 | }; | |
529 | ||
530 | static void __init xics_init_host(void) | |
531 | { | |
532 | struct irq_host_ops *ops; | |
533 | ||
534 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
535 | ops = &xics_host_lpar_ops; | |
536 | else | |
537 | ops = &xics_host_direct_ops; | |
538 | xics_host = irq_alloc_host(IRQ_HOST_MAP_TREE, 0, ops, | |
539 | XICS_IRQ_SPURIOUS); | |
540 | BUG_ON(xics_host == NULL); | |
541 | irq_set_default_host(xics_host); | |
6c80a21c | 542 | } |
1da177e4 | 543 | |
0ebfff14 BH |
544 | static void __init xics_map_one_cpu(int hw_id, unsigned long addr, |
545 | unsigned long size) | |
1da177e4 | 546 | { |
0ebfff14 | 547 | #ifdef CONFIG_SMP |
1da177e4 | 548 | int i; |
1da177e4 | 549 | |
0ebfff14 BH |
550 | /* This may look gross but it's good enough for now, we don't quite |
551 | * have a hard -> linux processor id matching. | |
552 | */ | |
553 | for_each_possible_cpu(i) { | |
554 | if (!cpu_present(i)) | |
555 | continue; | |
556 | if (hw_id == get_hard_smp_processor_id(i)) { | |
557 | xics_per_cpu[i] = ioremap(addr, size); | |
558 | return; | |
559 | } | |
560 | } | |
561 | #else | |
562 | if (hw_id != 0) | |
563 | return; | |
564 | xics_per_cpu[0] = ioremap(addr, size); | |
565 | #endif /* CONFIG_SMP */ | |
566 | } | |
1da177e4 | 567 | |
0ebfff14 BH |
568 | static void __init xics_init_one_node(struct device_node *np, |
569 | unsigned int *indx) | |
570 | { | |
571 | unsigned int ilen; | |
954a46e2 | 572 | const u32 *ireg; |
1da177e4 | 573 | |
0ebfff14 BH |
574 | /* This code does the theorically broken assumption that the interrupt |
575 | * server numbers are the same as the hard CPU numbers. | |
576 | * This happens to be the case so far but we are playing with fire... | |
577 | * should be fixed one of these days. -BenH. | |
578 | */ | |
e2eb6392 | 579 | ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL); |
1da177e4 | 580 | |
0ebfff14 BH |
581 | /* Do that ever happen ? we'll know soon enough... but even good'old |
582 | * f80 does have that property .. | |
583 | */ | |
584 | WARN_ON(ireg == NULL); | |
1da177e4 LT |
585 | if (ireg) { |
586 | /* | |
587 | * set node starting index for this node | |
588 | */ | |
0ebfff14 | 589 | *indx = *ireg; |
1da177e4 | 590 | } |
e2eb6392 | 591 | ireg = of_get_property(np, "reg", &ilen); |
1da177e4 LT |
592 | if (!ireg) |
593 | panic("xics_init_IRQ: can't find interrupt reg property"); | |
007e8f51 | 594 | |
0ebfff14 BH |
595 | while (ilen >= (4 * sizeof(u32))) { |
596 | unsigned long addr, size; | |
597 | ||
598 | /* XXX Use proper OF parsing code here !!! */ | |
599 | addr = (unsigned long)*ireg++ << 32; | |
600 | ilen -= sizeof(u32); | |
601 | addr |= *ireg++; | |
602 | ilen -= sizeof(u32); | |
603 | size = (unsigned long)*ireg++ << 32; | |
604 | ilen -= sizeof(u32); | |
605 | size |= *ireg++; | |
606 | ilen -= sizeof(u32); | |
607 | xics_map_one_cpu(*indx, addr, size); | |
608 | (*indx)++; | |
609 | } | |
610 | } | |
611 | ||
612 | ||
613 | static void __init xics_setup_8259_cascade(void) | |
614 | { | |
615 | struct device_node *np, *old, *found = NULL; | |
616 | int cascade, naddr; | |
954a46e2 | 617 | const u32 *addrp; |
0ebfff14 BH |
618 | unsigned long intack = 0; |
619 | ||
620 | for_each_node_by_type(np, "interrupt-controller") | |
621 | if (device_is_compatible(np, "chrp,iic")) { | |
622 | found = np; | |
623 | break; | |
624 | } | |
625 | if (found == NULL) { | |
626 | printk(KERN_DEBUG "xics: no ISA interrupt controller\n"); | |
627 | return; | |
1da177e4 | 628 | } |
0ebfff14 BH |
629 | cascade = irq_of_parse_and_map(found, 0); |
630 | if (cascade == NO_IRQ) { | |
631 | printk(KERN_ERR "xics: failed to map cascade interrupt"); | |
632 | return; | |
633 | } | |
634 | pr_debug("xics: cascade mapped to irq %d\n", cascade); | |
635 | ||
636 | for (old = of_node_get(found); old != NULL ; old = np) { | |
637 | np = of_get_parent(old); | |
638 | of_node_put(old); | |
639 | if (np == NULL) | |
640 | break; | |
641 | if (strcmp(np->name, "pci") != 0) | |
642 | continue; | |
e2eb6392 | 643 | addrp = of_get_property(np, "8259-interrupt-acknowledge", NULL); |
0ebfff14 BH |
644 | if (addrp == NULL) |
645 | continue; | |
a8bda5dd | 646 | naddr = of_n_addr_cells(np); |
0ebfff14 BH |
647 | intack = addrp[naddr-1]; |
648 | if (naddr > 1) | |
649 | intack |= ((unsigned long)addrp[naddr-2]) << 32; | |
650 | } | |
651 | if (intack) | |
652 | printk(KERN_DEBUG "xics: PCI 8259 intack at 0x%016lx\n", intack); | |
653 | i8259_init(found, intack); | |
654 | of_node_put(found); | |
655 | set_irq_chained_handler(cascade, pseries_8259_cascade); | |
656 | } | |
1da177e4 | 657 | |
a5715d6d MK |
658 | static struct device_node *cpuid_to_of_node(int cpu) |
659 | { | |
660 | struct device_node *np; | |
661 | u32 hcpuid = get_hard_smp_processor_id(cpu); | |
662 | ||
663 | for_each_node_by_type(np, "cpu") { | |
664 | int i, len; | |
665 | const u32 *intserv; | |
666 | ||
e2eb6392 SR |
667 | intserv = of_get_property(np, "ibm,ppc-interrupt-server#s", |
668 | &len); | |
a5715d6d MK |
669 | |
670 | if (!intserv) | |
e2eb6392 | 671 | intserv = of_get_property(np, "reg", &len); |
a5715d6d MK |
672 | |
673 | i = len / sizeof(u32); | |
674 | ||
675 | while (i--) | |
676 | if (intserv[i] == hcpuid) | |
677 | return np; | |
678 | } | |
679 | ||
680 | return NULL; | |
681 | } | |
682 | ||
0ebfff14 BH |
683 | void __init xics_init_IRQ(void) |
684 | { | |
a5715d6d | 685 | int i, j; |
0ebfff14 | 686 | struct device_node *np; |
954a46e2 | 687 | u32 ilen, indx = 0; |
a5715d6d | 688 | const u32 *ireg, *isize; |
0ebfff14 | 689 | int found = 0; |
a5715d6d | 690 | u32 hcpuid; |
0ebfff14 BH |
691 | |
692 | ppc64_boot_msg(0x20, "XICS Init"); | |
693 | ||
694 | ibm_get_xive = rtas_token("ibm,get-xive"); | |
695 | ibm_set_xive = rtas_token("ibm,set-xive"); | |
696 | ibm_int_on = rtas_token("ibm,int-on"); | |
697 | ibm_int_off = rtas_token("ibm,int-off"); | |
698 | ||
699 | for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") { | |
700 | found = 1; | |
701 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
702 | break; | |
703 | xics_init_one_node(np, &indx); | |
704 | } | |
705 | if (found == 0) | |
706 | return; | |
707 | ||
708 | xics_init_host(); | |
1da177e4 LT |
709 | |
710 | /* Find the server numbers for the boot cpu. */ | |
a5715d6d MK |
711 | np = cpuid_to_of_node(boot_cpuid); |
712 | BUG_ON(!np); | |
e2eb6392 | 713 | ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); |
a5715d6d MK |
714 | if (!ireg) |
715 | goto skip_gserver_check; | |
716 | i = ilen / sizeof(int); | |
717 | hcpuid = get_hard_smp_processor_id(boot_cpuid); | |
718 | ||
719 | /* Global interrupt distribution server is specified in the last | |
720 | * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last | |
721 | * entry fom this property for current boot cpu id and use it as | |
722 | * default distribution server | |
723 | */ | |
724 | for (j = 0; j < i; j += 2) { | |
725 | if (ireg[j] == hcpuid) { | |
726 | default_server = hcpuid; | |
727 | default_distrib_server = ireg[j+1]; | |
728 | ||
e2eb6392 | 729 | isize = of_get_property(np, |
1da177e4 | 730 | "ibm,interrupt-server#-size", NULL); |
a5715d6d MK |
731 | if (isize) |
732 | interrupt_server_size = *isize; | |
1da177e4 LT |
733 | } |
734 | } | |
a5715d6d | 735 | skip_gserver_check: |
1da177e4 LT |
736 | of_node_put(np); |
737 | ||
0ebfff14 BH |
738 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
739 | ppc_md.get_irq = xics_get_irq_lpar; | |
740 | else | |
b9e5b4e6 | 741 | ppc_md.get_irq = xics_get_irq_direct; |
1da177e4 | 742 | |
6c80a21c | 743 | xics_setup_cpu(); |
1da177e4 | 744 | |
0ebfff14 | 745 | xics_setup_8259_cascade(); |
1da177e4 | 746 | |
0ebfff14 | 747 | ppc64_boot_msg(0x21, "XICS Done"); |
1da177e4 | 748 | } |
b9e5b4e6 | 749 | |
1da177e4 LT |
750 | |
751 | #ifdef CONFIG_SMP | |
752 | void xics_request_IPIs(void) | |
753 | { | |
0ebfff14 BH |
754 | unsigned int ipi; |
755 | ||
6e99e458 | 756 | ipi = irq_create_mapping(xics_host, XICS_IPI); |
0ebfff14 | 757 | BUG_ON(ipi == NO_IRQ); |
1da177e4 | 758 | |
6714465e TG |
759 | /* |
760 | * IPIs are marked IRQF_DISABLED as they must run with irqs | |
761 | * disabled | |
762 | */ | |
0ebfff14 | 763 | set_irq_handler(ipi, handle_percpu_irq); |
b9e5b4e6 | 764 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
0ebfff14 BH |
765 | request_irq(ipi, xics_ipi_action_lpar, IRQF_DISABLED, |
766 | "IPI", NULL); | |
b9e5b4e6 | 767 | else |
0ebfff14 BH |
768 | request_irq(ipi, xics_ipi_action_direct, IRQF_DISABLED, |
769 | "IPI", NULL); | |
1da177e4 | 770 | } |
b9e5b4e6 | 771 | #endif /* CONFIG_SMP */ |
1da177e4 | 772 | |
6d22d85a | 773 | void xics_teardown_cpu(int secondary) |
fce0d574 S |
774 | { |
775 | int cpu = smp_processor_id(); | |
0ebfff14 BH |
776 | unsigned int ipi; |
777 | struct irq_desc *desc; | |
fce0d574 | 778 | |
0ebfff14 | 779 | xics_set_cpu_priority(cpu, 0); |
81bbbe92 | 780 | |
6e99e458 BH |
781 | /* |
782 | * Clear IPI | |
783 | */ | |
784 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
785 | lpar_qirr_info(cpu, 0xff); | |
786 | else | |
787 | direct_qirr_info(cpu, 0xff); | |
788 | ||
81bbbe92 HM |
789 | /* |
790 | * we need to EOI the IPI if we got here from kexec down IPI | |
791 | * | |
792 | * probably need to check all the other interrupts too | |
793 | * should we be flagging idle loop instead? | |
794 | * or creating some task to be scheduled? | |
795 | */ | |
0ebfff14 BH |
796 | |
797 | ipi = irq_find_mapping(xics_host, XICS_IPI); | |
798 | if (ipi == XICS_IRQ_SPURIOUS) | |
799 | return; | |
800 | desc = get_irq_desc(ipi); | |
b9e5b4e6 | 801 | if (desc->chip && desc->chip->eoi) |
6e99e458 | 802 | desc->chip->eoi(ipi); |
81bbbe92 | 803 | |
fce0d574 | 804 | /* |
6d22d85a PM |
805 | * Some machines need to have at least one cpu in the GIQ, |
806 | * so leave the master cpu in the group. | |
fce0d574 | 807 | */ |
81bbbe92 | 808 | if (secondary) |
81b73dd9 | 809 | rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, |
0ebfff14 BH |
810 | (1UL << interrupt_server_size) - 1 - |
811 | default_distrib_server, 0); | |
fce0d574 S |
812 | } |
813 | ||
1da177e4 LT |
814 | #ifdef CONFIG_HOTPLUG_CPU |
815 | ||
816 | /* Interrupts are disabled. */ | |
817 | void xics_migrate_irqs_away(void) | |
818 | { | |
819 | int status; | |
820 | unsigned int irq, virq, cpu = smp_processor_id(); | |
821 | ||
822 | /* Reject any interrupt that was queued to us... */ | |
b9e5b4e6 | 823 | xics_set_cpu_priority(cpu, 0); |
1da177e4 LT |
824 | |
825 | /* remove ourselves from the global interrupt queue */ | |
81b73dd9 | 826 | status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, |
1da177e4 LT |
827 | (1UL << interrupt_server_size) - 1 - default_distrib_server, 0); |
828 | WARN_ON(status < 0); | |
829 | ||
830 | /* Allow IPIs again... */ | |
b9e5b4e6 | 831 | xics_set_cpu_priority(cpu, DEFAULT_PRIORITY); |
1da177e4 LT |
832 | |
833 | for_each_irq(virq) { | |
b9e5b4e6 | 834 | struct irq_desc *desc; |
1da177e4 LT |
835 | int xics_status[2]; |
836 | unsigned long flags; | |
837 | ||
838 | /* We cant set affinity on ISA interrupts */ | |
0ebfff14 | 839 | if (virq < NUM_ISA_INTERRUPTS) |
1da177e4 | 840 | continue; |
0ebfff14 BH |
841 | if (irq_map[virq].host != xics_host) |
842 | continue; | |
843 | irq = (unsigned int)irq_map[virq].hwirq; | |
1da177e4 | 844 | /* We need to get IPIs still. */ |
0ebfff14 | 845 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
1da177e4 | 846 | continue; |
0ebfff14 | 847 | desc = get_irq_desc(virq); |
1da177e4 LT |
848 | |
849 | /* We only need to migrate enabled IRQS */ | |
d1bef4ed | 850 | if (desc == NULL || desc->chip == NULL |
1da177e4 | 851 | || desc->action == NULL |
d1bef4ed | 852 | || desc->chip->set_affinity == NULL) |
1da177e4 LT |
853 | continue; |
854 | ||
855 | spin_lock_irqsave(&desc->lock, flags); | |
856 | ||
857 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
858 | if (status) { | |
26370322 | 859 | printk(KERN_ERR "migrate_irqs_away: irq=%u " |
1da177e4 LT |
860 | "ibm,get-xive returns %d\n", |
861 | virq, status); | |
862 | goto unlock; | |
863 | } | |
864 | ||
865 | /* | |
866 | * We only support delivery to all cpus or to one cpu. | |
867 | * The irq has to be migrated only in the single cpu | |
868 | * case. | |
869 | */ | |
870 | if (xics_status[0] != get_hard_smp_processor_id(cpu)) | |
871 | goto unlock; | |
872 | ||
26370322 | 873 | printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n", |
1da177e4 LT |
874 | virq, cpu); |
875 | ||
876 | /* Reset affinity to all cpus */ | |
d1bef4ed | 877 | desc->chip->set_affinity(virq, CPU_MASK_ALL); |
a53da52f | 878 | irq_desc[irq].affinity = CPU_MASK_ALL; |
1da177e4 LT |
879 | unlock: |
880 | spin_unlock_irqrestore(&desc->lock, flags); | |
881 | } | |
882 | } | |
883 | #endif |