Commit | Line | Data |
---|---|---|
007e8f51 DG |
1 | /* |
2 | * arch/powerpc/platforms/pseries/xics.c | |
1da177e4 LT |
3 | * |
4 | * Copyright 2000 IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
0ebfff14 | 11 | |
1da177e4 LT |
12 | #include <linux/types.h> |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/irq.h> | |
16 | #include <linux/smp.h> | |
17 | #include <linux/interrupt.h> | |
1da177e4 | 18 | #include <linux/init.h> |
1da177e4 LT |
19 | #include <linux/radix-tree.h> |
20 | #include <linux/cpu.h> | |
8435b027 | 21 | #include <linux/msi.h> |
188bdddd | 22 | #include <linux/of.h> |
0ebfff14 | 23 | |
57cfb814 | 24 | #include <asm/firmware.h> |
1da177e4 LT |
25 | #include <asm/io.h> |
26 | #include <asm/pgtable.h> | |
27 | #include <asm/smp.h> | |
28 | #include <asm/rtas.h> | |
1da177e4 LT |
29 | #include <asm/hvcall.h> |
30 | #include <asm/machdep.h> | |
1da177e4 | 31 | |
007e8f51 | 32 | #include "xics.h" |
b9377ffc | 33 | #include "plpar_wrappers.h" |
007e8f51 | 34 | |
0641cc91 MM |
35 | static struct irq_host *xics_host; |
36 | ||
1da177e4 LT |
37 | #define XICS_IPI 2 |
38 | #define XICS_IRQ_SPURIOUS 0 | |
39 | ||
40 | /* Want a priority other than 0. Various HW issues require this. */ | |
41 | #define DEFAULT_PRIORITY 5 | |
42 | ||
007e8f51 | 43 | /* |
1da177e4 | 44 | * Mark IPIs as higher priority so we can take them inside interrupts that |
6714465e | 45 | * arent marked IRQF_DISABLED |
1da177e4 LT |
46 | */ |
47 | #define IPI_PRIORITY 4 | |
48 | ||
0641cc91 MM |
49 | static unsigned int default_server = 0xFF; |
50 | static unsigned int default_distrib_server = 0; | |
51 | static unsigned int interrupt_server_size = 8; | |
52 | ||
53 | /* RTAS service tokens */ | |
54 | static int ibm_get_xive; | |
55 | static int ibm_set_xive; | |
56 | static int ibm_int_on; | |
57 | static int ibm_int_off; | |
58 | ||
59 | ||
60 | /* Direct hardware low level accessors */ | |
61 | ||
62 | /* The part of the interrupt presentation layer that we care about */ | |
1da177e4 LT |
63 | struct xics_ipl { |
64 | union { | |
65 | u32 word; | |
66 | u8 bytes[4]; | |
67 | } xirr_poll; | |
68 | union { | |
69 | u32 word; | |
70 | u8 bytes[4]; | |
71 | } xirr; | |
72 | u32 dummy; | |
73 | union { | |
74 | u32 word; | |
75 | u8 bytes[4]; | |
76 | } qirr; | |
77 | }; | |
78 | ||
79 | static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS]; | |
80 | ||
d7cf0edb | 81 | static inline unsigned int direct_xirr_info_get(void) |
1da177e4 | 82 | { |
d7cf0edb MM |
83 | int cpu = smp_processor_id(); |
84 | ||
85 | return in_be32(&xics_per_cpu[cpu]->xirr.word); | |
1da177e4 LT |
86 | } |
87 | ||
9dc2d441 | 88 | static inline void direct_xirr_info_set(unsigned int value) |
1da177e4 | 89 | { |
d7cf0edb MM |
90 | int cpu = smp_processor_id(); |
91 | ||
92 | out_be32(&xics_per_cpu[cpu]->xirr.word, value); | |
1da177e4 LT |
93 | } |
94 | ||
d7cf0edb | 95 | static inline void direct_cppr_info(u8 value) |
1da177e4 | 96 | { |
d7cf0edb MM |
97 | int cpu = smp_processor_id(); |
98 | ||
99 | out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value); | |
1da177e4 LT |
100 | } |
101 | ||
b9e5b4e6 | 102 | static inline void direct_qirr_info(int n_cpu, u8 value) |
1da177e4 LT |
103 | { |
104 | out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value); | |
105 | } | |
106 | ||
1da177e4 | 107 | |
b9e5b4e6 | 108 | /* LPAR low level accessors */ |
1da177e4 | 109 | |
d7cf0edb | 110 | static inline unsigned int lpar_xirr_info_get(void) |
1da177e4 LT |
111 | { |
112 | unsigned long lpar_rc; | |
007e8f51 | 113 | unsigned long return_value; |
1da177e4 LT |
114 | |
115 | lpar_rc = plpar_xirr(&return_value); | |
706c8c93 | 116 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 117 | panic(" bad return code xirr - rc = %lx \n", lpar_rc); |
0ebfff14 | 118 | return (unsigned int)return_value; |
1da177e4 LT |
119 | } |
120 | ||
9dc2d441 | 121 | static inline void lpar_xirr_info_set(unsigned int value) |
1da177e4 LT |
122 | { |
123 | unsigned long lpar_rc; | |
1da177e4 | 124 | |
9dc2d441 | 125 | lpar_rc = plpar_eoi(value); |
706c8c93 | 126 | if (lpar_rc != H_SUCCESS) |
9dc2d441 MM |
127 | panic("bad return code EOI - rc = %ld, value=%x\n", lpar_rc, |
128 | value); | |
1da177e4 LT |
129 | } |
130 | ||
d7cf0edb | 131 | static inline void lpar_cppr_info(u8 value) |
1da177e4 LT |
132 | { |
133 | unsigned long lpar_rc; | |
134 | ||
135 | lpar_rc = plpar_cppr(value); | |
706c8c93 | 136 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 137 | panic("bad return code cppr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
138 | } |
139 | ||
b9e5b4e6 | 140 | static inline void lpar_qirr_info(int n_cpu , u8 value) |
1da177e4 LT |
141 | { |
142 | unsigned long lpar_rc; | |
143 | ||
144 | lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value); | |
706c8c93 | 145 | if (lpar_rc != H_SUCCESS) |
007e8f51 | 146 | panic("bad return code qirr - rc = %lx\n", lpar_rc); |
1da177e4 LT |
147 | } |
148 | ||
1da177e4 | 149 | |
0641cc91 | 150 | /* Interface to generic irq subsystem */ |
1da177e4 LT |
151 | |
152 | #ifdef CONFIG_SMP | |
7ccb4a66 | 153 | static int get_irq_server(unsigned int virq, unsigned int strict_check) |
1da177e4 | 154 | { |
7ccb4a66 | 155 | int server; |
1da177e4 | 156 | /* For the moment only implement delivery to all cpus or one cpu */ |
e65e49d0 | 157 | cpumask_t cpumask; |
1da177e4 LT |
158 | cpumask_t tmp = CPU_MASK_NONE; |
159 | ||
6cff46f4 | 160 | cpumask_copy(&cpumask, irq_to_desc(virq)->affinity); |
1da177e4 LT |
161 | if (!distribute_irqs) |
162 | return default_server; | |
163 | ||
7ccb4a66 | 164 | if (!cpus_equal(cpumask, CPU_MASK_ALL)) { |
1da177e4 LT |
165 | cpus_and(tmp, cpu_online_map, cpumask); |
166 | ||
7ccb4a66 MK |
167 | server = first_cpu(tmp); |
168 | ||
169 | if (server < NR_CPUS) | |
170 | return get_hard_smp_processor_id(server); | |
171 | ||
172 | if (strict_check) | |
173 | return -1; | |
1da177e4 LT |
174 | } |
175 | ||
7ccb4a66 MK |
176 | if (cpus_equal(cpu_online_map, cpu_present_map)) |
177 | return default_distrib_server; | |
1da177e4 | 178 | |
7ccb4a66 | 179 | return default_server; |
1da177e4 LT |
180 | } |
181 | #else | |
7ccb4a66 | 182 | static int get_irq_server(unsigned int virq, unsigned int strict_check) |
1da177e4 LT |
183 | { |
184 | return default_server; | |
185 | } | |
186 | #endif | |
187 | ||
b9e5b4e6 | 188 | static void xics_unmask_irq(unsigned int virq) |
1da177e4 LT |
189 | { |
190 | unsigned int irq; | |
191 | int call_status; | |
7ccb4a66 | 192 | int server; |
1da177e4 | 193 | |
b69e9e93 | 194 | pr_devel("xics: unmask virq %d\n", virq); |
0ebfff14 BH |
195 | |
196 | irq = (unsigned int)irq_map[virq].hwirq; | |
b69e9e93 | 197 | pr_devel(" -> map to hwirq 0x%x\n", irq); |
0ebfff14 | 198 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
1da177e4 LT |
199 | return; |
200 | ||
7ccb4a66 | 201 | server = get_irq_server(virq, 0); |
b9e5b4e6 | 202 | |
1da177e4 LT |
203 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, |
204 | DEFAULT_PRIORITY); | |
205 | if (call_status != 0) { | |
2172fe87 MM |
206 | printk(KERN_ERR |
207 | "%s: ibm_set_xive irq %u server %x returned %d\n", | |
208 | __func__, irq, server, call_status); | |
1da177e4 LT |
209 | return; |
210 | } | |
211 | ||
212 | /* Now unmask the interrupt (often a no-op) */ | |
213 | call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq); | |
214 | if (call_status != 0) { | |
2172fe87 MM |
215 | printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n", |
216 | __func__, irq, call_status); | |
1da177e4 LT |
217 | return; |
218 | } | |
219 | } | |
220 | ||
0641cc91 MM |
221 | static unsigned int xics_startup(unsigned int virq) |
222 | { | |
8435b027 AD |
223 | /* |
224 | * The generic MSI code returns with the interrupt disabled on the | |
225 | * card, using the MSI mask bits. Firmware doesn't appear to unmask | |
226 | * at that level, so we do it here by hand. | |
227 | */ | |
228 | if (irq_to_desc(virq)->msi_desc) | |
229 | unmask_msi_irq(virq); | |
230 | ||
0641cc91 MM |
231 | /* unmask it */ |
232 | xics_unmask_irq(virq); | |
233 | return 0; | |
234 | } | |
235 | ||
b9e5b4e6 | 236 | static void xics_mask_real_irq(unsigned int irq) |
1da177e4 LT |
237 | { |
238 | int call_status; | |
1da177e4 LT |
239 | |
240 | if (irq == XICS_IPI) | |
241 | return; | |
242 | ||
243 | call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq); | |
244 | if (call_status != 0) { | |
2172fe87 MM |
245 | printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n", |
246 | __func__, irq, call_status); | |
1da177e4 LT |
247 | return; |
248 | } | |
249 | ||
1da177e4 | 250 | /* Have to set XIVE to 0xff to be able to remove a slot */ |
673aeb76 MO |
251 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, |
252 | default_server, 0xff); | |
1da177e4 | 253 | if (call_status != 0) { |
2172fe87 MM |
254 | printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n", |
255 | __func__, irq, call_status); | |
1da177e4 LT |
256 | return; |
257 | } | |
258 | } | |
259 | ||
b9e5b4e6 | 260 | static void xics_mask_irq(unsigned int virq) |
1da177e4 LT |
261 | { |
262 | unsigned int irq; | |
263 | ||
b69e9e93 | 264 | pr_devel("xics: mask virq %d\n", virq); |
0ebfff14 BH |
265 | |
266 | irq = (unsigned int)irq_map[virq].hwirq; | |
267 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
268 | return; | |
269 | xics_mask_real_irq(irq); | |
b9e5b4e6 BH |
270 | } |
271 | ||
0641cc91 | 272 | static void xics_mask_unknown_vec(unsigned int vec) |
1da177e4 | 273 | { |
0641cc91 MM |
274 | printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec); |
275 | xics_mask_real_irq(vec); | |
1da177e4 LT |
276 | } |
277 | ||
8767e9ba | 278 | static inline unsigned int xics_xirr_vector(unsigned int xirr) |
1da177e4 | 279 | { |
8767e9ba MM |
280 | /* |
281 | * The top byte is the old cppr, to be restored on EOI. | |
282 | * The remaining 24 bits are the vector. | |
283 | */ | |
284 | return xirr & 0x00ffffff; | |
285 | } | |
286 | ||
8767e9ba MM |
287 | static unsigned int xics_get_irq_direct(void) |
288 | { | |
289 | unsigned int xirr = direct_xirr_info_get(); | |
290 | unsigned int vec = xics_xirr_vector(xirr); | |
291 | unsigned int irq; | |
1da177e4 | 292 | |
b9e5b4e6 BH |
293 | if (vec == XICS_IRQ_SPURIOUS) |
294 | return NO_IRQ; | |
8767e9ba | 295 | |
967e012e | 296 | irq = irq_radix_revmap_lookup(xics_host, vec); |
b9e5b4e6 | 297 | if (likely(irq != NO_IRQ)) |
0ebfff14 | 298 | return irq; |
b9e5b4e6 | 299 | |
8767e9ba MM |
300 | /* We don't have a linux mapping, so have rtas mask it. */ |
301 | xics_mask_unknown_vec(vec); | |
1da177e4 | 302 | |
8767e9ba MM |
303 | /* We might learn about it later, so EOI it */ |
304 | direct_xirr_info_set(xirr); | |
305 | return NO_IRQ; | |
b9e5b4e6 BH |
306 | } |
307 | ||
35a84c2f | 308 | static unsigned int xics_get_irq_lpar(void) |
1da177e4 | 309 | { |
8767e9ba MM |
310 | unsigned int xirr = lpar_xirr_info_get(); |
311 | unsigned int vec = xics_xirr_vector(xirr); | |
312 | unsigned int irq; | |
313 | ||
314 | if (vec == XICS_IRQ_SPURIOUS) | |
315 | return NO_IRQ; | |
316 | ||
317 | irq = irq_radix_revmap_lookup(xics_host, vec); | |
318 | if (likely(irq != NO_IRQ)) | |
319 | return irq; | |
320 | ||
321 | /* We don't have a linux mapping, so have RTAS mask it. */ | |
322 | xics_mask_unknown_vec(vec); | |
323 | ||
324 | /* We might learn about it later, so EOI it */ | |
325 | lpar_xirr_info_set(xirr); | |
326 | return NO_IRQ; | |
b9e5b4e6 BH |
327 | } |
328 | ||
0641cc91 | 329 | static void xics_eoi_direct(unsigned int virq) |
b9e5b4e6 | 330 | { |
0641cc91 | 331 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; |
b9e5b4e6 | 332 | |
0641cc91 MM |
333 | iosync(); |
334 | direct_xirr_info_set((0xff << 24) | irq); | |
b9e5b4e6 BH |
335 | } |
336 | ||
0641cc91 | 337 | static void xics_eoi_lpar(unsigned int virq) |
b9e5b4e6 | 338 | { |
0641cc91 | 339 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; |
1da177e4 | 340 | |
b9e5b4e6 | 341 | iosync(); |
0641cc91 | 342 | lpar_xirr_info_set((0xff << 24) | irq); |
b9e5b4e6 BH |
343 | } |
344 | ||
d5dedd45 | 345 | static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) |
b9e5b4e6 BH |
346 | { |
347 | unsigned int irq; | |
348 | int status; | |
349 | int xics_status[2]; | |
7ccb4a66 | 350 | int irq_server; |
b9e5b4e6 | 351 | |
0ebfff14 BH |
352 | irq = (unsigned int)irq_map[virq].hwirq; |
353 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | |
d5dedd45 | 354 | return -1; |
b9e5b4e6 BH |
355 | |
356 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
357 | ||
358 | if (status) { | |
2172fe87 MM |
359 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", |
360 | __func__, irq, status); | |
d5dedd45 | 361 | return -1; |
b9e5b4e6 BH |
362 | } |
363 | ||
7ccb4a66 MK |
364 | /* |
365 | * For the moment only implement delivery to all cpus or one cpu. | |
366 | * Get current irq_server for the given irq | |
367 | */ | |
e48395f1 | 368 | irq_server = get_irq_server(virq, 1); |
7ccb4a66 MK |
369 | if (irq_server == -1) { |
370 | char cpulist[128]; | |
371 | cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask); | |
2172fe87 MM |
372 | printk(KERN_WARNING |
373 | "%s: No online cpus in the mask %s for irq %d\n", | |
374 | __func__, cpulist, virq); | |
d5dedd45 | 375 | return -1; |
b9e5b4e6 BH |
376 | } |
377 | ||
378 | status = rtas_call(ibm_set_xive, 3, 1, NULL, | |
7ccb4a66 | 379 | irq, irq_server, xics_status[1]); |
b9e5b4e6 BH |
380 | |
381 | if (status) { | |
2172fe87 MM |
382 | printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n", |
383 | __func__, irq, status); | |
d5dedd45 | 384 | return -1; |
b9e5b4e6 | 385 | } |
d5dedd45 YL |
386 | |
387 | return 0; | |
b9e5b4e6 BH |
388 | } |
389 | ||
390 | static struct irq_chip xics_pic_direct = { | |
b27df672 | 391 | .name = " XICS ", |
b9e5b4e6 BH |
392 | .startup = xics_startup, |
393 | .mask = xics_mask_irq, | |
394 | .unmask = xics_unmask_irq, | |
395 | .eoi = xics_eoi_direct, | |
396 | .set_affinity = xics_set_affinity | |
397 | }; | |
398 | ||
b9e5b4e6 | 399 | static struct irq_chip xics_pic_lpar = { |
b27df672 | 400 | .name = " XICS ", |
b9e5b4e6 BH |
401 | .startup = xics_startup, |
402 | .mask = xics_mask_irq, | |
403 | .unmask = xics_unmask_irq, | |
404 | .eoi = xics_eoi_lpar, | |
405 | .set_affinity = xics_set_affinity | |
406 | }; | |
407 | ||
0641cc91 MM |
408 | |
409 | /* Interface to arch irq controller subsystem layer */ | |
410 | ||
1af9fa89 ME |
411 | /* Points to the irq_chip we're actually using */ |
412 | static struct irq_chip *xics_irq_chip; | |
b9e5b4e6 | 413 | |
0ebfff14 | 414 | static int xics_host_match(struct irq_host *h, struct device_node *node) |
1da177e4 | 415 | { |
0ebfff14 BH |
416 | /* IBM machines have interrupt parents of various funky types for things |
417 | * like vdevices, events, etc... The trick we use here is to match | |
418 | * everything here except the legacy 8259 which is compatible "chrp,iic" | |
419 | */ | |
55b61fec | 420 | return !of_device_is_compatible(node, "chrp,iic"); |
0ebfff14 | 421 | } |
1da177e4 | 422 | |
1af9fa89 ME |
423 | static int xics_host_map(struct irq_host *h, unsigned int virq, |
424 | irq_hw_number_t hw) | |
0ebfff14 | 425 | { |
b69e9e93 | 426 | pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw); |
0ebfff14 | 427 | |
967e012e SD |
428 | /* Insert the interrupt mapping into the radix tree for fast lookup */ |
429 | irq_radix_revmap_insert(xics_host, virq, hw); | |
430 | ||
6cff46f4 | 431 | irq_to_desc(virq)->status |= IRQ_LEVEL; |
1af9fa89 | 432 | set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); |
0ebfff14 BH |
433 | return 0; |
434 | } | |
435 | ||
436 | static int xics_host_xlate(struct irq_host *h, struct device_node *ct, | |
437 | u32 *intspec, unsigned int intsize, | |
438 | irq_hw_number_t *out_hwirq, unsigned int *out_flags) | |
439 | ||
440 | { | |
441 | /* Current xics implementation translates everything | |
442 | * to level. It is not technically right for MSIs but this | |
443 | * is irrelevant at this point. We might get smarter in the future | |
6c80a21c | 444 | */ |
0ebfff14 BH |
445 | *out_hwirq = intspec[0]; |
446 | *out_flags = IRQ_TYPE_LEVEL_LOW; | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
1af9fa89 | 451 | static struct irq_host_ops xics_host_ops = { |
0ebfff14 | 452 | .match = xics_host_match, |
1af9fa89 | 453 | .map = xics_host_map, |
0ebfff14 BH |
454 | .xlate = xics_host_xlate, |
455 | }; | |
456 | ||
457 | static void __init xics_init_host(void) | |
458 | { | |
0ebfff14 | 459 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
1af9fa89 | 460 | xics_irq_chip = &xics_pic_lpar; |
0ebfff14 | 461 | else |
1af9fa89 ME |
462 | xics_irq_chip = &xics_pic_direct; |
463 | ||
464 | xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops, | |
0ebfff14 BH |
465 | XICS_IRQ_SPURIOUS); |
466 | BUG_ON(xics_host == NULL); | |
467 | irq_set_default_host(xics_host); | |
6c80a21c | 468 | } |
1da177e4 | 469 | |
0641cc91 MM |
470 | |
471 | /* Inter-processor interrupt support */ | |
472 | ||
473 | #ifdef CONFIG_SMP | |
474 | /* | |
475 | * XICS only has a single IPI, so encode the messages per CPU | |
476 | */ | |
477 | struct xics_ipi_struct { | |
478 | unsigned long value; | |
479 | } ____cacheline_aligned; | |
480 | ||
481 | static struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned; | |
482 | ||
483 | static inline void smp_xics_do_message(int cpu, int msg) | |
484 | { | |
485 | set_bit(msg, &xics_ipi_message[cpu].value); | |
486 | mb(); | |
487 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
488 | lpar_qirr_info(cpu, IPI_PRIORITY); | |
489 | else | |
490 | direct_qirr_info(cpu, IPI_PRIORITY); | |
491 | } | |
492 | ||
493 | void smp_xics_message_pass(int target, int msg) | |
494 | { | |
495 | unsigned int i; | |
496 | ||
497 | if (target < NR_CPUS) { | |
498 | smp_xics_do_message(target, msg); | |
499 | } else { | |
500 | for_each_online_cpu(i) { | |
501 | if (target == MSG_ALL_BUT_SELF | |
502 | && i == smp_processor_id()) | |
503 | continue; | |
504 | smp_xics_do_message(i, msg); | |
505 | } | |
506 | } | |
507 | } | |
508 | ||
509 | static irqreturn_t xics_ipi_dispatch(int cpu) | |
510 | { | |
511 | WARN_ON(cpu_is_offline(cpu)); | |
512 | ||
199f45c4 | 513 | mb(); /* order mmio clearing qirr */ |
0641cc91 MM |
514 | while (xics_ipi_message[cpu].value) { |
515 | if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, | |
516 | &xics_ipi_message[cpu].value)) { | |
0641cc91 MM |
517 | smp_message_recv(PPC_MSG_CALL_FUNCTION); |
518 | } | |
519 | if (test_and_clear_bit(PPC_MSG_RESCHEDULE, | |
520 | &xics_ipi_message[cpu].value)) { | |
0641cc91 MM |
521 | smp_message_recv(PPC_MSG_RESCHEDULE); |
522 | } | |
523 | if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE, | |
524 | &xics_ipi_message[cpu].value)) { | |
0641cc91 MM |
525 | smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE); |
526 | } | |
527 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) | |
528 | if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, | |
529 | &xics_ipi_message[cpu].value)) { | |
0641cc91 MM |
530 | smp_message_recv(PPC_MSG_DEBUGGER_BREAK); |
531 | } | |
532 | #endif | |
533 | } | |
534 | return IRQ_HANDLED; | |
535 | } | |
536 | ||
537 | static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id) | |
538 | { | |
539 | int cpu = smp_processor_id(); | |
540 | ||
541 | direct_qirr_info(cpu, 0xff); | |
542 | ||
543 | return xics_ipi_dispatch(cpu); | |
544 | } | |
545 | ||
546 | static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id) | |
547 | { | |
548 | int cpu = smp_processor_id(); | |
549 | ||
550 | lpar_qirr_info(cpu, 0xff); | |
551 | ||
552 | return xics_ipi_dispatch(cpu); | |
553 | } | |
554 | ||
555 | static void xics_request_ipi(void) | |
556 | { | |
557 | unsigned int ipi; | |
558 | int rc; | |
559 | ||
560 | ipi = irq_create_mapping(xics_host, XICS_IPI); | |
561 | BUG_ON(ipi == NO_IRQ); | |
562 | ||
563 | /* | |
564 | * IPIs are marked IRQF_DISABLED as they must run with irqs | |
565 | * disabled | |
566 | */ | |
567 | set_irq_handler(ipi, handle_percpu_irq); | |
568 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
d879f384 MM |
569 | rc = request_irq(ipi, xics_ipi_action_lpar, |
570 | IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL); | |
0641cc91 | 571 | else |
d879f384 MM |
572 | rc = request_irq(ipi, xics_ipi_action_direct, |
573 | IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL); | |
0641cc91 MM |
574 | BUG_ON(rc); |
575 | } | |
576 | ||
577 | int __init smp_xics_probe(void) | |
578 | { | |
579 | xics_request_ipi(); | |
580 | ||
581 | return cpus_weight(cpu_possible_map); | |
582 | } | |
583 | ||
584 | #endif /* CONFIG_SMP */ | |
585 | ||
586 | ||
587 | /* Initialization */ | |
588 | ||
589 | static void xics_update_irq_servers(void) | |
590 | { | |
591 | int i, j; | |
592 | struct device_node *np; | |
593 | u32 ilen; | |
1ef8014d | 594 | const u32 *ireg; |
0641cc91 MM |
595 | u32 hcpuid; |
596 | ||
597 | /* Find the server numbers for the boot cpu. */ | |
598 | np = of_get_cpu_node(boot_cpuid, NULL); | |
599 | BUG_ON(!np); | |
600 | ||
601 | ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); | |
602 | if (!ireg) { | |
603 | of_node_put(np); | |
604 | return; | |
605 | } | |
606 | ||
607 | i = ilen / sizeof(int); | |
608 | hcpuid = get_hard_smp_processor_id(boot_cpuid); | |
609 | ||
610 | /* Global interrupt distribution server is specified in the last | |
611 | * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last | |
612 | * entry fom this property for current boot cpu id and use it as | |
613 | * default distribution server | |
614 | */ | |
615 | for (j = 0; j < i; j += 2) { | |
616 | if (ireg[j] == hcpuid) { | |
617 | default_server = hcpuid; | |
618 | default_distrib_server = ireg[j+1]; | |
0641cc91 MM |
619 | } |
620 | } | |
621 | ||
622 | of_node_put(np); | |
623 | } | |
624 | ||
0ebfff14 BH |
625 | static void __init xics_map_one_cpu(int hw_id, unsigned long addr, |
626 | unsigned long size) | |
1da177e4 LT |
627 | { |
628 | int i; | |
1da177e4 | 629 | |
0ebfff14 BH |
630 | /* This may look gross but it's good enough for now, we don't quite |
631 | * have a hard -> linux processor id matching. | |
632 | */ | |
633 | for_each_possible_cpu(i) { | |
634 | if (!cpu_present(i)) | |
635 | continue; | |
636 | if (hw_id == get_hard_smp_processor_id(i)) { | |
637 | xics_per_cpu[i] = ioremap(addr, size); | |
638 | return; | |
639 | } | |
640 | } | |
0ebfff14 | 641 | } |
1da177e4 | 642 | |
0ebfff14 BH |
643 | static void __init xics_init_one_node(struct device_node *np, |
644 | unsigned int *indx) | |
645 | { | |
646 | unsigned int ilen; | |
954a46e2 | 647 | const u32 *ireg; |
1da177e4 | 648 | |
0ebfff14 BH |
649 | /* This code does the theorically broken assumption that the interrupt |
650 | * server numbers are the same as the hard CPU numbers. | |
651 | * This happens to be the case so far but we are playing with fire... | |
652 | * should be fixed one of these days. -BenH. | |
653 | */ | |
e2eb6392 | 654 | ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL); |
1da177e4 | 655 | |
0ebfff14 BH |
656 | /* Do that ever happen ? we'll know soon enough... but even good'old |
657 | * f80 does have that property .. | |
658 | */ | |
659 | WARN_ON(ireg == NULL); | |
1da177e4 LT |
660 | if (ireg) { |
661 | /* | |
662 | * set node starting index for this node | |
663 | */ | |
0ebfff14 | 664 | *indx = *ireg; |
1da177e4 | 665 | } |
e2eb6392 | 666 | ireg = of_get_property(np, "reg", &ilen); |
1da177e4 LT |
667 | if (!ireg) |
668 | panic("xics_init_IRQ: can't find interrupt reg property"); | |
007e8f51 | 669 | |
0ebfff14 BH |
670 | while (ilen >= (4 * sizeof(u32))) { |
671 | unsigned long addr, size; | |
672 | ||
673 | /* XXX Use proper OF parsing code here !!! */ | |
674 | addr = (unsigned long)*ireg++ << 32; | |
675 | ilen -= sizeof(u32); | |
676 | addr |= *ireg++; | |
677 | ilen -= sizeof(u32); | |
678 | size = (unsigned long)*ireg++ << 32; | |
679 | ilen -= sizeof(u32); | |
680 | size |= *ireg++; | |
681 | ilen -= sizeof(u32); | |
682 | xics_map_one_cpu(*indx, addr, size); | |
683 | (*indx)++; | |
684 | } | |
685 | } | |
686 | ||
0ebfff14 BH |
687 | void __init xics_init_IRQ(void) |
688 | { | |
0ebfff14 | 689 | struct device_node *np; |
de0723dc | 690 | u32 indx = 0; |
0ebfff14 | 691 | int found = 0; |
1ef8014d | 692 | const u32 *isize; |
0ebfff14 BH |
693 | |
694 | ppc64_boot_msg(0x20, "XICS Init"); | |
695 | ||
696 | ibm_get_xive = rtas_token("ibm,get-xive"); | |
697 | ibm_set_xive = rtas_token("ibm,set-xive"); | |
698 | ibm_int_on = rtas_token("ibm,int-on"); | |
699 | ibm_int_off = rtas_token("ibm,int-off"); | |
700 | ||
701 | for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") { | |
702 | found = 1; | |
a244a957 MM |
703 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
704 | of_node_put(np); | |
0ebfff14 | 705 | break; |
a244a957 | 706 | } |
0ebfff14 BH |
707 | xics_init_one_node(np, &indx); |
708 | } | |
709 | if (found == 0) | |
710 | return; | |
711 | ||
1ef8014d SD |
712 | /* get the bit size of server numbers */ |
713 | found = 0; | |
714 | ||
715 | for_each_compatible_node(np, NULL, "ibm,ppc-xics") { | |
716 | isize = of_get_property(np, "ibm,interrupt-server#-size", NULL); | |
717 | ||
718 | if (!isize) | |
719 | continue; | |
720 | ||
721 | if (!found) { | |
722 | interrupt_server_size = *isize; | |
723 | found = 1; | |
724 | } else if (*isize != interrupt_server_size) { | |
725 | printk(KERN_WARNING "XICS: " | |
726 | "mismatched ibm,interrupt-server#-size\n"); | |
727 | interrupt_server_size = max(*isize, | |
728 | interrupt_server_size); | |
729 | } | |
730 | } | |
731 | ||
de0723dc | 732 | xics_update_irq_servers(); |
302905a3 | 733 | xics_init_host(); |
1da177e4 | 734 | |
0ebfff14 BH |
735 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
736 | ppc_md.get_irq = xics_get_irq_lpar; | |
737 | else | |
b9e5b4e6 | 738 | ppc_md.get_irq = xics_get_irq_direct; |
1da177e4 | 739 | |
6c80a21c | 740 | xics_setup_cpu(); |
1da177e4 | 741 | |
0ebfff14 | 742 | ppc64_boot_msg(0x21, "XICS Done"); |
1da177e4 | 743 | } |
b9e5b4e6 | 744 | |
0641cc91 | 745 | /* Cpu startup, shutdown, and hotplug */ |
1da177e4 | 746 | |
0641cc91 | 747 | static void xics_set_cpu_priority(unsigned char cppr) |
1da177e4 | 748 | { |
b9e5b4e6 | 749 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
0641cc91 | 750 | lpar_cppr_info(cppr); |
b9e5b4e6 | 751 | else |
0641cc91 MM |
752 | direct_cppr_info(cppr); |
753 | iosync(); | |
1da177e4 | 754 | } |
d13f7208 | 755 | |
b4963255 MM |
756 | /* Have the calling processor join or leave the specified global queue */ |
757 | static void xics_set_cpu_giq(unsigned int gserver, unsigned int join) | |
758 | { | |
edc72ac4 NL |
759 | int index; |
760 | int status; | |
761 | ||
762 | if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL)) | |
763 | return; | |
764 | ||
765 | index = (1UL << interrupt_server_size) - 1 - gserver; | |
766 | ||
767 | status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join); | |
768 | ||
769 | WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", | |
770 | GLOBAL_INTERRUPT_QUEUE, index, join, status); | |
b4963255 | 771 | } |
0641cc91 MM |
772 | |
773 | void xics_setup_cpu(void) | |
d13f7208 | 774 | { |
0641cc91 | 775 | xics_set_cpu_priority(0xff); |
d13f7208 | 776 | |
b4963255 | 777 | xics_set_cpu_giq(default_distrib_server, 1); |
d13f7208 MM |
778 | } |
779 | ||
f10095c3 | 780 | void xics_teardown_cpu(void) |
fce0d574 S |
781 | { |
782 | int cpu = smp_processor_id(); | |
fce0d574 | 783 | |
d7cf0edb | 784 | xics_set_cpu_priority(0); |
81bbbe92 | 785 | |
b4963255 | 786 | /* Clear any pending IPI request */ |
6e99e458 BH |
787 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
788 | lpar_qirr_info(cpu, 0xff); | |
789 | else | |
790 | direct_qirr_info(cpu, 0xff); | |
c3e8506c NF |
791 | } |
792 | ||
793 | void xics_kexec_teardown_cpu(int secondary) | |
794 | { | |
c3e8506c | 795 | xics_teardown_cpu(); |
6e99e458 | 796 | |
81bbbe92 | 797 | /* |
1a57c926 MM |
798 | * we take the ipi irq but and never return so we |
799 | * need to EOI the IPI, but want to leave our priority 0 | |
81bbbe92 | 800 | * |
1a57c926 | 801 | * should we check all the other interrupts too? |
81bbbe92 HM |
802 | * should we be flagging idle loop instead? |
803 | * or creating some task to be scheduled? | |
804 | */ | |
0ebfff14 | 805 | |
1a57c926 MM |
806 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
807 | lpar_xirr_info_set((0x00 << 24) | XICS_IPI); | |
808 | else | |
809 | direct_xirr_info_set((0x00 << 24) | XICS_IPI); | |
81bbbe92 | 810 | |
fce0d574 | 811 | /* |
6d22d85a PM |
812 | * Some machines need to have at least one cpu in the GIQ, |
813 | * so leave the master cpu in the group. | |
fce0d574 | 814 | */ |
81bbbe92 | 815 | if (secondary) |
b4963255 | 816 | xics_set_cpu_giq(default_distrib_server, 0); |
fce0d574 S |
817 | } |
818 | ||
1da177e4 LT |
819 | #ifdef CONFIG_HOTPLUG_CPU |
820 | ||
821 | /* Interrupts are disabled. */ | |
822 | void xics_migrate_irqs_away(void) | |
823 | { | |
d7cf0edb MM |
824 | int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); |
825 | unsigned int irq, virq; | |
1da177e4 | 826 | |
302905a3 MM |
827 | /* If we used to be the default server, move to the new "boot_cpuid" */ |
828 | if (hw_cpu == default_server) | |
829 | xics_update_irq_servers(); | |
830 | ||
1da177e4 | 831 | /* Reject any interrupt that was queued to us... */ |
d7cf0edb | 832 | xics_set_cpu_priority(0); |
1da177e4 | 833 | |
b4963255 MM |
834 | /* Remove ourselves from the global interrupt queue */ |
835 | xics_set_cpu_giq(default_distrib_server, 0); | |
1da177e4 LT |
836 | |
837 | /* Allow IPIs again... */ | |
d7cf0edb | 838 | xics_set_cpu_priority(DEFAULT_PRIORITY); |
1da177e4 LT |
839 | |
840 | for_each_irq(virq) { | |
b9e5b4e6 | 841 | struct irq_desc *desc; |
1da177e4 | 842 | int xics_status[2]; |
b4963255 | 843 | int status; |
1da177e4 LT |
844 | unsigned long flags; |
845 | ||
846 | /* We cant set affinity on ISA interrupts */ | |
0ebfff14 | 847 | if (virq < NUM_ISA_INTERRUPTS) |
1da177e4 | 848 | continue; |
0ebfff14 BH |
849 | if (irq_map[virq].host != xics_host) |
850 | continue; | |
851 | irq = (unsigned int)irq_map[virq].hwirq; | |
1da177e4 | 852 | /* We need to get IPIs still. */ |
0ebfff14 | 853 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
1da177e4 | 854 | continue; |
6cff46f4 | 855 | desc = irq_to_desc(virq); |
1da177e4 LT |
856 | |
857 | /* We only need to migrate enabled IRQS */ | |
d1bef4ed | 858 | if (desc == NULL || desc->chip == NULL |
1da177e4 | 859 | || desc->action == NULL |
d1bef4ed | 860 | || desc->chip->set_affinity == NULL) |
1da177e4 LT |
861 | continue; |
862 | ||
863 | spin_lock_irqsave(&desc->lock, flags); | |
864 | ||
865 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | |
866 | if (status) { | |
2172fe87 MM |
867 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", |
868 | __func__, irq, status); | |
1da177e4 LT |
869 | goto unlock; |
870 | } | |
871 | ||
872 | /* | |
873 | * We only support delivery to all cpus or to one cpu. | |
874 | * The irq has to be migrated only in the single cpu | |
875 | * case. | |
876 | */ | |
d7cf0edb | 877 | if (xics_status[0] != hw_cpu) |
1da177e4 LT |
878 | goto unlock; |
879 | ||
26370322 | 880 | printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n", |
1da177e4 LT |
881 | virq, cpu); |
882 | ||
883 | /* Reset affinity to all cpus */ | |
6cff46f4 | 884 | cpumask_setall(irq_to_desc(virq)->affinity); |
0de26520 | 885 | desc->chip->set_affinity(virq, cpu_all_mask); |
1da177e4 LT |
886 | unlock: |
887 | spin_unlock_irqrestore(&desc->lock, flags); | |
888 | } | |
889 | } | |
890 | #endif |