[linux-block.git] / arch / powerpc / platforms / pseries / pci.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
 *
 * pSeries specific routines for PCI.
 */

#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>

#include <asm/eeh.h>
#include <asm/pci-bridge.h>
#include <asm/prom.h>
#include <asm/ppc-pci.h>
#include <asm/pci.h>
#include "pseries.h"

#if 0
void pcibios_name_device(struct pci_dev *dev)
{
	struct device_node *dn;

	/*
	 * Add IBM loc code (slot) as a prefix to the device names for service
	 */
	dn = pci_device_to_OF_node(dev);
	if (dn) {
		const char *loc_code = of_get_property(dn, "ibm,loc-code",
				NULL);
		if (loc_code) {
			int loc_len = strlen(loc_code);
			if (loc_len < sizeof(dev->dev.name)) {
				memmove(dev->dev.name+loc_len+1, dev->dev.name,
					sizeof(dev->dev.name)-loc_len-1);
				memcpy(dev->dev.name, loc_code, loc_len);
				dev->dev.name[loc_len] = ' ';
				dev->dev.name[sizeof(dev->dev.name)-1] = '\0';
			}
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_name_device);
#endif

#ifdef CONFIG_PCI_IOV
#define MAX_VFS_FOR_MAP_PE 256
struct pe_map_bar_entry {
	__be64     bar;       /* Input:  Virtual Function BAR */
	__be16     rid;       /* Input:  Virtual Function Router ID */
	__be16     pe_num;    /* Output: Virtual Function PE Number */
	__be32     reserved;  /* Reserved Space */
};

int pseries_send_map_pe(struct pci_dev *pdev,
			u16 num_vfs,
			struct pe_map_bar_entry *vf_pe_array)
{
	struct pci_dn *pdn;
	int rc;
	unsigned long buid, addr;
	int ibm_map_pes = rtas_token("ibm,open-sriov-map-pe-number");

	if (ibm_map_pes == RTAS_UNKNOWN_SERVICE)
		return -EINVAL;

	pdn = pci_get_pdn(pdev);
	addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
	buid = pdn->phb->buid;
	spin_lock(&rtas_data_buf_lock);
	memcpy(rtas_data_buf, vf_pe_array,
	       RTAS_DATA_BUF_SIZE);
	rc = rtas_call(ibm_map_pes, 5, 1, NULL, addr,
		       BUID_HI(buid), BUID_LO(buid),
		       rtas_data_buf,
		       num_vfs * sizeof(struct pe_map_bar_entry));
	memcpy(vf_pe_array, rtas_data_buf, RTAS_DATA_BUF_SIZE);
	spin_unlock(&rtas_data_buf_lock);

	if (rc)
		dev_err(&pdev->dev,
			"%s: Failed to associate pes PE#%lx, rc=%x\n",
			__func__,  addr, rc);

	return rc;
}

void pseries_set_pe_num(struct pci_dev *pdev, u16 vf_index, __be16 pe_num)
{
	struct pci_dn *pdn;

	pdn = pci_get_pdn(pdev);
	pdn->pe_num_map[vf_index] = be16_to_cpu(pe_num);
	dev_dbg(&pdev->dev, "VF %04x:%02x:%02x.%x associated with PE#%x\n",
		pci_domain_nr(pdev->bus),
		pdev->bus->number,
		PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
		PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)),
		pdn->pe_num_map[vf_index]);
}

int pseries_associate_pes(struct pci_dev *pdev, u16 num_vfs)
{
	struct pci_dn *pdn;
	int i, rc, vf_index;
	struct pe_map_bar_entry *vf_pe_array;
	struct resource *res;
	u64 size;

	vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
	if (!vf_pe_array)
		return -ENOMEM;

	pdn = pci_get_pdn(pdev);
	/* create firmware structure to associate pes */
	for (vf_index = 0; vf_index < num_vfs; vf_index++) {
		pdn->pe_num_map[vf_index] = IODA_INVALID_PE;
		for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
			res = &pdev->resource[i + PCI_IOV_RESOURCES];
			if (!res->parent)
				continue;
			size = pcibios_iov_resource_alignment(pdev, i +
					PCI_IOV_RESOURCES);
			vf_pe_array[vf_index].bar =
				cpu_to_be64(res->start + size * vf_index);
			vf_pe_array[vf_index].rid =
				cpu_to_be16((pci_iov_virtfn_bus(pdev, vf_index)
					    << 8) | pci_iov_virtfn_devfn(pdev,
					    vf_index));
			vf_pe_array[vf_index].pe_num =
				cpu_to_be16(IODA_INVALID_PE);
		}
	}

	rc = pseries_send_map_pe(pdev, num_vfs, vf_pe_array);
	/* Only zero is success */
	if (!rc)
		for (vf_index = 0; vf_index < num_vfs; vf_index++)
			pseries_set_pe_num(pdev, vf_index,
					   vf_pe_array[vf_index].pe_num);

	kfree(vf_pe_array);
	return rc;
}

int pseries_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
{
	struct pci_dn         *pdn;
	int                    rc;
	const int *max_vfs;
	int max_config_vfs;
	struct device_node *dn = pci_device_to_OF_node(pdev);

	max_vfs = of_get_property(dn, "ibm,number-of-configurable-vfs", NULL);

	if (!max_vfs)
		return -EINVAL;

	/* First integer stores max config */
	max_config_vfs = of_read_number(&max_vfs[0], 1);
	if (max_config_vfs < num_vfs && num_vfs > MAX_VFS_FOR_MAP_PE) {
		dev_err(&pdev->dev,
			"Num VFs %x > %x Configurable VFs\n",
			num_vfs, (num_vfs > MAX_VFS_FOR_MAP_PE) ?
			MAX_VFS_FOR_MAP_PE : max_config_vfs);
		return -EINVAL;
	}

	pdn = pci_get_pdn(pdev);
	pdn->pe_num_map = kmalloc_array(num_vfs,
					sizeof(*pdn->pe_num_map),
					GFP_KERNEL);
	if (!pdn->pe_num_map)
		return -ENOMEM;

	rc = pseries_associate_pes(pdev, num_vfs);

	/* Anything other than zero is failure */
	if (rc) {
		dev_err(&pdev->dev, "Failure to enable sriov: %x\n", rc);
		kfree(pdn->pe_num_map);
	} else {
		pci_vf_drivers_autoprobe(pdev, false);
	}

	return rc;
}

int pseries_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
{
	/* Allocate PCI data */
	add_dev_pci_data(pdev);
	return pseries_pci_sriov_enable(pdev, num_vfs);
}

int pseries_pcibios_sriov_disable(struct pci_dev *pdev)
{
	struct pci_dn         *pdn;

	pdn = pci_get_pdn(pdev);
	/* Releasing pe_num_map */
	kfree(pdn->pe_num_map);
	/* Release PCI data */
	remove_dev_pci_data(pdev);
	pci_vf_drivers_autoprobe(pdev, true);
	return 0;
}
#endif

static void __init pSeries_request_regions(void)
{
	if (!isa_io_base)
		return;

	request_region(0x20,0x20,"pic1");
	request_region(0xa0,0x20,"pic2");
	request_region(0x00,0x20,"dma1");
	request_region(0x40,0x20,"timer");
	request_region(0x80,0x10,"dma page reg");
	request_region(0xc0,0x20,"dma2");
}

void __init pSeries_final_fixup(void)
{
	struct pci_controller *hose;

	pSeries_request_regions();

	eeh_probe_devices();
	eeh_addr_cache_build();

#ifdef CONFIG_PCI_IOV
	ppc_md.pcibios_sriov_enable = pseries_pcibios_sriov_enable;
	ppc_md.pcibios_sriov_disable = pseries_pcibios_sriov_disable;
#endif
	list_for_each_entry(hose, &hose_list, list_node) {
		struct device_node *dn = hose->dn, *nvdn;

		while (1) {
			dn = of_find_all_nodes(dn);
			if (!dn)
				break;
			nvdn = of_parse_phandle(dn, "ibm,nvlink", 0);
			if (!nvdn)
				continue;
			if (!of_device_is_compatible(nvdn, "ibm,npu-link"))
				continue;
			if (!of_device_is_compatible(nvdn->parent,
						"ibm,power9-npu"))
				continue;
#ifdef CONFIG_PPC_POWERNV
			WARN_ON_ONCE(pnv_npu2_init(hose));
#endif
			break;
		}
	}
}

/*
 * Assume the winbond 82c105 is the IDE controller on a
 * p610/p615/p630. We should probably be more careful in case
 * someone tries to plug in a similar adapter.
 */
static void fixup_winbond_82c105(struct pci_dev* dev)
{
	int i;
	unsigned int reg;

	if (!machine_is(pseries))
		return;

	printk("Using INTC for W82c105 IDE controller.\n");
	pci_read_config_dword(dev, 0x40, &reg);
	/* Enable LEGIRQ to use INTC instead of ISA interrupts */
	pci_write_config_dword(dev, 0x40, reg | (1<<11));

	for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
		/* zap the 2nd function of the winbond chip */
		if (dev->resource[i].flags & IORESOURCE_IO
		    && dev->bus->number == 0 && dev->devfn == 0x81)
			dev->resource[i].flags &= ~IORESOURCE_IO;
		if (dev->resource[i].start == 0 && dev->resource[i].end) {
			dev->resource[i].flags = 0;
			dev->resource[i].end = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
			 fixup_winbond_82c105);

int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
{
	struct device_node *dn, *pdn;
	struct pci_bus *bus;
	u32 pcie_link_speed_stats[2];
	int rc;

	bus = bridge->bus;

	/* Rely on the pcibios_free_controller_deferred() callback. */
	pci_set_host_bridge_release(bridge, pcibios_free_controller_deferred,
					(void *) pci_bus_to_host(bus));

	dn = pcibios_get_phb_of_node(bus);
	if (!dn)
		return 0;

	for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
		rc = of_property_read_u32_array(pdn,
				"ibm,pcie-link-speed-stats",
				&pcie_link_speed_stats[0], 2);
		if (!rc)
			break;
	}

	of_node_put(pdn);

	if (rc) {
		pr_debug("no ibm,pcie-link-speed-stats property\n");
		return 0;
	}

	switch (pcie_link_speed_stats[0]) {
	case 0x01:
		bus->max_bus_speed = PCIE_SPEED_2_5GT;
		break;
	case 0x02:
		bus->max_bus_speed = PCIE_SPEED_5_0GT;
		break;
	case 0x04:
		bus->max_bus_speed = PCIE_SPEED_8_0GT;
		break;
	default:
		bus->max_bus_speed = PCI_SPEED_UNKNOWN;
		break;
	}

	switch (pcie_link_speed_stats[1]) {
	case 0x01:
		bus->cur_bus_speed = PCIE_SPEED_2_5GT;
		break;
	case 0x02:
		bus->cur_bus_speed = PCIE_SPEED_5_0GT;
		break;
	case 0x04:
		bus->cur_bus_speed = PCIE_SPEED_8_0GT;
		break;
	default:
		bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
		break;
	}

	return 0;
}
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4	2	/*
1da177e4 LT	3	* Copyright (C) 2001 Dave Engebretsen, IBM Corporation
	4	* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
	5	*
	6	* pSeries specific routines for PCI.
1da177e4 LT	7	*/
1da177e4 LT	8
c5a3c2e5 AB	9	#include <linux/init.h>
c5a3c2e5 AB	10	#include <linux/ioport.h>
1da177e4	11	#include <linux/kernel.h>
1da177e4 LT	12	#include <linux/pci.h>
1da177e4 LT	13	#include <linux/string.h>
1da177e4	14
c3b9d9ab	15	#include <asm/eeh.h>
1da177e4	16	#include <asm/pci-bridge.h>
c5a3c2e5	17	#include <asm/prom.h>
d387899f	18	#include <asm/ppc-pci.h>
3be2df00	19	#include <asm/pci.h>
1217d34b	20	#include "pseries.h"
1da177e4	21
1da177e4 LT	22	#if 0
	23	void pcibios_name_device(struct pci_dev *dev)
	24	{
	25	struct device_node *dn;
	26
	27	/*
	28	* Add IBM loc code (slot) as a prefix to the device names for service
	29	*/
	30	dn = pci_device_to_OF_node(dev);
	31	if (dn) {
724c6abf TB	32	const char *loc_code = of_get_property(dn, "ibm,loc-code",
724c6abf TB	33	NULL);
1da177e4 LT	34	if (loc_code) {
	35	int loc_len = strlen(loc_code);
	36	if (loc_len < sizeof(dev->dev.name)) {
	37	memmove(dev->dev.name+loc_len+1, dev->dev.name,
	38	sizeof(dev->dev.name)-loc_len-1);
	39	memcpy(dev->dev.name, loc_code, loc_len);
	40	dev->dev.name[loc_len] = ' ';
	41	dev->dev.name[sizeof(dev->dev.name)-1] = '\0';
	42	}
	43	}
	44	}
dae7253f	45	}
1da177e4 LT	46	DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_name_device);
	47	#endif
	48
dae7253f	49	#ifdef CONFIG_PCI_IOV
9a7f6b43 BL	50	#define MAX_VFS_FOR_MAP_PE 256
	51	struct pe_map_bar_entry {
	52	__be64 bar; /* Input: Virtual Function BAR */
	53	__be16 rid; /* Input: Virtual Function Router ID */
	54	__be16 pe_num; /* Output: Virtual Function PE Number */
	55	__be32 reserved; /* Reserved Space */
	56	};
	57
	58	int pseries_send_map_pe(struct pci_dev *pdev,
	59	u16 num_vfs,
	60	struct pe_map_bar_entry *vf_pe_array)
	61	{
	62	struct pci_dn *pdn;
	63	int rc;
	64	unsigned long buid, addr;
	65	int ibm_map_pes = rtas_token("ibm,open-sriov-map-pe-number");
	66
	67	if (ibm_map_pes == RTAS_UNKNOWN_SERVICE)
	68	return -EINVAL;
	69
	70	pdn = pci_get_pdn(pdev);
	71	addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
	72	buid = pdn->phb->buid;
	73	spin_lock(&rtas_data_buf_lock);
	74	memcpy(rtas_data_buf, vf_pe_array,
	75	RTAS_DATA_BUF_SIZE);
	76	rc = rtas_call(ibm_map_pes, 5, 1, NULL, addr,
	77	BUID_HI(buid), BUID_LO(buid),
	78	rtas_data_buf,
	79	num_vfs * sizeof(struct pe_map_bar_entry));
	80	memcpy(vf_pe_array, rtas_data_buf, RTAS_DATA_BUF_SIZE);
	81	spin_unlock(&rtas_data_buf_lock);
	82
	83	if (rc)
	84	dev_err(&pdev->dev,
	85	"%s: Failed to associate pes PE#%lx, rc=%x\n",
	86	__func__, addr, rc);
	87
	88	return rc;
	89	}
	90
	91	void pseries_set_pe_num(struct pci_dev *pdev, u16 vf_index, __be16 pe_num)
	92	{
	93	struct pci_dn *pdn;
	94
	95	pdn = pci_get_pdn(pdev);
	96	pdn->pe_num_map[vf_index] = be16_to_cpu(pe_num);
	97	dev_dbg(&pdev->dev, "VF %04x:%02x:%02x.%x associated with PE#%x\n",
	98	pci_domain_nr(pdev->bus),
	99	pdev->bus->number,
	100	PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
	101	PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)),
	102	pdn->pe_num_map[vf_index]);
	103	}
	104
	105	int pseries_associate_pes(struct pci_dev *pdev, u16 num_vfs)
	106	{
	107	struct pci_dn *pdn;
	108	int i, rc, vf_index;
	109	struct pe_map_bar_entry *vf_pe_array;
	110	struct resource *res;
	111	u64 size;
	112
	113	vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
114	if (!vf_pe_array)
115	return -ENOMEM;
116
117	pdn = pci_get_pdn(pdev);
118	/* create firmware structure to associate pes */
119	for (vf_index = 0; vf_index < num_vfs; vf_index++) {
120	pdn->pe_num_map[vf_index] = IODA_INVALID_PE;
121	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
122	res = &pdev->resource[i + PCI_IOV_RESOURCES];
123	if (!res->parent)
124	continue;
125	size = pcibios_iov_resource_alignment(pdev, i +
126	PCI_IOV_RESOURCES);
127	vf_pe_array[vf_index].bar =
128	cpu_to_be64(res->start + size * vf_index);
129	vf_pe_array[vf_index].rid =
130	cpu_to_be16((pci_iov_virtfn_bus(pdev, vf_index)
131	<< 8) \| pci_iov_virtfn_devfn(pdev,
132	vf_index));
133	vf_pe_array[vf_index].pe_num =
134	cpu_to_be16(IODA_INVALID_PE);
135	}
136	}
137
138	rc = pseries_send_map_pe(pdev, num_vfs, vf_pe_array);
139	/* Only zero is success */
140	if (!rc)
141	for (vf_index = 0; vf_index < num_vfs; vf_index++)
142	pseries_set_pe_num(pdev, vf_index,
143	vf_pe_array[vf_index].pe_num);
144
145	kfree(vf_pe_array);
146	return rc;
147	}
148
149	int pseries_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
150	{
151	struct pci_dn *pdn;
152	int rc;
153	const int *max_vfs;
154	int max_config_vfs;
155	struct device_node *dn = pci_device_to_OF_node(pdev);
156
157	max_vfs = of_get_property(dn, "ibm,number-of-configurable-vfs", NULL);
158
159	if (!max_vfs)
160	return -EINVAL;
161
162	/* First integer stores max config */
163	max_config_vfs = of_read_number(&max_vfs[0], 1);
164	if (max_config_vfs < num_vfs && num_vfs > MAX_VFS_FOR_MAP_PE) {
165	dev_err(&pdev->dev,
166	"Num VFs %x > %x Configurable VFs\n",
167	num_vfs, (num_vfs > MAX_VFS_FOR_MAP_PE) ?
168	MAX_VFS_FOR_MAP_PE : max_config_vfs);
169	return -EINVAL;
170	}
171
172	pdn = pci_get_pdn(pdev);
173	pdn->pe_num_map = kmalloc_array(num_vfs,
174	sizeof(*pdn->pe_num_map),
175	GFP_KERNEL);
176	if (!pdn->pe_num_map)
177	return -ENOMEM;
178
179	rc = pseries_associate_pes(pdev, num_vfs);
180
181	/* Anything other than zero is failure */
182	if (rc) {
183	dev_err(&pdev->dev, "Failure to enable sriov: %x\n", rc);
184	kfree(pdn->pe_num_map);
185	} else {
186	pci_vf_drivers_autoprobe(pdev, false);
187	}
188
189	return rc;
190	}
191
dae7253f BL	192	int pseries_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
	193	{
	194	/* Allocate PCI data */
	195	add_dev_pci_data(pdev);
9a7f6b43	196	return pseries_pci_sriov_enable(pdev, num_vfs);
dae7253f BL	197	}
	198
	199	int pseries_pcibios_sriov_disable(struct pci_dev *pdev)
	200	{
9a7f6b43 BL	201	struct pci_dn *pdn;
	202
	203	pdn = pci_get_pdn(pdev);
	204	/* Releasing pe_num_map */
	205	kfree(pdn->pe_num_map);
dae7253f BL	206	/* Release PCI data */
dae7253f BL	207	remove_dev_pci_data(pdev);
608c0d88	208	pci_vf_drivers_autoprobe(pdev, true);
dae7253f BL	209	return 0;
	210	}
	211	#endif
	212
1da177e4 LT	213	static void __init pSeries_request_regions(void)
	214	{
	215	if (!isa_io_base)
	216	return;
	217
	218	request_region(0x20,0x20,"pic1");
	219	request_region(0xa0,0x20,"pic2");
	220	request_region(0x00,0x20,"dma1");
	221	request_region(0x40,0x20,"timer");
	222	request_region(0x80,0x10,"dma page reg");
	223	request_region(0xc0,0x20,"dma2");
	224	}
	225
	226	void __init pSeries_final_fixup(void)
	227	{
3be2df00 AK	228	struct pci_controller *hose;
3be2df00 AK	229
1da177e4 LT	230	pSeries_request_regions();
1da177e4 LT	231
bffc0176	232	eeh_probe_devices();
3ab96a02	233	eeh_addr_cache_build();
dae7253f BL	234
	235	#ifdef CONFIG_PCI_IOV
	236	ppc_md.pcibios_sriov_enable = pseries_pcibios_sriov_enable;
	237	ppc_md.pcibios_sriov_disable = pseries_pcibios_sriov_disable;
	238	#endif
3be2df00 AK	239	list_for_each_entry(hose, &hose_list, list_node) {
	240	struct device_node dn = hose->dn, nvdn;
	241
	242	while (1) {
	243	dn = of_find_all_nodes(dn);
	244	if (!dn)
	245	break;
	246	nvdn = of_parse_phandle(dn, "ibm,nvlink", 0);
	247	if (!nvdn)
	248	continue;
	249	if (!of_device_is_compatible(nvdn, "ibm,npu-link"))
	250	continue;
	251	if (!of_device_is_compatible(nvdn->parent,
	252	"ibm,power9-npu"))
	253	continue;
da727097	254	#ifdef CONFIG_PPC_POWERNV
3be2df00	255	WARN_ON_ONCE(pnv_npu2_init(hose));
da727097	256	#endif
3be2df00 AK	257	break;
	258	}
	259	}
1da177e4 LT	260	}
	261
	262	/*
	263	* Assume the winbond 82c105 is the IDE controller on a
0bcace3b	264	* p610/p615/p630. We should probably be more careful in case
1da177e4 LT	265	* someone tries to plug in a similar adapter.
	266	*/
	267	static void fixup_winbond_82c105(struct pci_dev* dev)
	268	{
	269	int i;
	270	unsigned int reg;
	271
e8222502	272	if (!machine_is(pseries))
1da177e4 LT	273	return;
	274
	275	printk("Using INTC for W82c105 IDE controller.\n");
	276	pci_read_config_dword(dev, 0x40, &reg);
	277	/* Enable LEGIRQ to use INTC instead of ISA interrupts */
	278	pci_write_config_dword(dev, 0x40, reg \| (1<<11));
	279
	280	for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
	281	/* zap the 2nd function of the winbond chip */
	282	if (dev->resource[i].flags & IORESOURCE_IO
	283	&& dev->bus->number == 0 && dev->devfn == 0x81)
	284	dev->resource[i].flags &= ~IORESOURCE_IO;
2d99c41f OH	285	if (dev->resource[i].start == 0 && dev->resource[i].end) {
	286	dev->resource[i].flags = 0;
	287	dev->resource[i].end = 0;
	288	}
1da177e4 LT	289	}
	290	}
	291	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
	292	fixup_winbond_82c105);
d82fb31a KSS	293
	294	int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
	295	{
	296	struct device_node dn, pdn;
	297	struct pci_bus *bus;
b020cc6c KSS	298	u32 pcie_link_speed_stats[2];
b020cc6c KSS	299	int rc;
d82fb31a KSS	300
	301	bus = bridge->bus;
	302
2dd9c11b MFO	303	/* Rely on the pcibios_free_controller_deferred() callback. */
	304	pci_set_host_bridge_release(bridge, pcibios_free_controller_deferred,
	305	(void *) pci_bus_to_host(bus));
	306
d82fb31a KSS	307	dn = pcibios_get_phb_of_node(bus);
	308	if (!dn)
	309	return 0;
	310
	311	for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
b020cc6c KSS	312	rc = of_property_read_u32_array(pdn,
	313	"ibm,pcie-link-speed-stats",
	314	&pcie_link_speed_stats[0], 2);
	315	if (!rc)
d82fb31a KSS	316	break;
	317	}
	318
	319	of_node_put(pdn);
	320
b020cc6c	321	if (rc) {
7aa189c8	322	pr_debug("no ibm,pcie-link-speed-stats property\n");
d82fb31a KSS	323	return 0;
	324	}
	325
b020cc6c	326	switch (pcie_link_speed_stats[0]) {
d82fb31a KSS	327	case 0x01:
	328	bus->max_bus_speed = PCIE_SPEED_2_5GT;
	329	break;
	330	case 0x02:
	331	bus->max_bus_speed = PCIE_SPEED_5_0GT;
	332	break;
49d9684a KSS	333	case 0x04:
	334	bus->max_bus_speed = PCIE_SPEED_8_0GT;
	335	break;
d82fb31a KSS	336	default:
	337	bus->max_bus_speed = PCI_SPEED_UNKNOWN;
	338	break;
	339	}
	340
b020cc6c	341	switch (pcie_link_speed_stats[1]) {
d82fb31a KSS	342	case 0x01:
	343	bus->cur_bus_speed = PCIE_SPEED_2_5GT;
	344	break;
	345	case 0x02:
	346	bus->cur_bus_speed = PCIE_SPEED_5_0GT;
	347	break;
49d9684a KSS	348	case 0x04:
	349	bus->cur_bus_speed = PCIE_SPEED_8_0GT;
	350	break;
d82fb31a KSS	351	default:
	352	bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
	353	break;
	354	}
	355
	356	return 0;
	357	}