Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
3 | * | |
bc97ce95 | 4 | * Rewrite, cleanup: |
1da177e4 | 5 | * |
91f14480 | 6 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
bc97ce95 | 7 | * Copyright (C) 2006 Olof Johansson <olof@lixom.net> |
1da177e4 LT |
8 | * |
9 | * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. | |
10 | * | |
bc97ce95 | 11 | * |
1da177e4 LT |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
bc97ce95 | 16 | * |
1da177e4 LT |
17 | * This program is distributed in the hope that it will be useful, |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
bc97ce95 | 21 | * |
1da177e4 LT |
22 | * You should have received a copy of the GNU General Public License |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/types.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <asm/io.h> | |
36 | #include <asm/prom.h> | |
37 | #include <asm/rtas.h> | |
1da177e4 LT |
38 | #include <asm/iommu.h> |
39 | #include <asm/pci-bridge.h> | |
40 | #include <asm/machdep.h> | |
41 | #include <asm/abs_addr.h> | |
1da177e4 | 42 | #include <asm/pSeries_reconfig.h> |
1ababe11 | 43 | #include <asm/firmware.h> |
c707ffcf | 44 | #include <asm/tce.h> |
d387899f | 45 | #include <asm/ppc-pci.h> |
2249ca9d | 46 | #include <asm/udbg.h> |
1da177e4 | 47 | |
a1218720 ME |
48 | #include "plpar_wrappers.h" |
49 | ||
1da177e4 LT |
50 | #define DBG(fmt...) |
51 | ||
bc97ce95 OJ |
52 | static void tce_build_pSeries(struct iommu_table *tbl, long index, |
53 | long npages, unsigned long uaddr, | |
1da177e4 LT |
54 | enum dma_data_direction direction) |
55 | { | |
bc97ce95 OJ |
56 | u64 proto_tce; |
57 | u64 *tcep; | |
58 | u64 rpn; | |
1da177e4 | 59 | |
bc97ce95 | 60 | proto_tce = TCE_PCI_READ; // Read allowed |
1da177e4 LT |
61 | |
62 | if (direction != DMA_TO_DEVICE) | |
bc97ce95 | 63 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 | 64 | |
bc97ce95 | 65 | tcep = ((u64 *)tbl->it_base) + index; |
1da177e4 LT |
66 | |
67 | while (npages--) { | |
68 | /* can't move this out since we might cross LMB boundary */ | |
bc97ce95 OJ |
69 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
70 | *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; | |
1da177e4 | 71 | |
d0035c62 | 72 | uaddr += TCE_PAGE_SIZE; |
bc97ce95 | 73 | tcep++; |
1da177e4 LT |
74 | } |
75 | } | |
76 | ||
77 | ||
78 | static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) | |
79 | { | |
bc97ce95 | 80 | u64 *tcep; |
1da177e4 | 81 | |
bc97ce95 OJ |
82 | tcep = ((u64 *)tbl->it_base) + index; |
83 | ||
84 | while (npages--) | |
85 | *(tcep++) = 0; | |
1da177e4 LT |
86 | } |
87 | ||
5f50867b HM |
88 | static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) |
89 | { | |
90 | u64 *tcep; | |
91 | ||
5f50867b HM |
92 | tcep = ((u64 *)tbl->it_base) + index; |
93 | ||
94 | return *tcep; | |
95 | } | |
1da177e4 LT |
96 | |
97 | static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
98 | long npages, unsigned long uaddr, | |
99 | enum dma_data_direction direction) | |
100 | { | |
101 | u64 rc; | |
bc97ce95 OJ |
102 | u64 proto_tce, tce; |
103 | u64 rpn; | |
1da177e4 | 104 | |
bc97ce95 OJ |
105 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
106 | proto_tce = TCE_PCI_READ; | |
1da177e4 | 107 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 108 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
109 | |
110 | while (npages--) { | |
bc97ce95 OJ |
111 | tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
112 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce); | |
113 | ||
1da177e4 LT |
114 | if (rc && printk_ratelimit()) { |
115 | printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
116 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
117 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
bc97ce95 | 118 | printk("\ttce val = 0x%lx\n", tce ); |
1da177e4 LT |
119 | show_stack(current, (unsigned long *)__get_SP()); |
120 | } | |
bc97ce95 | 121 | |
1da177e4 | 122 | tcenum++; |
bc97ce95 | 123 | rpn++; |
1da177e4 LT |
124 | } |
125 | } | |
126 | ||
bc97ce95 | 127 | static DEFINE_PER_CPU(u64 *, tce_page) = NULL; |
1da177e4 LT |
128 | |
129 | static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, | |
130 | long npages, unsigned long uaddr, | |
131 | enum dma_data_direction direction) | |
132 | { | |
133 | u64 rc; | |
bc97ce95 OJ |
134 | u64 proto_tce; |
135 | u64 *tcep; | |
136 | u64 rpn; | |
1da177e4 LT |
137 | long l, limit; |
138 | ||
5d2efba6 | 139 | if (npages == 1) |
1da177e4 LT |
140 | return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, |
141 | direction); | |
142 | ||
143 | tcep = __get_cpu_var(tce_page); | |
144 | ||
145 | /* This is safe to do since interrupts are off when we're called | |
146 | * from iommu_alloc{,_sg}() | |
147 | */ | |
148 | if (!tcep) { | |
bc97ce95 | 149 | tcep = (u64 *)__get_free_page(GFP_ATOMIC); |
1da177e4 LT |
150 | /* If allocation fails, fall back to the loop implementation */ |
151 | if (!tcep) | |
152 | return tce_build_pSeriesLP(tbl, tcenum, npages, | |
153 | uaddr, direction); | |
154 | __get_cpu_var(tce_page) = tcep; | |
155 | } | |
156 | ||
bc97ce95 OJ |
157 | rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; |
158 | proto_tce = TCE_PCI_READ; | |
1da177e4 | 159 | if (direction != DMA_TO_DEVICE) |
bc97ce95 | 160 | proto_tce |= TCE_PCI_WRITE; |
1da177e4 LT |
161 | |
162 | /* We can map max one pageful of TCEs at a time */ | |
163 | do { | |
164 | /* | |
165 | * Set up the page with TCE data, looping through and setting | |
166 | * the values. | |
167 | */ | |
bc97ce95 | 168 | limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE); |
1da177e4 LT |
169 | |
170 | for (l = 0; l < limit; l++) { | |
bc97ce95 OJ |
171 | tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; |
172 | rpn++; | |
1da177e4 LT |
173 | } |
174 | ||
175 | rc = plpar_tce_put_indirect((u64)tbl->it_index, | |
176 | (u64)tcenum << 12, | |
177 | (u64)virt_to_abs(tcep), | |
178 | limit); | |
179 | ||
180 | npages -= limit; | |
181 | tcenum += limit; | |
182 | } while (npages > 0 && !rc); | |
183 | ||
184 | if (rc && printk_ratelimit()) { | |
185 | printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
186 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
187 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
bc97ce95 | 188 | printk("\ttce[0] val = 0x%lx\n", tcep[0]); |
1da177e4 LT |
189 | show_stack(current, (unsigned long *)__get_SP()); |
190 | } | |
191 | } | |
192 | ||
193 | static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
194 | { | |
195 | u64 rc; | |
1da177e4 | 196 | |
1da177e4 | 197 | while (npages--) { |
bc97ce95 | 198 | rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0); |
1da177e4 LT |
199 | |
200 | if (rc && printk_ratelimit()) { | |
201 | printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); | |
202 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
203 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
1da177e4 LT |
204 | show_stack(current, (unsigned long *)__get_SP()); |
205 | } | |
206 | ||
207 | tcenum++; | |
208 | } | |
209 | } | |
210 | ||
211 | ||
212 | static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) | |
213 | { | |
214 | u64 rc; | |
1da177e4 | 215 | |
bc97ce95 | 216 | rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); |
1da177e4 LT |
217 | |
218 | if (rc && printk_ratelimit()) { | |
219 | printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); | |
220 | printk("\trc = %ld\n", rc); | |
221 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
222 | printk("\tnpages = 0x%lx\n", (u64)npages); | |
1da177e4 LT |
223 | show_stack(current, (unsigned long *)__get_SP()); |
224 | } | |
225 | } | |
226 | ||
5f50867b HM |
227 | static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) |
228 | { | |
229 | u64 rc; | |
230 | unsigned long tce_ret; | |
231 | ||
5f50867b HM |
232 | rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret); |
233 | ||
234 | if (rc && printk_ratelimit()) { | |
235 | printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%ld\n", | |
236 | rc); | |
237 | printk("\tindex = 0x%lx\n", (u64)tbl->it_index); | |
238 | printk("\ttcenum = 0x%lx\n", (u64)tcenum); | |
239 | show_stack(current, (unsigned long *)__get_SP()); | |
240 | } | |
241 | ||
242 | return tce_ret; | |
243 | } | |
244 | ||
1da177e4 LT |
245 | static void iommu_table_setparms(struct pci_controller *phb, |
246 | struct device_node *dn, | |
bc97ce95 | 247 | struct iommu_table *tbl) |
1da177e4 LT |
248 | { |
249 | struct device_node *node; | |
9938c474 NL |
250 | const unsigned long *basep; |
251 | const u32 *sizep; | |
1da177e4 LT |
252 | |
253 | node = (struct device_node *)phb->arch_data; | |
254 | ||
954a46e2 JK |
255 | basep = get_property(node, "linux,tce-base", NULL); |
256 | sizep = get_property(node, "linux,tce-size", NULL); | |
1da177e4 LT |
257 | if (basep == NULL || sizep == NULL) { |
258 | printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " | |
259 | "missing tce entries !\n", dn->full_name); | |
260 | return; | |
261 | } | |
262 | ||
263 | tbl->it_base = (unsigned long)__va(*basep); | |
5f50867b HM |
264 | |
265 | #ifndef CONFIG_CRASH_DUMP | |
1da177e4 | 266 | memset((void *)tbl->it_base, 0, *sizep); |
5f50867b | 267 | #endif |
1da177e4 LT |
268 | |
269 | tbl->it_busno = phb->bus->number; | |
bc97ce95 | 270 | |
1da177e4 | 271 | /* Units of tce entries */ |
5d2efba6 | 272 | tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT; |
bc97ce95 | 273 | |
1da177e4 | 274 | /* Test if we are going over 2GB of DMA space */ |
3c2822cc OJ |
275 | if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { |
276 | udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); | |
bc97ce95 | 277 | panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); |
3c2822cc | 278 | } |
bc97ce95 | 279 | |
1da177e4 LT |
280 | phb->dma_window_base_cur += phb->dma_window_size; |
281 | ||
282 | /* Set the tce table size - measured in entries */ | |
5d2efba6 | 283 | tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT; |
1da177e4 LT |
284 | |
285 | tbl->it_index = 0; | |
286 | tbl->it_blocksize = 16; | |
287 | tbl->it_type = TCE_PCI; | |
288 | } | |
289 | ||
290 | /* | |
291 | * iommu_table_setparms_lpar | |
292 | * | |
293 | * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. | |
1da177e4 LT |
294 | */ |
295 | static void iommu_table_setparms_lpar(struct pci_controller *phb, | |
296 | struct device_node *dn, | |
297 | struct iommu_table *tbl, | |
954a46e2 | 298 | const void *dma_window) |
1da177e4 | 299 | { |
4c76e0bc JK |
300 | unsigned long offset, size; |
301 | ||
1635317f | 302 | tbl->it_busno = PCI_DN(dn)->bussubno; |
4c76e0bc | 303 | of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); |
1da177e4 | 304 | |
1da177e4 | 305 | tbl->it_base = 0; |
1da177e4 LT |
306 | tbl->it_blocksize = 16; |
307 | tbl->it_type = TCE_PCI; | |
5d2efba6 LV |
308 | tbl->it_offset = offset >> IOMMU_PAGE_SHIFT; |
309 | tbl->it_size = size >> IOMMU_PAGE_SHIFT; | |
1da177e4 LT |
310 | } |
311 | ||
12d04eef | 312 | static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) |
1da177e4 | 313 | { |
3c2822cc | 314 | struct device_node *dn; |
1da177e4 | 315 | struct iommu_table *tbl; |
3c2822cc OJ |
316 | struct device_node *isa_dn, *isa_dn_orig; |
317 | struct device_node *tmp; | |
318 | struct pci_dn *pci; | |
319 | int children; | |
1da177e4 | 320 | |
3c2822cc | 321 | dn = pci_bus_to_OF_node(bus); |
12d04eef BH |
322 | |
323 | DBG("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name); | |
3c2822cc OJ |
324 | |
325 | if (bus->self) { | |
326 | /* This is not a root bus, any setup will be done for the | |
327 | * device-side of the bridge in iommu_dev_setup_pSeries(). | |
328 | */ | |
329 | return; | |
330 | } | |
12d04eef | 331 | pci = PCI_DN(dn); |
3c2822cc OJ |
332 | |
333 | /* Check if the ISA bus on the system is under | |
334 | * this PHB. | |
1da177e4 | 335 | */ |
3c2822cc | 336 | isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); |
1da177e4 | 337 | |
3c2822cc OJ |
338 | while (isa_dn && isa_dn != dn) |
339 | isa_dn = isa_dn->parent; | |
340 | ||
341 | if (isa_dn_orig) | |
342 | of_node_put(isa_dn_orig); | |
1da177e4 | 343 | |
d3c58fb1 | 344 | /* Count number of direct PCI children of the PHB. */ |
3c2822cc | 345 | for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) |
d3c58fb1 | 346 | children++; |
1da177e4 | 347 | |
3c2822cc | 348 | DBG("Children: %d\n", children); |
1da177e4 | 349 | |
3c2822cc OJ |
350 | /* Calculate amount of DMA window per slot. Each window must be |
351 | * a power of two (due to pci_alloc_consistent requirements). | |
352 | * | |
353 | * Keep 256MB aside for PHBs with ISA. | |
354 | */ | |
1da177e4 | 355 | |
3c2822cc OJ |
356 | if (!isa_dn) { |
357 | /* No ISA/IDE - just set window size and return */ | |
358 | pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ | |
359 | ||
360 | while (pci->phb->dma_window_size * children > 0x80000000ul) | |
361 | pci->phb->dma_window_size >>= 1; | |
f951da37 AB |
362 | DBG("No ISA/IDE, window size is 0x%lx\n", |
363 | pci->phb->dma_window_size); | |
3c2822cc OJ |
364 | pci->phb->dma_window_base_cur = 0; |
365 | ||
366 | return; | |
1da177e4 | 367 | } |
3c2822cc OJ |
368 | |
369 | /* If we have ISA, then we probably have an IDE | |
370 | * controller too. Allocate a 128MB table but | |
371 | * skip the first 128MB to avoid stepping on ISA | |
372 | * space. | |
373 | */ | |
374 | pci->phb->dma_window_size = 0x8000000ul; | |
375 | pci->phb->dma_window_base_cur = 0x8000000ul; | |
376 | ||
ca1588e7 AB |
377 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
378 | pci->phb->node); | |
3c2822cc OJ |
379 | |
380 | iommu_table_setparms(pci->phb, dn, tbl); | |
ca1588e7 | 381 | pci->iommu_table = iommu_init_table(tbl, pci->phb->node); |
3c2822cc OJ |
382 | |
383 | /* Divide the rest (1.75GB) among the children */ | |
384 | pci->phb->dma_window_size = 0x80000000ul; | |
385 | while (pci->phb->dma_window_size * children > 0x70000000ul) | |
386 | pci->phb->dma_window_size >>= 1; | |
387 | ||
f951da37 | 388 | DBG("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size); |
3c2822cc | 389 | |
1da177e4 LT |
390 | } |
391 | ||
392 | ||
12d04eef | 393 | static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) |
1da177e4 LT |
394 | { |
395 | struct iommu_table *tbl; | |
396 | struct device_node *dn, *pdn; | |
1635317f | 397 | struct pci_dn *ppci; |
954a46e2 | 398 | const void *dma_window = NULL; |
1da177e4 | 399 | |
1da177e4 LT |
400 | dn = pci_bus_to_OF_node(bus); |
401 | ||
12d04eef BH |
402 | DBG("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n", dn->full_name); |
403 | ||
1da177e4 LT |
404 | /* Find nearest ibm,dma-window, walking up the device tree */ |
405 | for (pdn = dn; pdn != NULL; pdn = pdn->parent) { | |
4c76e0bc | 406 | dma_window = get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
407 | if (dma_window != NULL) |
408 | break; | |
409 | } | |
410 | ||
411 | if (dma_window == NULL) { | |
12d04eef | 412 | DBG(" no ibm,dma-window property !\n"); |
1da177e4 LT |
413 | return; |
414 | } | |
415 | ||
e07102db | 416 | ppci = PCI_DN(pdn); |
12d04eef BH |
417 | |
418 | DBG(" parent is %s, iommu_table: 0x%p\n", | |
419 | pdn->full_name, ppci->iommu_table); | |
420 | ||
1635317f | 421 | if (!ppci->iommu_table) { |
1da177e4 LT |
422 | /* Bussubno hasn't been copied yet. |
423 | * Do it now because iommu_table_setparms_lpar needs it. | |
424 | */ | |
1635317f PM |
425 | |
426 | ppci->bussubno = bus->number; | |
1da177e4 | 427 | |
ca1588e7 AB |
428 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
429 | ppci->phb->node); | |
bc97ce95 | 430 | |
1635317f | 431 | iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window); |
1da177e4 | 432 | |
ca1588e7 | 433 | ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node); |
12d04eef | 434 | DBG(" created table: %p\n", ppci->iommu_table); |
1da177e4 LT |
435 | } |
436 | ||
437 | if (pdn != dn) | |
1635317f | 438 | PCI_DN(dn)->iommu_table = ppci->iommu_table; |
1da177e4 LT |
439 | } |
440 | ||
441 | ||
12d04eef | 442 | static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) |
1da177e4 | 443 | { |
12d04eef | 444 | struct device_node *dn; |
3c2822cc | 445 | struct iommu_table *tbl; |
1da177e4 | 446 | |
12d04eef | 447 | DBG("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); |
1da177e4 | 448 | |
12d04eef | 449 | dn = dev->dev.archdata.of_node; |
1da177e4 | 450 | |
3c2822cc OJ |
451 | /* If we're the direct child of a root bus, then we need to allocate |
452 | * an iommu table ourselves. The bus setup code should have setup | |
453 | * the window sizes already. | |
454 | */ | |
455 | if (!dev->bus->self) { | |
12d04eef BH |
456 | struct pci_controller *phb = PCI_DN(dn)->phb; |
457 | ||
3c2822cc | 458 | DBG(" --> first child, no bridge. Allocating iommu table.\n"); |
ca1588e7 | 459 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
12d04eef BH |
460 | phb->node); |
461 | iommu_table_setparms(phb, dn, tbl); | |
77319254 LV |
462 | PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node); |
463 | dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; | |
3c2822cc OJ |
464 | return; |
465 | } | |
466 | ||
467 | /* If this device is further down the bus tree, search upwards until | |
468 | * an already allocated iommu table is found and use that. | |
469 | */ | |
470 | ||
e07102db | 471 | while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL) |
1da177e4 LT |
472 | dn = dn->parent; |
473 | ||
12d04eef BH |
474 | if (dn && PCI_DN(dn)) |
475 | dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; | |
476 | else | |
477 | printk(KERN_WARNING "iommu: Device %s has no iommu table\n", | |
478 | pci_name(dev)); | |
1da177e4 LT |
479 | } |
480 | ||
481 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) | |
482 | { | |
483 | int err = NOTIFY_OK; | |
484 | struct device_node *np = node; | |
e07102db | 485 | struct pci_dn *pci = PCI_DN(np); |
1da177e4 LT |
486 | |
487 | switch (action) { | |
488 | case PSERIES_RECONFIG_REMOVE: | |
8902e87f | 489 | if (pci && pci->iommu_table && |
1da177e4 LT |
490 | get_property(np, "ibm,dma-window", NULL)) |
491 | iommu_free_table(np); | |
492 | break; | |
493 | default: | |
494 | err = NOTIFY_DONE; | |
495 | break; | |
496 | } | |
497 | return err; | |
498 | } | |
499 | ||
500 | static struct notifier_block iommu_reconfig_nb = { | |
501 | .notifier_call = iommu_reconfig_notifier, | |
502 | }; | |
503 | ||
12d04eef | 504 | static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) |
1da177e4 LT |
505 | { |
506 | struct device_node *pdn, *dn; | |
507 | struct iommu_table *tbl; | |
954a46e2 | 508 | const void *dma_window = NULL; |
1635317f | 509 | struct pci_dn *pci; |
1da177e4 | 510 | |
12d04eef BH |
511 | DBG("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); |
512 | ||
1da177e4 LT |
513 | /* dev setup for LPAR is a little tricky, since the device tree might |
514 | * contain the dma-window properties per-device and not neccesarily | |
515 | * for the bus. So we need to search upwards in the tree until we | |
516 | * either hit a dma-window property, OR find a parent with a table | |
517 | * already allocated. | |
518 | */ | |
519 | dn = pci_device_to_OF_node(dev); | |
12d04eef | 520 | DBG(" node is %s\n", dn->full_name); |
5d2efba6 | 521 | |
e07102db | 522 | for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; |
1635317f | 523 | pdn = pdn->parent) { |
4c76e0bc | 524 | dma_window = get_property(pdn, "ibm,dma-window", NULL); |
1da177e4 LT |
525 | if (dma_window) |
526 | break; | |
527 | } | |
528 | ||
12d04eef BH |
529 | DBG(" parent is %s\n", pdn->full_name); |
530 | ||
1da177e4 LT |
531 | /* Check for parent == NULL so we don't try to setup the empty EADS |
532 | * slots on POWER4 machines. | |
533 | */ | |
534 | if (dma_window == NULL || pdn->parent == NULL) { | |
12d04eef BH |
535 | DBG(" no dma window for device, linking to parent\n"); |
536 | dev->dev.archdata.dma_data = PCI_DN(pdn)->iommu_table; | |
1da177e4 | 537 | return; |
1da177e4 | 538 | } |
12d04eef | 539 | DBG(" found DMA window, table: %p\n", pci->iommu_table); |
1da177e4 | 540 | |
e07102db | 541 | pci = PCI_DN(pdn); |
1635317f | 542 | if (!pci->iommu_table) { |
1da177e4 | 543 | /* iommu_table_setparms_lpar needs bussubno. */ |
1635317f | 544 | pci->bussubno = pci->phb->bus->number; |
1da177e4 | 545 | |
ca1588e7 AB |
546 | tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, |
547 | pci->phb->node); | |
1da177e4 | 548 | |
1635317f | 549 | iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window); |
1da177e4 | 550 | |
ca1588e7 | 551 | pci->iommu_table = iommu_init_table(tbl, pci->phb->node); |
12d04eef | 552 | DBG(" created table: %p\n", pci->iommu_table); |
1da177e4 LT |
553 | } |
554 | ||
12d04eef | 555 | dev->dev.archdata.dma_data = pci->iommu_table; |
1da177e4 LT |
556 | } |
557 | ||
1da177e4 LT |
558 | /* These are called very early. */ |
559 | void iommu_init_early_pSeries(void) | |
560 | { | |
561 | if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) { | |
562 | /* Direct I/O, IOMMU off */ | |
12d04eef BH |
563 | ppc_md.pci_dma_dev_setup = NULL; |
564 | ppc_md.pci_dma_bus_setup = NULL; | |
565 | pci_dma_ops = &dma_direct_ops; | |
1da177e4 LT |
566 | return; |
567 | } | |
568 | ||
57cfb814 | 569 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1ababe11 | 570 | if (firmware_has_feature(FW_FEATURE_MULTITCE)) { |
1da177e4 LT |
571 | ppc_md.tce_build = tce_buildmulti_pSeriesLP; |
572 | ppc_md.tce_free = tce_freemulti_pSeriesLP; | |
573 | } else { | |
574 | ppc_md.tce_build = tce_build_pSeriesLP; | |
575 | ppc_md.tce_free = tce_free_pSeriesLP; | |
576 | } | |
5f50867b | 577 | ppc_md.tce_get = tce_get_pSeriesLP; |
12d04eef BH |
578 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP; |
579 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP; | |
1da177e4 LT |
580 | } else { |
581 | ppc_md.tce_build = tce_build_pSeries; | |
582 | ppc_md.tce_free = tce_free_pSeries; | |
5f50867b | 583 | ppc_md.tce_get = tce_get_pseries; |
12d04eef BH |
584 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries; |
585 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries; | |
1da177e4 LT |
586 | } |
587 | ||
588 | ||
589 | pSeries_reconfig_notifier_register(&iommu_reconfig_nb); | |
590 | ||
12d04eef | 591 | pci_dma_ops = &dma_iommu_ops; |
1da177e4 LT |
592 | } |
593 |