Commit | Line | Data |
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1da177e4 | 1 | /* |
3c8c90ab LV |
2 | * Copyright IBM Corporation 2001, 2005, 2006 |
3 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
4 | * Copyright Linas Vepstas 2005, 2006 | |
cb3bc9d0 | 5 | * Copyright 2001-2012 IBM Corporation. |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
6dee3fb9 | 24 | #include <linux/delay.h> |
cb3bc9d0 | 25 | #include <linux/sched.h> |
1da177e4 LT |
26 | #include <linux/init.h> |
27 | #include <linux/list.h> | |
1da177e4 LT |
28 | #include <linux/pci.h> |
29 | #include <linux/proc_fs.h> | |
30 | #include <linux/rbtree.h> | |
31 | #include <linux/seq_file.h> | |
32 | #include <linux/spinlock.h> | |
66b15db6 | 33 | #include <linux/export.h> |
acaa6176 SR |
34 | #include <linux/of.h> |
35 | ||
60063497 | 36 | #include <linux/atomic.h> |
1da177e4 | 37 | #include <asm/eeh.h> |
172ca926 | 38 | #include <asm/eeh_event.h> |
1da177e4 LT |
39 | #include <asm/io.h> |
40 | #include <asm/machdep.h> | |
172ca926 | 41 | #include <asm/ppc-pci.h> |
1da177e4 | 42 | #include <asm/rtas.h> |
1da177e4 | 43 | |
1da177e4 LT |
44 | |
45 | /** Overview: | |
46 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
47 | * dealing with PCI bus errors that can't be dealt with within the | |
48 | * usual PCI framework, except by check-stopping the CPU. Systems | |
49 | * that are designed for high-availability/reliability cannot afford | |
50 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
51 | * An EEH-capable bridge operates by converting a detected error | |
52 | * into a "slot freeze", taking the PCI adapter off-line, making | |
53 | * the slot behave, from the OS'es point of view, as if the slot | |
54 | * were "empty": all reads return 0xff's and all writes are silently | |
55 | * ignored. EEH slot isolation events can be triggered by parity | |
56 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
57 | * which in turn might be caused by low voltage on the bus, dust, |
58 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
59 | * |
60 | * Note, however, that one of the leading causes of EEH slot | |
61 | * freeze events are buggy device drivers, buggy device microcode, | |
62 | * or buggy device hardware. This is because any attempt by the | |
63 | * device to bus-master data to a memory address that is not | |
64 | * assigned to the device will trigger a slot freeze. (The idea | |
65 | * is to prevent devices-gone-wild from corrupting system memory). | |
66 | * Buggy hardware/drivers will have a miserable time co-existing | |
67 | * with EEH. | |
68 | * | |
69 | * Ideally, a PCI device driver, when suspecting that an isolation | |
25985edc | 70 | * event has occurred (e.g. by reading 0xff's), will then ask EEH |
1da177e4 LT |
71 | * whether this is the case, and then take appropriate steps to |
72 | * reset the PCI slot, the PCI device, and then resume operations. | |
73 | * However, until that day, the checking is done here, with the | |
74 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
75 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
76 | * and sent out for processing. | |
77 | */ | |
78 | ||
5c1344e9 | 79 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
80 | * handler after a slot isolation event, it might be broken. |
81 | * This sets the threshold for how many read attempts we allow | |
82 | * before printing an error message. | |
1da177e4 | 83 | */ |
2fd30be8 | 84 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 85 | |
17213c3b | 86 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
9c547768 LV |
87 | #define PCI_BUS_RESET_WAIT_MSEC (60*1000) |
88 | ||
aa1e6374 GS |
89 | /* Platform dependent EEH operations */ |
90 | struct eeh_ops *eeh_ops = NULL; | |
91 | ||
1e28a7dd DW |
92 | int eeh_subsystem_enabled; |
93 | EXPORT_SYMBOL(eeh_subsystem_enabled); | |
1da177e4 | 94 | |
fd761fd8 | 95 | /* Lock to avoid races due to multiple reports of an error */ |
3d372628 | 96 | static DEFINE_RAW_SPINLOCK(confirm_error_lock); |
fd761fd8 | 97 | |
17213c3b LV |
98 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
99 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
100 | * can access it. | |
101 | */ | |
d99bb1db LV |
102 | #define EEH_PCI_REGS_LOG_LEN 4096 |
103 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
104 | ||
e575f8db GS |
105 | /* |
106 | * The struct is used to maintain the EEH global statistic | |
107 | * information. Besides, the EEH global statistics will be | |
108 | * exported to user space through procfs | |
109 | */ | |
110 | struct eeh_stats { | |
111 | u64 no_device; /* PCI device not found */ | |
112 | u64 no_dn; /* OF node not found */ | |
113 | u64 no_cfg_addr; /* Config address not found */ | |
114 | u64 ignored_check; /* EEH check skipped */ | |
115 | u64 total_mmio_ffs; /* Total EEH checks */ | |
116 | u64 false_positives; /* Unnecessary EEH checks */ | |
117 | u64 slot_resets; /* PE reset */ | |
118 | }; | |
119 | ||
120 | static struct eeh_stats eeh_stats; | |
1da177e4 | 121 | |
7684b40c LV |
122 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
123 | ||
d99bb1db | 124 | /** |
cce4b2d2 | 125 | * eeh_gather_pci_data - Copy assorted PCI config space registers to buff |
f631acd3 | 126 | * @edev: device to report data for |
d99bb1db LV |
127 | * @buf: point to buffer in which to log |
128 | * @len: amount of room in buffer | |
129 | * | |
130 | * This routine captures assorted PCI configuration space data, | |
131 | * and puts them into a buffer for RTAS error logging. | |
132 | */ | |
f631acd3 | 133 | static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len) |
d99bb1db | 134 | { |
f631acd3 GS |
135 | struct device_node *dn = eeh_dev_to_of_node(edev); |
136 | struct pci_dev *dev = eeh_dev_to_pci_dev(edev); | |
d99bb1db | 137 | u32 cfg; |
fcf9892b | 138 | int cap, i; |
d99bb1db LV |
139 | int n = 0; |
140 | ||
f631acd3 GS |
141 | n += scnprintf(buf+n, len-n, "%s\n", dn->full_name); |
142 | printk(KERN_WARNING "EEH: of node=%s\n", dn->full_name); | |
fcf9892b | 143 | |
f631acd3 | 144 | rtas_read_config(PCI_DN(dn), PCI_VENDOR_ID, 4, &cfg); |
fcf9892b LV |
145 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
146 | printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg); | |
147 | ||
f631acd3 | 148 | rtas_read_config(PCI_DN(dn), PCI_COMMAND, 4, &cfg); |
d99bb1db | 149 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); |
fcf9892b LV |
150 | printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg); |
151 | ||
b37ceefe LV |
152 | if (!dev) { |
153 | printk(KERN_WARNING "EEH: no PCI device for this of node\n"); | |
154 | return n; | |
155 | } | |
156 | ||
0b9369f4 LV |
157 | /* Gather bridge-specific registers */ |
158 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
f631acd3 | 159 | rtas_read_config(PCI_DN(dn), PCI_SEC_STATUS, 2, &cfg); |
0b9369f4 LV |
160 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); |
161 | printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg); | |
162 | ||
f631acd3 | 163 | rtas_read_config(PCI_DN(dn), PCI_BRIDGE_CONTROL, 2, &cfg); |
0b9369f4 LV |
164 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); |
165 | printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg); | |
166 | } | |
167 | ||
fcf9892b | 168 | /* Dump out the PCI-X command and status regs */ |
b37ceefe | 169 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
fcf9892b | 170 | if (cap) { |
f631acd3 | 171 | rtas_read_config(PCI_DN(dn), cap, 4, &cfg); |
fcf9892b LV |
172 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); |
173 | printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg); | |
174 | ||
f631acd3 | 175 | rtas_read_config(PCI_DN(dn), cap+4, 4, &cfg); |
fcf9892b LV |
176 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); |
177 | printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg); | |
178 | } | |
179 | ||
180 | /* If PCI-E capable, dump PCI-E cap 10, and the AER */ | |
b37ceefe | 181 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); |
fcf9892b LV |
182 | if (cap) { |
183 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); | |
184 | printk(KERN_WARNING | |
185 | "EEH: PCI-E capabilities and status follow:\n"); | |
186 | ||
187 | for (i=0; i<=8; i++) { | |
f631acd3 | 188 | rtas_read_config(PCI_DN(dn), cap+4*i, 4, &cfg); |
fcf9892b LV |
189 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
190 | printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg); | |
191 | } | |
192 | ||
b37ceefe | 193 | cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
fcf9892b LV |
194 | if (cap) { |
195 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
196 | printk(KERN_WARNING | |
197 | "EEH: PCI-E AER capability register set follows:\n"); | |
198 | ||
199 | for (i=0; i<14; i++) { | |
f631acd3 | 200 | rtas_read_config(PCI_DN(dn), cap+4*i, 4, &cfg); |
fcf9892b LV |
201 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
202 | printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
203 | } | |
204 | } | |
205 | } | |
0b9369f4 LV |
206 | |
207 | /* Gather status on devices under the bridge */ | |
208 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
f631acd3 | 209 | struct device_node *child; |
acaa6176 | 210 | |
f631acd3 GS |
211 | for_each_child_of_node(dn, child) { |
212 | if (of_node_to_eeh_dev(child)) | |
213 | n += eeh_gather_pci_data(of_node_to_eeh_dev(child), buf+n, len-n); | |
0b9369f4 LV |
214 | } |
215 | } | |
216 | ||
d99bb1db LV |
217 | return n; |
218 | } | |
219 | ||
cb3bc9d0 GS |
220 | /** |
221 | * eeh_slot_error_detail - Generate combined log including driver log and error log | |
f631acd3 | 222 | * @edev: device to report error log for |
cb3bc9d0 GS |
223 | * @severity: temporary or permanent error log |
224 | * | |
225 | * This routine should be called to generate the combined log, which | |
226 | * is comprised of driver log and error log. The driver log is figured | |
227 | * out from the config space of the corresponding PCI device, while | |
228 | * the error log is fetched through platform dependent function call. | |
229 | */ | |
f631acd3 | 230 | void eeh_slot_error_detail(struct eeh_dev *edev, int severity) |
d99bb1db LV |
231 | { |
232 | size_t loglen = 0; | |
17213c3b | 233 | pci_regs_buf[0] = 0; |
d99bb1db | 234 | |
f631acd3 GS |
235 | eeh_pci_enable(edev, EEH_OPT_THAW_MMIO); |
236 | eeh_ops->configure_bridge(eeh_dev_to_of_node(edev)); | |
237 | eeh_restore_bars(edev); | |
238 | loglen = eeh_gather_pci_data(edev, pci_regs_buf, EEH_PCI_REGS_LOG_LEN); | |
d99bb1db | 239 | |
f631acd3 | 240 | eeh_ops->get_log(eeh_dev_to_of_node(edev), severity, pci_regs_buf, loglen); |
d99bb1db LV |
241 | } |
242 | ||
1da177e4 | 243 | /** |
cb3bc9d0 GS |
244 | * eeh_token_to_phys - Convert EEH address token to phys address |
245 | * @token: I/O token, should be address in the form 0xA.... | |
246 | * | |
247 | * This routine should be called to convert virtual I/O address | |
248 | * to physical one. | |
1da177e4 LT |
249 | */ |
250 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
251 | { | |
252 | pte_t *ptep; | |
253 | unsigned long pa; | |
254 | ||
20cee16c | 255 | ptep = find_linux_pte(init_mm.pgd, token); |
1da177e4 LT |
256 | if (!ptep) |
257 | return token; | |
258 | pa = pte_pfn(*ptep) << PAGE_SHIFT; | |
259 | ||
260 | return pa | (token & (PAGE_SIZE-1)); | |
261 | } | |
262 | ||
cb3bc9d0 | 263 | /** |
cce4b2d2 | 264 | * eeh_find_device_pe - Retrieve the PE for the given device |
cb3bc9d0 GS |
265 | * @dn: device node |
266 | * | |
267 | * Return the PE under which this device lies | |
fd761fd8 | 268 | */ |
cce4b2d2 | 269 | struct device_node *eeh_find_device_pe(struct device_node *dn) |
fd761fd8 | 270 | { |
f631acd3 GS |
271 | while (dn->parent && of_node_to_eeh_dev(dn->parent) && |
272 | (of_node_to_eeh_dev(dn->parent)->mode & EEH_MODE_SUPPORTED)) { | |
fd761fd8 LV |
273 | dn = dn->parent; |
274 | } | |
275 | return dn; | |
276 | } | |
277 | ||
cb3bc9d0 GS |
278 | /** |
279 | * __eeh_mark_slot - Mark all child devices as failed | |
280 | * @parent: parent device | |
281 | * @mode_flag: failure flag | |
282 | * | |
283 | * Mark all devices that are children of this device as failed. | |
284 | * Mark the device driver too, so that it can see the failure | |
285 | * immediately; this is critical, since some drivers poll | |
286 | * status registers in interrupts ... If a driver is polling, | |
287 | * and the slot is frozen, then the driver can deadlock in | |
288 | * an interrupt context, which is bad. | |
fd761fd8 | 289 | */ |
acaa6176 | 290 | static void __eeh_mark_slot(struct device_node *parent, int mode_flag) |
fd761fd8 | 291 | { |
acaa6176 SR |
292 | struct device_node *dn; |
293 | ||
294 | for_each_child_of_node(parent, dn) { | |
f631acd3 | 295 | if (of_node_to_eeh_dev(dn)) { |
77bd7415 | 296 | /* Mark the pci device driver too */ |
f631acd3 | 297 | struct pci_dev *dev = of_node_to_eeh_dev(dn)->pdev; |
ea183a95 | 298 | |
f631acd3 | 299 | of_node_to_eeh_dev(dn)->mode |= mode_flag; |
ea183a95 | 300 | |
77bd7415 LV |
301 | if (dev && dev->driver) |
302 | dev->error_state = pci_channel_io_frozen; | |
303 | ||
acaa6176 | 304 | __eeh_mark_slot(dn, mode_flag); |
d9564ad1 | 305 | } |
fd761fd8 LV |
306 | } |
307 | } | |
308 | ||
cb3bc9d0 GS |
309 | /** |
310 | * eeh_mark_slot - Mark the indicated device and its children as failed | |
311 | * @dn: parent device | |
312 | * @mode_flag: failure flag | |
313 | * | |
314 | * Mark the indicated device and its child devices as failed. | |
315 | * The device drivers are marked as failed as well. | |
316 | */ | |
317 | void eeh_mark_slot(struct device_node *dn, int mode_flag) | |
d9564ad1 | 318 | { |
022d51b1 | 319 | struct pci_dev *dev; |
cce4b2d2 | 320 | dn = eeh_find_device_pe(dn); |
3914ac7b LV |
321 | |
322 | /* Back up one, since config addrs might be shared */ | |
f631acd3 | 323 | if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent)) |
3914ac7b LV |
324 | dn = dn->parent; |
325 | ||
f631acd3 | 326 | of_node_to_eeh_dev(dn)->mode |= mode_flag; |
022d51b1 LV |
327 | |
328 | /* Mark the pci device too */ | |
f631acd3 | 329 | dev = of_node_to_eeh_dev(dn)->pdev; |
022d51b1 LV |
330 | if (dev) |
331 | dev->error_state = pci_channel_io_frozen; | |
332 | ||
acaa6176 | 333 | __eeh_mark_slot(dn, mode_flag); |
d9564ad1 LV |
334 | } |
335 | ||
cb3bc9d0 GS |
336 | /** |
337 | * __eeh_clear_slot - Clear failure flag for the child devices | |
338 | * @parent: parent device | |
339 | * @mode_flag: flag to be cleared | |
340 | * | |
341 | * Clear failure flag for the child devices. | |
342 | */ | |
acaa6176 | 343 | static void __eeh_clear_slot(struct device_node *parent, int mode_flag) |
fd761fd8 | 344 | { |
acaa6176 SR |
345 | struct device_node *dn; |
346 | ||
347 | for_each_child_of_node(parent, dn) { | |
f631acd3 GS |
348 | if (of_node_to_eeh_dev(dn)) { |
349 | of_node_to_eeh_dev(dn)->mode &= ~mode_flag; | |
350 | of_node_to_eeh_dev(dn)->check_count = 0; | |
acaa6176 | 351 | __eeh_clear_slot(dn, mode_flag); |
d9564ad1 | 352 | } |
fd761fd8 LV |
353 | } |
354 | } | |
355 | ||
cb3bc9d0 GS |
356 | /** |
357 | * eeh_clear_slot - Clear failure flag for the indicated device and its children | |
358 | * @dn: parent device | |
359 | * @mode_flag: flag to be cleared | |
360 | * | |
361 | * Clear failure flag for the indicated device and its children. | |
362 | */ | |
363 | void eeh_clear_slot(struct device_node *dn, int mode_flag) | |
fd761fd8 LV |
364 | { |
365 | unsigned long flags; | |
3d372628 | 366 | raw_spin_lock_irqsave(&confirm_error_lock, flags); |
3914ac7b | 367 | |
cce4b2d2 | 368 | dn = eeh_find_device_pe(dn); |
3914ac7b LV |
369 | |
370 | /* Back up one, since config addrs might be shared */ | |
f631acd3 | 371 | if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent)) |
3914ac7b LV |
372 | dn = dn->parent; |
373 | ||
f631acd3 GS |
374 | of_node_to_eeh_dev(dn)->mode &= ~mode_flag; |
375 | of_node_to_eeh_dev(dn)->check_count = 0; | |
acaa6176 | 376 | __eeh_clear_slot(dn, mode_flag); |
3d372628 | 377 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
fd761fd8 LV |
378 | } |
379 | ||
1da177e4 | 380 | /** |
cb3bc9d0 GS |
381 | * eeh_dn_check_failure - Check if all 1's data is due to EEH slot freeze |
382 | * @dn: device node | |
383 | * @dev: pci device, if known | |
1da177e4 LT |
384 | * |
385 | * Check for an EEH failure for the given device node. Call this | |
386 | * routine if the result of a read was all 0xff's and you want to | |
387 | * find out if this is due to an EEH slot freeze. This routine | |
388 | * will query firmware for the EEH status. | |
389 | * | |
390 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 391 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
392 | * |
393 | * It is safe to call this routine in an interrupt context. | |
394 | */ | |
395 | int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) | |
396 | { | |
397 | int ret; | |
1da177e4 | 398 | unsigned long flags; |
f631acd3 | 399 | struct eeh_dev *edev; |
fd761fd8 | 400 | int rc = 0; |
f36c5227 | 401 | const char *location; |
1da177e4 | 402 | |
e575f8db | 403 | eeh_stats.total_mmio_ffs++; |
1da177e4 LT |
404 | |
405 | if (!eeh_subsystem_enabled) | |
406 | return 0; | |
407 | ||
177bc936 | 408 | if (!dn) { |
e575f8db | 409 | eeh_stats.no_dn++; |
1da177e4 | 410 | return 0; |
177bc936 | 411 | } |
cce4b2d2 | 412 | dn = eeh_find_device_pe(dn); |
f631acd3 | 413 | edev = of_node_to_eeh_dev(dn); |
1da177e4 LT |
414 | |
415 | /* Access to IO BARs might get this far and still not want checking. */ | |
f631acd3 GS |
416 | if (!(edev->mode & EEH_MODE_SUPPORTED) || |
417 | edev->mode & EEH_MODE_NOCHECK) { | |
e575f8db | 418 | eeh_stats.ignored_check++; |
57b066ff | 419 | pr_debug("EEH: Ignored check (%x) for %s %s\n", |
f631acd3 | 420 | edev->mode, eeh_pci_name(dev), dn->full_name); |
1da177e4 LT |
421 | return 0; |
422 | } | |
423 | ||
f631acd3 | 424 | if (!edev->config_addr && !edev->pe_config_addr) { |
e575f8db | 425 | eeh_stats.no_cfg_addr++; |
1da177e4 LT |
426 | return 0; |
427 | } | |
428 | ||
fd761fd8 LV |
429 | /* If we already have a pending isolation event for this |
430 | * slot, we know it's bad already, we don't need to check. | |
431 | * Do this checking under a lock; as multiple PCI devices | |
432 | * in one slot might report errors simultaneously, and we | |
433 | * only want one error recovery routine running. | |
1da177e4 | 434 | */ |
3d372628 | 435 | raw_spin_lock_irqsave(&confirm_error_lock, flags); |
fd761fd8 | 436 | rc = 1; |
f631acd3 GS |
437 | if (edev->mode & EEH_MODE_ISOLATED) { |
438 | edev->check_count++; | |
439 | if (edev->check_count % EEH_MAX_FAILS == 0) { | |
f36c5227 | 440 | location = of_get_property(dn, "ibm,loc-code", NULL); |
cb3bc9d0 | 441 | printk(KERN_ERR "EEH: %d reads ignored for recovering device at " |
f36c5227 | 442 | "location=%s driver=%s pci addr=%s\n", |
f631acd3 | 443 | edev->check_count, location, |
778a785f | 444 | eeh_driver_name(dev), eeh_pci_name(dev)); |
cb3bc9d0 | 445 | printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
778a785f | 446 | eeh_driver_name(dev)); |
5c1344e9 | 447 | dump_stack(); |
1da177e4 | 448 | } |
fd761fd8 | 449 | goto dn_unlock; |
1da177e4 LT |
450 | } |
451 | ||
452 | /* | |
453 | * Now test for an EEH failure. This is VERY expensive. | |
454 | * Note that the eeh_config_addr may be a parent device | |
455 | * in the case of a device behind a bridge, or it may be | |
456 | * function zero of a multi-function device. | |
457 | * In any case they must share a common PHB. | |
458 | */ | |
f631acd3 | 459 | ret = eeh_ops->get_state(dn, NULL); |
76e6faf7 | 460 | |
39d16e29 | 461 | /* Note that config-io to empty slots may fail; |
cb3bc9d0 | 462 | * they are empty when they don't have children. |
eb594a47 GS |
463 | * We will punt with the following conditions: Failure to get |
464 | * PE's state, EEH not support and Permanently unavailable | |
465 | * state, PE is in good state. | |
cb3bc9d0 | 466 | */ |
eb594a47 GS |
467 | if ((ret < 0) || |
468 | (ret == EEH_STATE_NOT_SUPPORT) || | |
469 | (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == | |
470 | (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { | |
e575f8db | 471 | eeh_stats.false_positives++; |
f631acd3 | 472 | edev->false_positives ++; |
fd761fd8 LV |
473 | rc = 0; |
474 | goto dn_unlock; | |
76e6faf7 LV |
475 | } |
476 | ||
e575f8db | 477 | eeh_stats.slot_resets++; |
fd761fd8 LV |
478 | |
479 | /* Avoid repeated reports of this failure, including problems | |
480 | * with other functions on this device, and functions under | |
cb3bc9d0 GS |
481 | * bridges. |
482 | */ | |
483 | eeh_mark_slot(dn, EEH_MODE_ISOLATED); | |
3d372628 | 484 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
1da177e4 | 485 | |
40a7cd92 | 486 | eeh_send_failure_event(edev); |
77bd7415 | 487 | |
1da177e4 LT |
488 | /* Most EEH events are due to device driver bugs. Having |
489 | * a stack trace will help the device-driver authors figure | |
cb3bc9d0 GS |
490 | * out what happened. So print that out. |
491 | */ | |
90375f53 | 492 | dump_stack(); |
fd761fd8 LV |
493 | return 1; |
494 | ||
495 | dn_unlock: | |
3d372628 | 496 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
fd761fd8 | 497 | return rc; |
1da177e4 LT |
498 | } |
499 | ||
fd761fd8 | 500 | EXPORT_SYMBOL_GPL(eeh_dn_check_failure); |
1da177e4 LT |
501 | |
502 | /** | |
cb3bc9d0 GS |
503 | * eeh_check_failure - Check if all 1's data is due to EEH slot freeze |
504 | * @token: I/O token, should be address in the form 0xA.... | |
505 | * @val: value, should be all 1's (XXX why do we need this arg??) | |
1da177e4 | 506 | * |
1da177e4 LT |
507 | * Check for an EEH failure at the given token address. Call this |
508 | * routine if the result of a read was all 0xff's and you want to | |
509 | * find out if this is due to an EEH slot freeze event. This routine | |
510 | * will query firmware for the EEH status. | |
511 | * | |
512 | * Note this routine is safe to call in an interrupt context. | |
513 | */ | |
514 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
515 | { | |
516 | unsigned long addr; | |
517 | struct pci_dev *dev; | |
518 | struct device_node *dn; | |
519 | ||
520 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
521 | addr = eeh_token_to_phys((unsigned long __force) token); | |
def9d83d | 522 | dev = pci_addr_cache_get_device(addr); |
177bc936 | 523 | if (!dev) { |
e575f8db | 524 | eeh_stats.no_device++; |
1da177e4 | 525 | return val; |
177bc936 | 526 | } |
1da177e4 LT |
527 | |
528 | dn = pci_device_to_OF_node(dev); | |
cb3bc9d0 | 529 | eeh_dn_check_failure(dn, dev); |
1da177e4 LT |
530 | |
531 | pci_dev_put(dev); | |
532 | return val; | |
533 | } | |
534 | ||
535 | EXPORT_SYMBOL(eeh_check_failure); | |
536 | ||
6dee3fb9 | 537 | |
47b5c838 | 538 | /** |
cce4b2d2 | 539 | * eeh_pci_enable - Enable MMIO or DMA transfers for this slot |
f631acd3 | 540 | * @edev: pci device node |
cb3bc9d0 GS |
541 | * |
542 | * This routine should be called to reenable frozen MMIO or DMA | |
543 | * so that it would work correctly again. It's useful while doing | |
544 | * recovery or log collection on the indicated device. | |
47b5c838 | 545 | */ |
f631acd3 | 546 | int eeh_pci_enable(struct eeh_dev *edev, int function) |
47b5c838 | 547 | { |
47b5c838 | 548 | int rc; |
f631acd3 | 549 | struct device_node *dn = eeh_dev_to_of_node(edev); |
47b5c838 | 550 | |
f631acd3 | 551 | rc = eeh_ops->set_option(dn, function); |
47b5c838 | 552 | if (rc) |
fa1be476 | 553 | printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n", |
f631acd3 | 554 | function, rc, dn->full_name); |
47b5c838 | 555 | |
f631acd3 | 556 | rc = eeh_ops->wait_state(dn, PCI_BUS_RESET_WAIT_MSEC); |
eb594a47 GS |
557 | if (rc > 0 && (rc & EEH_STATE_MMIO_ENABLED) && |
558 | (function == EEH_OPT_THAW_MMIO)) | |
fa1be476 LV |
559 | return 0; |
560 | ||
47b5c838 LV |
561 | return rc; |
562 | } | |
563 | ||
00c2ae35 BK |
564 | /** |
565 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
cb3bc9d0 GS |
566 | * @dev: pci device struct |
567 | * @state: reset state to enter | |
00c2ae35 BK |
568 | * |
569 | * Return value: | |
570 | * 0 if success | |
cb3bc9d0 | 571 | */ |
00c2ae35 BK |
572 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
573 | { | |
574 | struct device_node *dn = pci_device_to_OF_node(dev); | |
00c2ae35 BK |
575 | |
576 | switch (state) { | |
577 | case pcie_deassert_reset: | |
2652481f | 578 | eeh_ops->reset(dn, EEH_RESET_DEACTIVATE); |
00c2ae35 BK |
579 | break; |
580 | case pcie_hot_reset: | |
2652481f | 581 | eeh_ops->reset(dn, EEH_RESET_HOT); |
00c2ae35 BK |
582 | break; |
583 | case pcie_warm_reset: | |
2652481f | 584 | eeh_ops->reset(dn, EEH_RESET_FUNDAMENTAL); |
00c2ae35 BK |
585 | break; |
586 | default: | |
587 | return -EINVAL; | |
588 | }; | |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
cb5b5624 | 593 | /** |
cb3bc9d0 GS |
594 | * __eeh_set_pe_freset - Check the required reset for child devices |
595 | * @parent: parent device | |
596 | * @freset: return value | |
597 | * | |
598 | * Each device might have its preferred reset type: fundamental or | |
599 | * hot reset. The routine is used to collect the information from | |
600 | * the child devices so that they could be reset accordingly. | |
6dee3fb9 | 601 | */ |
cb3bc9d0 GS |
602 | void __eeh_set_pe_freset(struct device_node *parent, unsigned int *freset) |
603 | { | |
604 | struct device_node *dn; | |
605 | ||
606 | for_each_child_of_node(parent, dn) { | |
f631acd3 GS |
607 | if (of_node_to_eeh_dev(dn)) { |
608 | struct pci_dev *dev = of_node_to_eeh_dev(dn)->pdev; | |
cb3bc9d0 GS |
609 | |
610 | if (dev && dev->driver) | |
611 | *freset |= dev->needs_freset; | |
612 | ||
613 | __eeh_set_pe_freset(dn, freset); | |
614 | } | |
615 | } | |
616 | } | |
617 | ||
618 | /** | |
619 | * eeh_set_pe_freset - Check the required reset for the indicated device and its children | |
620 | * @dn: parent device | |
621 | * @freset: return value | |
622 | * | |
623 | * Each device might have its preferred reset type: fundamental or | |
624 | * hot reset. The routine is used to collected the information for | |
625 | * the indicated device and its children so that the bunch of the | |
626 | * devices could be reset properly. | |
627 | */ | |
628 | void eeh_set_pe_freset(struct device_node *dn, unsigned int *freset) | |
629 | { | |
630 | struct pci_dev *dev; | |
cce4b2d2 | 631 | dn = eeh_find_device_pe(dn); |
cb3bc9d0 GS |
632 | |
633 | /* Back up one, since config addrs might be shared */ | |
f631acd3 | 634 | if (!pcibios_find_pci_bus(dn) && of_node_to_eeh_dev(dn->parent)) |
cb3bc9d0 | 635 | dn = dn->parent; |
6dee3fb9 | 636 | |
f631acd3 | 637 | dev = of_node_to_eeh_dev(dn)->pdev; |
cb3bc9d0 GS |
638 | if (dev) |
639 | *freset |= dev->needs_freset; | |
640 | ||
641 | __eeh_set_pe_freset(dn, freset); | |
642 | } | |
643 | ||
644 | /** | |
cce4b2d2 | 645 | * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second |
f631acd3 | 646 | * @edev: pci device node to be reset. |
cb3bc9d0 GS |
647 | * |
648 | * Assert the PCI #RST line for 1/4 second. | |
649 | */ | |
f631acd3 | 650 | static void eeh_reset_pe_once(struct eeh_dev *edev) |
6dee3fb9 | 651 | { |
308fc4f8 | 652 | unsigned int freset = 0; |
f631acd3 | 653 | struct device_node *dn = eeh_dev_to_of_node(edev); |
6e19314c | 654 | |
308fc4f8 RL |
655 | /* Determine type of EEH reset required for |
656 | * Partitionable Endpoint, a hot-reset (1) | |
657 | * or a fundamental reset (3). | |
658 | * A fundamental reset required by any device under | |
659 | * Partitionable Endpoint trumps hot-reset. | |
660 | */ | |
f631acd3 | 661 | eeh_set_pe_freset(dn, &freset); |
308fc4f8 RL |
662 | |
663 | if (freset) | |
f631acd3 | 664 | eeh_ops->reset(dn, EEH_RESET_FUNDAMENTAL); |
6e19314c | 665 | else |
f631acd3 | 666 | eeh_ops->reset(dn, EEH_RESET_HOT); |
6dee3fb9 LV |
667 | |
668 | /* The PCI bus requires that the reset be held high for at least | |
cb3bc9d0 GS |
669 | * a 100 milliseconds. We wait a bit longer 'just in case'. |
670 | */ | |
6dee3fb9 | 671 | #define PCI_BUS_RST_HOLD_TIME_MSEC 250 |
cb3bc9d0 | 672 | msleep(PCI_BUS_RST_HOLD_TIME_MSEC); |
d9564ad1 LV |
673 | |
674 | /* We might get hit with another EEH freeze as soon as the | |
675 | * pci slot reset line is dropped. Make sure we don't miss | |
cb3bc9d0 GS |
676 | * these, and clear the flag now. |
677 | */ | |
f631acd3 | 678 | eeh_clear_slot(dn, EEH_MODE_ISOLATED); |
d9564ad1 | 679 | |
f631acd3 | 680 | eeh_ops->reset(dn, EEH_RESET_DEACTIVATE); |
6dee3fb9 LV |
681 | |
682 | /* After a PCI slot has been reset, the PCI Express spec requires | |
683 | * a 1.5 second idle time for the bus to stabilize, before starting | |
cb3bc9d0 GS |
684 | * up traffic. |
685 | */ | |
6dee3fb9 | 686 | #define PCI_BUS_SETTLE_TIME_MSEC 1800 |
cb3bc9d0 | 687 | msleep(PCI_BUS_SETTLE_TIME_MSEC); |
e1029263 LV |
688 | } |
689 | ||
cb3bc9d0 | 690 | /** |
cce4b2d2 | 691 | * eeh_reset_pe - Reset the indicated PE |
f631acd3 | 692 | * @edev: PCI device associated EEH device |
cb3bc9d0 GS |
693 | * |
694 | * This routine should be called to reset indicated device, including | |
695 | * PE. A PE might include multiple PCI devices and sometimes PCI bridges | |
696 | * might be involved as well. | |
697 | */ | |
f631acd3 | 698 | int eeh_reset_pe(struct eeh_dev *edev) |
e1029263 LV |
699 | { |
700 | int i, rc; | |
f631acd3 | 701 | struct device_node *dn = eeh_dev_to_of_node(edev); |
e1029263 | 702 | |
9c547768 LV |
703 | /* Take three shots at resetting the bus */ |
704 | for (i=0; i<3; i++) { | |
f631acd3 | 705 | eeh_reset_pe_once(edev); |
6dee3fb9 | 706 | |
f631acd3 | 707 | rc = eeh_ops->wait_state(dn, PCI_BUS_RESET_WAIT_MSEC); |
eb594a47 | 708 | if (rc == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) |
b6495c0c | 709 | return 0; |
e1029263 | 710 | |
e1029263 | 711 | if (rc < 0) { |
12588da7 | 712 | printk(KERN_ERR "EEH: unrecoverable slot failure %s\n", |
f631acd3 | 713 | dn->full_name); |
b6495c0c | 714 | return -1; |
e1029263 | 715 | } |
12588da7 | 716 | printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n", |
f631acd3 | 717 | i+1, dn->full_name, rc); |
6dee3fb9 | 718 | } |
b6495c0c | 719 | |
9c547768 | 720 | return -1; |
6dee3fb9 LV |
721 | } |
722 | ||
8b553f32 LV |
723 | /** Save and restore of PCI BARs |
724 | * | |
725 | * Although firmware will set up BARs during boot, it doesn't | |
726 | * set up device BAR's after a device reset, although it will, | |
727 | * if requested, set up bridge configuration. Thus, we need to | |
728 | * configure the PCI devices ourselves. | |
729 | */ | |
730 | ||
731 | /** | |
cce4b2d2 | 732 | * eeh_restore_one_device_bars - Restore the Base Address Registers for one device |
f631acd3 | 733 | * @edev: PCI device associated EEH device |
cb5b5624 | 734 | * |
8b553f32 LV |
735 | * Loads the PCI configuration space base address registers, |
736 | * the expansion ROM base address, the latency timer, and etc. | |
737 | * from the saved values in the device node. | |
738 | */ | |
f631acd3 | 739 | static inline void eeh_restore_one_device_bars(struct eeh_dev *edev) |
8b553f32 LV |
740 | { |
741 | int i; | |
cde274c0 | 742 | u32 cmd; |
f631acd3 GS |
743 | struct device_node *dn = eeh_dev_to_of_node(edev); |
744 | ||
745 | if (!edev->phb) | |
746 | return; | |
8b553f32 | 747 | |
8b553f32 | 748 | for (i=4; i<10; i++) { |
f631acd3 | 749 | rtas_write_config(PCI_DN(dn), i*4, 4, edev->config_space[i]); |
8b553f32 LV |
750 | } |
751 | ||
752 | /* 12 == Expansion ROM Address */ | |
f631acd3 | 753 | rtas_write_config(PCI_DN(dn), 12*4, 4, edev->config_space[12]); |
8b553f32 LV |
754 | |
755 | #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) | |
f631acd3 | 756 | #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)]) |
8b553f32 | 757 | |
f631acd3 | 758 | rtas_write_config(PCI_DN(dn), PCI_CACHE_LINE_SIZE, 1, |
8b553f32 LV |
759 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); |
760 | ||
f631acd3 | 761 | rtas_write_config(PCI_DN(dn), PCI_LATENCY_TIMER, 1, |
8b553f32 LV |
762 | SAVED_BYTE(PCI_LATENCY_TIMER)); |
763 | ||
764 | /* max latency, min grant, interrupt pin and line */ | |
f631acd3 | 765 | rtas_write_config(PCI_DN(dn), 15*4, 4, edev->config_space[15]); |
cde274c0 MM |
766 | |
767 | /* Restore PERR & SERR bits, some devices require it, | |
cb3bc9d0 GS |
768 | * don't touch the other command bits |
769 | */ | |
f631acd3 GS |
770 | rtas_read_config(PCI_DN(dn), PCI_COMMAND, 4, &cmd); |
771 | if (edev->config_space[1] & PCI_COMMAND_PARITY) | |
cde274c0 MM |
772 | cmd |= PCI_COMMAND_PARITY; |
773 | else | |
774 | cmd &= ~PCI_COMMAND_PARITY; | |
f631acd3 | 775 | if (edev->config_space[1] & PCI_COMMAND_SERR) |
cde274c0 MM |
776 | cmd |= PCI_COMMAND_SERR; |
777 | else | |
778 | cmd &= ~PCI_COMMAND_SERR; | |
f631acd3 | 779 | rtas_write_config(PCI_DN(dn), PCI_COMMAND, 4, cmd); |
8b553f32 LV |
780 | } |
781 | ||
782 | /** | |
cb3bc9d0 | 783 | * eeh_restore_bars - Restore the PCI config space info |
f631acd3 | 784 | * @edev: EEH device |
8b553f32 LV |
785 | * |
786 | * This routine performs a recursive walk to the children | |
787 | * of this device as well. | |
788 | */ | |
f631acd3 | 789 | void eeh_restore_bars(struct eeh_dev *edev) |
8b553f32 LV |
790 | { |
791 | struct device_node *dn; | |
f631acd3 | 792 | if (!edev) |
8b553f32 LV |
793 | return; |
794 | ||
f631acd3 GS |
795 | if ((edev->mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(edev->class_code)) |
796 | eeh_restore_one_device_bars(edev); | |
8b553f32 | 797 | |
f631acd3 GS |
798 | for_each_child_of_node(eeh_dev_to_of_node(edev), dn) |
799 | eeh_restore_bars(of_node_to_eeh_dev(dn)); | |
8b553f32 LV |
800 | } |
801 | ||
802 | /** | |
cb3bc9d0 | 803 | * eeh_save_bars - Save device bars |
f631acd3 | 804 | * @edev: PCI device associated EEH device |
8b553f32 LV |
805 | * |
806 | * Save the values of the device bars. Unlike the restore | |
807 | * routine, this routine is *not* recursive. This is because | |
31116f0b | 808 | * PCI devices are added individually; but, for the restore, |
8b553f32 LV |
809 | * an entire slot is reset at a time. |
810 | */ | |
f631acd3 | 811 | static void eeh_save_bars(struct eeh_dev *edev) |
8b553f32 LV |
812 | { |
813 | int i; | |
f631acd3 | 814 | struct device_node *dn; |
8b553f32 | 815 | |
f631acd3 | 816 | if (!edev) |
8b553f32 | 817 | return; |
f631acd3 | 818 | dn = eeh_dev_to_of_node(edev); |
8b553f32 LV |
819 | |
820 | for (i = 0; i < 16; i++) | |
f631acd3 | 821 | rtas_read_config(PCI_DN(dn), i * 4, 4, &edev->config_space[i]); |
8b553f32 LV |
822 | } |
823 | ||
cb3bc9d0 | 824 | /** |
cce4b2d2 | 825 | * eeh_early_enable - Early enable EEH on the indicated device |
cb3bc9d0 GS |
826 | * @dn: device node |
827 | * @data: BUID | |
828 | * | |
829 | * Enable EEH functionality on the specified PCI device. The function | |
830 | * is expected to be called before real PCI probing is done. However, | |
831 | * the PHBs have been initialized at this point. | |
832 | */ | |
cce4b2d2 | 833 | static void *eeh_early_enable(struct device_node *dn, void *data) |
1da177e4 | 834 | { |
1da177e4 | 835 | int ret; |
e2eb6392 SR |
836 | const u32 *class_code = of_get_property(dn, "class-code", NULL); |
837 | const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL); | |
838 | const u32 *device_id = of_get_property(dn, "device-id", NULL); | |
954a46e2 | 839 | const u32 *regs; |
1da177e4 | 840 | int enable; |
f631acd3 | 841 | struct eeh_dev *edev = of_node_to_eeh_dev(dn); |
1da177e4 | 842 | |
f631acd3 GS |
843 | edev->class_code = 0; |
844 | edev->mode = 0; | |
845 | edev->check_count = 0; | |
846 | edev->freeze_count = 0; | |
847 | edev->false_positives = 0; | |
1da177e4 | 848 | |
c6d4d5a8 NL |
849 | if (!of_device_is_available(dn)) |
850 | return NULL; | |
1da177e4 LT |
851 | |
852 | /* Ignore bad nodes. */ | |
853 | if (!class_code || !vendor_id || !device_id) | |
854 | return NULL; | |
855 | ||
856 | /* There is nothing to check on PCI to ISA bridges */ | |
857 | if (dn->type && !strcmp(dn->type, "isa")) { | |
f631acd3 | 858 | edev->mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
859 | return NULL; |
860 | } | |
f631acd3 | 861 | edev->class_code = *class_code; |
1da177e4 | 862 | |
1da177e4 | 863 | /* Ok... see if this device supports EEH. Some do, some don't, |
cb3bc9d0 GS |
864 | * and the only way to find out is to check each and every one. |
865 | */ | |
e2eb6392 | 866 | regs = of_get_property(dn, "reg", NULL); |
1da177e4 LT |
867 | if (regs) { |
868 | /* First register entry is addr (00BBSS00) */ | |
869 | /* Try to enable eeh */ | |
8fb8f709 | 870 | ret = eeh_ops->set_option(dn, EEH_OPT_ENABLE); |
172ca926 | 871 | |
25c4a46f | 872 | enable = 0; |
1da177e4 | 873 | if (ret == 0) { |
f631acd3 | 874 | edev->config_addr = regs[0]; |
25e591f6 LV |
875 | |
876 | /* If the newer, better, ibm,get-config-addr-info is supported, | |
cb3bc9d0 GS |
877 | * then use that instead. |
878 | */ | |
f631acd3 | 879 | edev->pe_config_addr = eeh_ops->get_pe_addr(dn); |
25c4a46f LV |
880 | |
881 | /* Some older systems (Power4) allow the | |
882 | * ibm,set-eeh-option call to succeed even on nodes | |
883 | * where EEH is not supported. Verify support | |
cb3bc9d0 GS |
884 | * explicitly. |
885 | */ | |
f631acd3 | 886 | ret = eeh_ops->get_state(dn, NULL); |
eb594a47 | 887 | if (ret > 0 && ret != EEH_STATE_NOT_SUPPORT) |
25c4a46f LV |
888 | enable = 1; |
889 | } | |
890 | ||
891 | if (enable) { | |
892 | eeh_subsystem_enabled = 1; | |
f631acd3 | 893 | edev->mode |= EEH_MODE_SUPPORTED; |
25c4a46f | 894 | |
57b066ff | 895 | pr_debug("EEH: %s: eeh enabled, config=%x pe_config=%x\n", |
f631acd3 GS |
896 | dn->full_name, edev->config_addr, |
897 | edev->pe_config_addr); | |
1da177e4 LT |
898 | } else { |
899 | ||
900 | /* This device doesn't support EEH, but it may have an | |
cb3bc9d0 GS |
901 | * EEH parent, in which case we mark it as supported. |
902 | */ | |
f631acd3 GS |
903 | if (dn->parent && of_node_to_eeh_dev(dn->parent) && |
904 | (of_node_to_eeh_dev(dn->parent)->mode & EEH_MODE_SUPPORTED)) { | |
1da177e4 | 905 | /* Parent supports EEH. */ |
f631acd3 GS |
906 | edev->mode |= EEH_MODE_SUPPORTED; |
907 | edev->config_addr = of_node_to_eeh_dev(dn->parent)->config_addr; | |
1da177e4 LT |
908 | return NULL; |
909 | } | |
910 | } | |
911 | } else { | |
912 | printk(KERN_WARNING "EEH: %s: unable to get reg property.\n", | |
913 | dn->full_name); | |
914 | } | |
915 | ||
f631acd3 | 916 | eeh_save_bars(edev); |
69376502 | 917 | return NULL; |
1da177e4 LT |
918 | } |
919 | ||
aa1e6374 GS |
920 | /** |
921 | * eeh_ops_register - Register platform dependent EEH operations | |
922 | * @ops: platform dependent EEH operations | |
923 | * | |
924 | * Register the platform dependent EEH operation callback | |
925 | * functions. The platform should call this function before | |
926 | * any other EEH operations. | |
927 | */ | |
928 | int __init eeh_ops_register(struct eeh_ops *ops) | |
929 | { | |
930 | if (!ops->name) { | |
931 | pr_warning("%s: Invalid EEH ops name for %p\n", | |
932 | __func__, ops); | |
933 | return -EINVAL; | |
934 | } | |
935 | ||
936 | if (eeh_ops && eeh_ops != ops) { | |
937 | pr_warning("%s: EEH ops of platform %s already existing (%s)\n", | |
938 | __func__, eeh_ops->name, ops->name); | |
939 | return -EEXIST; | |
940 | } | |
941 | ||
942 | eeh_ops = ops; | |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
947 | /** | |
948 | * eeh_ops_unregister - Unreigster platform dependent EEH operations | |
949 | * @name: name of EEH platform operations | |
950 | * | |
951 | * Unregister the platform dependent EEH operation callback | |
952 | * functions. | |
953 | */ | |
954 | int __exit eeh_ops_unregister(const char *name) | |
955 | { | |
956 | if (!name || !strlen(name)) { | |
957 | pr_warning("%s: Invalid EEH ops name\n", | |
958 | __func__); | |
959 | return -EINVAL; | |
960 | } | |
961 | ||
962 | if (eeh_ops && !strcmp(eeh_ops->name, name)) { | |
963 | eeh_ops = NULL; | |
964 | return 0; | |
965 | } | |
966 | ||
967 | return -EEXIST; | |
968 | } | |
969 | ||
cb3bc9d0 GS |
970 | /** |
971 | * eeh_init - EEH initialization | |
972 | * | |
1da177e4 LT |
973 | * Initialize EEH by trying to enable it for all of the adapters in the system. |
974 | * As a side effect we can determine here if eeh is supported at all. | |
975 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
976 | * check. If a user turns off EEH for a particular adapter they are really | |
977 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
978 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
979 | * EEH for all slots/all devices. | |
980 | * | |
981 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
982 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
983 | * newer systems can boot. | |
984 | */ | |
985 | void __init eeh_init(void) | |
986 | { | |
987 | struct device_node *phb, *np; | |
e2af155c GS |
988 | int ret; |
989 | ||
990 | /* call platform initialization function */ | |
991 | if (!eeh_ops) { | |
992 | pr_warning("%s: Platform EEH operation not found\n", | |
993 | __func__); | |
994 | return; | |
995 | } else if ((ret = eeh_ops->init())) { | |
996 | pr_warning("%s: Failed to call platform init function (%d)\n", | |
997 | __func__, ret); | |
998 | return; | |
999 | } | |
1da177e4 | 1000 | |
3d372628 | 1001 | raw_spin_lock_init(&confirm_error_lock); |
df7242b1 | 1002 | |
1da177e4 LT |
1003 | np = of_find_node_by_path("/rtas"); |
1004 | if (np == NULL) | |
1005 | return; | |
1006 | ||
1da177e4 LT |
1007 | /* Enable EEH for all adapters. Note that eeh requires buid's */ |
1008 | for (phb = of_find_node_by_name(NULL, "pci"); phb; | |
1009 | phb = of_find_node_by_name(phb, "pci")) { | |
1010 | unsigned long buid; | |
1011 | ||
1012 | buid = get_phb_buid(phb); | |
f631acd3 | 1013 | if (buid == 0 || !of_node_to_eeh_dev(phb)) |
1da177e4 LT |
1014 | continue; |
1015 | ||
c8c29b38 | 1016 | traverse_pci_devices(phb, eeh_early_enable, NULL); |
1da177e4 LT |
1017 | } |
1018 | ||
1019 | if (eeh_subsystem_enabled) | |
1020 | printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n"); | |
1021 | else | |
1022 | printk(KERN_WARNING "EEH: No capable adapters found\n"); | |
1023 | } | |
1024 | ||
1025 | /** | |
cb3bc9d0 | 1026 | * eeh_add_device_early - Enable EEH for the indicated device_node |
1da177e4 LT |
1027 | * @dn: device node for which to set up EEH |
1028 | * | |
1029 | * This routine must be used to perform EEH initialization for PCI | |
1030 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1031 | * This routine must be called before any i/o is performed to the | |
1032 | * adapter (inluding any config-space i/o). | |
1033 | * Whether this actually enables EEH or not for this device depends | |
1034 | * on the CEC architecture, type of the device, on earlier boot | |
1035 | * command-line arguments & etc. | |
1036 | */ | |
794e085e | 1037 | static void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
1038 | { |
1039 | struct pci_controller *phb; | |
1da177e4 | 1040 | |
f631acd3 | 1041 | if (!dn || !of_node_to_eeh_dev(dn)) |
1da177e4 | 1042 | return; |
f631acd3 | 1043 | phb = of_node_to_eeh_dev(dn)->phb; |
f751f841 LV |
1044 | |
1045 | /* USB Bus children of PCI devices will not have BUID's */ | |
1046 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 1047 | return; |
1da177e4 | 1048 | |
c8c29b38 | 1049 | eeh_early_enable(dn, NULL); |
1da177e4 | 1050 | } |
1da177e4 | 1051 | |
cb3bc9d0 GS |
1052 | /** |
1053 | * eeh_add_device_tree_early - Enable EEH for the indicated device | |
1054 | * @dn: device node | |
1055 | * | |
1056 | * This routine must be used to perform EEH initialization for the | |
1057 | * indicated PCI device that was added after system boot (e.g. | |
1058 | * hotplug, dlpar). | |
1059 | */ | |
e2a296ee LV |
1060 | void eeh_add_device_tree_early(struct device_node *dn) |
1061 | { | |
1062 | struct device_node *sib; | |
acaa6176 SR |
1063 | |
1064 | for_each_child_of_node(dn, sib) | |
e2a296ee LV |
1065 | eeh_add_device_tree_early(sib); |
1066 | eeh_add_device_early(dn); | |
1067 | } | |
1068 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
1069 | ||
1da177e4 | 1070 | /** |
cb3bc9d0 | 1071 | * eeh_add_device_late - Perform EEH initialization for the indicated pci device |
1da177e4 LT |
1072 | * @dev: pci device for which to set up EEH |
1073 | * | |
1074 | * This routine must be used to complete EEH initialization for PCI | |
1075 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1076 | */ | |
794e085e | 1077 | static void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 1078 | { |
56b0fca3 | 1079 | struct device_node *dn; |
f631acd3 | 1080 | struct eeh_dev *edev; |
56b0fca3 | 1081 | |
1da177e4 LT |
1082 | if (!dev || !eeh_subsystem_enabled) |
1083 | return; | |
1084 | ||
57b066ff | 1085 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 1086 | |
56b0fca3 | 1087 | dn = pci_device_to_OF_node(dev); |
f631acd3 GS |
1088 | edev = pci_dev_to_eeh_dev(dev); |
1089 | if (edev->pdev == dev) { | |
57b066ff BH |
1090 | pr_debug("EEH: Already referenced !\n"); |
1091 | return; | |
1092 | } | |
f631acd3 | 1093 | WARN_ON(edev->pdev); |
57b066ff | 1094 | |
cb3bc9d0 | 1095 | pci_dev_get(dev); |
f631acd3 GS |
1096 | edev->pdev = dev; |
1097 | dev->dev.archdata.edev = edev; | |
56b0fca3 | 1098 | |
e1d04c97 LV |
1099 | pci_addr_cache_insert_device(dev); |
1100 | eeh_sysfs_add_device(dev); | |
1da177e4 | 1101 | } |
794e085e | 1102 | |
cb3bc9d0 GS |
1103 | /** |
1104 | * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus | |
1105 | * @bus: PCI bus | |
1106 | * | |
1107 | * This routine must be used to perform EEH initialization for PCI | |
1108 | * devices which are attached to the indicated PCI bus. The PCI bus | |
1109 | * is added after system boot through hotplug or dlpar. | |
1110 | */ | |
794e085e NF |
1111 | void eeh_add_device_tree_late(struct pci_bus *bus) |
1112 | { | |
1113 | struct pci_dev *dev; | |
1114 | ||
1115 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1116 | eeh_add_device_late(dev); | |
1117 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1118 | struct pci_bus *subbus = dev->subordinate; | |
1119 | if (subbus) | |
1120 | eeh_add_device_tree_late(subbus); | |
1121 | } | |
1122 | } | |
1123 | } | |
1124 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 LT |
1125 | |
1126 | /** | |
cb3bc9d0 | 1127 | * eeh_remove_device - Undo EEH setup for the indicated pci device |
1da177e4 LT |
1128 | * @dev: pci device to be removed |
1129 | * | |
794e085e NF |
1130 | * This routine should be called when a device is removed from |
1131 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1132 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1133 | * this device will no longer be detected after this call; thus, | |
1134 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1135 | */ |
794e085e | 1136 | static void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1137 | { |
f631acd3 GS |
1138 | struct eeh_dev *edev; |
1139 | ||
1da177e4 LT |
1140 | if (!dev || !eeh_subsystem_enabled) |
1141 | return; | |
f631acd3 | 1142 | edev = pci_dev_to_eeh_dev(dev); |
1da177e4 LT |
1143 | |
1144 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 1145 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 | 1146 | |
f631acd3 | 1147 | if (!edev || !edev->pdev) { |
57b066ff BH |
1148 | pr_debug("EEH: Not referenced !\n"); |
1149 | return; | |
b055a9e1 | 1150 | } |
f631acd3 GS |
1151 | edev->pdev = NULL; |
1152 | dev->dev.archdata.edev = NULL; | |
cb3bc9d0 | 1153 | pci_dev_put(dev); |
57b066ff BH |
1154 | |
1155 | pci_addr_cache_remove_device(dev); | |
1156 | eeh_sysfs_remove_device(dev); | |
1da177e4 | 1157 | } |
1da177e4 | 1158 | |
cb3bc9d0 GS |
1159 | /** |
1160 | * eeh_remove_bus_device - Undo EEH setup for the indicated PCI device | |
1161 | * @dev: PCI device | |
1162 | * | |
1163 | * This routine must be called when a device is removed from the | |
1164 | * running system through hotplug or dlpar. The corresponding | |
1165 | * PCI address cache will be removed. | |
1166 | */ | |
e2a296ee LV |
1167 | void eeh_remove_bus_device(struct pci_dev *dev) |
1168 | { | |
794e085e NF |
1169 | struct pci_bus *bus = dev->subordinate; |
1170 | struct pci_dev *child, *tmp; | |
1171 | ||
e2a296ee | 1172 | eeh_remove_device(dev); |
794e085e NF |
1173 | |
1174 | if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1175 | list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) | |
1176 | eeh_remove_bus_device(child); | |
e2a296ee LV |
1177 | } |
1178 | } | |
1179 | EXPORT_SYMBOL_GPL(eeh_remove_bus_device); | |
1180 | ||
1da177e4 LT |
1181 | static int proc_eeh_show(struct seq_file *m, void *v) |
1182 | { | |
1da177e4 LT |
1183 | if (0 == eeh_subsystem_enabled) { |
1184 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
e575f8db | 1185 | seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs); |
1da177e4 LT |
1186 | } else { |
1187 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 | 1188 | seq_printf(m, |
e575f8db GS |
1189 | "no device=%llu\n" |
1190 | "no device node=%llu\n" | |
1191 | "no config address=%llu\n" | |
1192 | "check not wanted=%llu\n" | |
1193 | "eeh_total_mmio_ffs=%llu\n" | |
1194 | "eeh_false_positives=%llu\n" | |
1195 | "eeh_slot_resets=%llu\n", | |
1196 | eeh_stats.no_device, | |
1197 | eeh_stats.no_dn, | |
1198 | eeh_stats.no_cfg_addr, | |
1199 | eeh_stats.ignored_check, | |
1200 | eeh_stats.total_mmio_ffs, | |
1201 | eeh_stats.false_positives, | |
1202 | eeh_stats.slot_resets); | |
1da177e4 LT |
1203 | } |
1204 | ||
1205 | return 0; | |
1206 | } | |
1207 | ||
1208 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1209 | { | |
1210 | return single_open(file, proc_eeh_show, NULL); | |
1211 | } | |
1212 | ||
5dfe4c96 | 1213 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1214 | .open = proc_eeh_open, |
1215 | .read = seq_read, | |
1216 | .llseek = seq_lseek, | |
1217 | .release = single_release, | |
1218 | }; | |
1219 | ||
1220 | static int __init eeh_init_proc(void) | |
1221 | { | |
66747138 | 1222 | if (machine_is(pseries)) |
8feaa434 | 1223 | proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations); |
1da177e4 LT |
1224 | return 0; |
1225 | } | |
1226 | __initcall(eeh_init_proc); |