Commit | Line | Data |
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55190f88 BH |
1 | /* |
2 | * SMP support for PowerNV machines. | |
3 | * | |
4 | * Copyright 2011 IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/sched.h> | |
ef8bd77f | 15 | #include <linux/sched/hotplug.h> |
55190f88 BH |
16 | #include <linux/smp.h> |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/cpu.h> | |
22 | ||
23 | #include <asm/irq.h> | |
24 | #include <asm/smp.h> | |
25 | #include <asm/paca.h> | |
26 | #include <asm/machdep.h> | |
27 | #include <asm/cputable.h> | |
28 | #include <asm/firmware.h> | |
55190f88 BH |
29 | #include <asm/vdso_datapage.h> |
30 | #include <asm/cputhreads.h> | |
31 | #include <asm/xics.h> | |
243e2511 | 32 | #include <asm/xive.h> |
14a43e69 | 33 | #include <asm/opal.h> |
f2038911 | 34 | #include <asm/runlatch.h> |
2751b628 | 35 | #include <asm/code-patching.h> |
d4e58e59 | 36 | #include <asm/dbell.h> |
755563bc PM |
37 | #include <asm/kvm_ppc.h> |
38 | #include <asm/ppc-opcode.h> | |
a7cd88da | 39 | #include <asm/cpuidle.h> |
55190f88 BH |
40 | |
41 | #include "powernv.h" | |
42 | ||
344eb010 BH |
43 | #ifdef DEBUG |
44 | #include <asm/udbg.h> | |
45 | #define DBG(fmt...) udbg_printf(fmt) | |
46 | #else | |
47 | #define DBG(fmt...) | |
48 | #endif | |
49 | ||
061d19f2 | 50 | static void pnv_smp_setup_cpu(int cpu) |
55190f88 | 51 | { |
5080332c MN |
52 | /* |
53 | * P9 workaround for CI vector load (see traps.c), | |
54 | * enable the corresponding HMI interrupt | |
55 | */ | |
56 | if (pvr_version_is(PVR_POWER9)) | |
57 | mtspr(SPRN_HMEER, mfspr(SPRN_HMEER) | PPC_BIT(17)); | |
58 | ||
243e2511 BH |
59 | if (xive_enabled()) |
60 | xive_smp_setup_cpu(); | |
61 | else if (cpu != boot_cpuid) | |
55190f88 BH |
62 | xics_setup_cpu(); |
63 | } | |
64 | ||
e51df2c1 | 65 | static int pnv_smp_kick_cpu(int nr) |
14a43e69 | 66 | { |
76d98ab4 | 67 | unsigned int pcpu; |
2751b628 AB |
68 | unsigned long start_here = |
69 | __pa(ppc_function_entry(generic_secondary_smp_init)); | |
14a43e69 | 70 | long rc; |
e4d54f71 | 71 | uint8_t status; |
14a43e69 | 72 | |
c642af9c | 73 | if (nr < 0 || nr >= nr_cpu_ids) |
f8d0d5dc | 74 | return -EINVAL; |
14a43e69 | 75 | |
76d98ab4 | 76 | pcpu = get_hard_smp_processor_id(nr); |
b2b48584 | 77 | /* |
e4d54f71 | 78 | * If we already started or OPAL is not supported, we just |
b2b48584 | 79 | * kick the CPU via the PACA |
14a43e69 | 80 | */ |
e4d54f71 | 81 | if (paca[nr].cpu_start || !firmware_has_feature(FW_FEATURE_OPAL)) |
b2b48584 BH |
82 | goto kick; |
83 | ||
84 | /* | |
85 | * At this point, the CPU can either be spinning on the way in | |
86 | * from kexec or be inside OPAL waiting to be started for the | |
87 | * first time. OPAL v3 allows us to query OPAL to know if it | |
88 | * has the CPUs, so we do that | |
89 | */ | |
e4d54f71 SS |
90 | rc = opal_query_cpu_status(pcpu, &status); |
91 | if (rc != OPAL_SUCCESS) { | |
92 | pr_warn("OPAL Error %ld querying CPU %d state\n", rc, nr); | |
93 | return -ENODEV; | |
94 | } | |
b2b48584 | 95 | |
e4d54f71 SS |
96 | /* |
97 | * Already started, just kick it, probably coming from | |
98 | * kexec and spinning | |
99 | */ | |
100 | if (status == OPAL_THREAD_STARTED) | |
101 | goto kick; | |
b2b48584 | 102 | |
e4d54f71 SS |
103 | /* |
104 | * Available/inactive, let's kick it | |
105 | */ | |
106 | if (status == OPAL_THREAD_INACTIVE) { | |
107 | pr_devel("OPAL: Starting CPU %d (HW 0x%x)...\n", nr, pcpu); | |
108 | rc = opal_start_cpu(pcpu, start_here); | |
109 | if (rc != OPAL_SUCCESS) { | |
110 | pr_warn("OPAL Error %ld starting CPU %d\n", rc, nr); | |
b2b48584 BH |
111 | return -ENODEV; |
112 | } | |
113 | } else { | |
114 | /* | |
e4d54f71 SS |
115 | * An unavailable CPU (or any other unknown status) |
116 | * shouldn't be started. It should also | |
117 | * not be in the possible map but currently it can | |
118 | * happen | |
b2b48584 | 119 | */ |
e4d54f71 SS |
120 | pr_devel("OPAL: CPU %d (HW 0x%x) is unavailable" |
121 | " (status %d)...\n", nr, pcpu, status); | |
122 | return -ENODEV; | |
14a43e69 | 123 | } |
e4d54f71 SS |
124 | |
125 | kick: | |
14a43e69 BH |
126 | return smp_generic_kick_cpu(nr); |
127 | } | |
128 | ||
344eb010 BH |
129 | #ifdef CONFIG_HOTPLUG_CPU |
130 | ||
131 | static int pnv_smp_cpu_disable(void) | |
132 | { | |
133 | int cpu = smp_processor_id(); | |
134 | ||
135 | /* This is identical to pSeries... might consolidate by | |
136 | * moving migrate_irqs_away to a ppc_md with default to | |
137 | * the generic fixup_irqs. --BenH. | |
138 | */ | |
139 | set_cpu_online(cpu, false); | |
140 | vdso_data->processorCount--; | |
141 | if (cpu == boot_cpuid) | |
142 | boot_cpuid = cpumask_any(cpu_online_mask); | |
243e2511 BH |
143 | if (xive_enabled()) |
144 | xive_smp_disable_cpu(); | |
145 | else | |
146 | xics_migrate_irqs_away(); | |
344eb010 BH |
147 | return 0; |
148 | } | |
149 | ||
150 | static void pnv_smp_cpu_kill_self(void) | |
151 | { | |
152 | unsigned int cpu; | |
755563bc | 153 | unsigned long srr1, wmask; |
344eb010 | 154 | |
344eb010 | 155 | /* Standard hot unplug procedure */ |
2525db04 NP |
156 | /* |
157 | * This hard disables local interurpts, ensuring we have no lazy | |
158 | * irqs pending. | |
159 | */ | |
160 | WARN_ON(irqs_disabled()); | |
161 | hard_irq_disable(); | |
162 | WARN_ON(lazy_irq_pending()); | |
163 | ||
344eb010 BH |
164 | idle_task_exit(); |
165 | current->active_mm = NULL; /* for sanity */ | |
166 | cpu = smp_processor_id(); | |
167 | DBG("CPU%d offline\n", cpu); | |
168 | generic_set_cpu_dead(cpu); | |
169 | smp_wmb(); | |
170 | ||
755563bc PM |
171 | wmask = SRR1_WAKEMASK; |
172 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) | |
173 | wmask = SRR1_WAKEMASK_P8; | |
174 | ||
344eb010 | 175 | while (!generic_check_cpu_restart(cpu)) { |
53c656c4 PM |
176 | /* |
177 | * Clear IPI flag, since we don't handle IPIs while | |
178 | * offline, except for those when changing micro-threading | |
179 | * mode, which are handled explicitly below, and those | |
180 | * for coming online, which are handled via | |
181 | * generic_check_cpu_restart() calls. | |
182 | */ | |
183 | kvmppc_set_host_ipi(cpu, 0); | |
77b54e9f | 184 | |
a7cd88da | 185 | srr1 = pnv_cpu_offline(cpu); |
e2186023 | 186 | |
2525db04 NP |
187 | WARN_ON(lazy_irq_pending()); |
188 | ||
56548fc0 PM |
189 | /* |
190 | * If the SRR1 value indicates that we woke up due to | |
191 | * an external interrupt, then clear the interrupt. | |
192 | * We clear the interrupt before checking for the | |
193 | * reason, so as to avoid a race where we wake up for | |
194 | * some other reason, find nothing and clear the interrupt | |
195 | * just as some other cpu is sending us an interrupt. | |
196 | * If we returned from power7_nap as a result of | |
197 | * having finished executing in a KVM guest, then srr1 | |
198 | * contains 0. | |
199 | */ | |
53c656c4 | 200 | if (((srr1 & wmask) == SRR1_WAKEEE) || |
2525db04 | 201 | ((srr1 & wmask) == SRR1_WAKEHVI)) { |
243e2511 BH |
202 | if (cpu_has_feature(CPU_FTR_ARCH_300)) { |
203 | if (xive_enabled()) | |
204 | xive_flush_interrupt(); | |
205 | else | |
206 | icp_opal_flush_interrupt(); | |
207 | } else | |
9b256714 | 208 | icp_native_flush_interrupt(); |
755563bc PM |
209 | } else if ((srr1 & wmask) == SRR1_WAKEHDBELL) { |
210 | unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER); | |
211 | asm volatile(PPC_MSGCLR(%0) : : "r" (msg)); | |
56548fc0 | 212 | } |
53c656c4 | 213 | smp_mb(); |
e2186023 ME |
214 | |
215 | if (cpu_core_split_required()) | |
216 | continue; | |
217 | ||
53c656c4 | 218 | if (srr1 && !generic_check_cpu_restart(cpu)) |
2525db04 NP |
219 | DBG("CPU%d Unexpected exit while offline srr1=%lx!\n", |
220 | cpu, srr1); | |
221 | ||
344eb010 | 222 | } |
9b256714 | 223 | |
344eb010 BH |
224 | DBG("CPU%d coming online...\n", cpu); |
225 | } | |
226 | ||
227 | #endif /* CONFIG_HOTPLUG_CPU */ | |
228 | ||
d70a54e2 GK |
229 | static int pnv_cpu_bootable(unsigned int nr) |
230 | { | |
231 | /* | |
232 | * Starting with POWER8, the subcore logic relies on all threads of a | |
233 | * core being booted so that they can participate in split mode | |
234 | * switches. So on those machines we ignore the smt_enabled_at_boot | |
235 | * setting (smt-enabled on the kernel command line). | |
236 | */ | |
237 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) | |
238 | return 1; | |
239 | ||
240 | return smp_generic_cpu_bootable(nr); | |
241 | } | |
242 | ||
243e2511 BH |
243 | static int pnv_smp_prepare_cpu(int cpu) |
244 | { | |
245 | if (xive_enabled()) | |
246 | return xive_smp_prepare_cpu(cpu); | |
247 | return 0; | |
248 | } | |
249 | ||
45b21cfe ME |
250 | /* Cause IPI as setup by the interrupt controller (xics or xive) */ |
251 | static void (*ic_cause_ipi)(int cpu); | |
252 | ||
b866cc21 NP |
253 | static void pnv_cause_ipi(int cpu) |
254 | { | |
255 | if (doorbell_try_core_ipi(cpu)) | |
256 | return; | |
257 | ||
45b21cfe | 258 | ic_cause_ipi(cpu); |
b866cc21 NP |
259 | } |
260 | ||
6b3edefe NP |
261 | static void pnv_p9_dd1_cause_ipi(int cpu) |
262 | { | |
263 | int this_cpu = get_cpu(); | |
264 | ||
265 | /* | |
266 | * POWER9 DD1 has a global addressed msgsnd, but for now we restrict | |
267 | * IPIs to same core, because it requires additional synchronization | |
268 | * for inter-core doorbells which we do not implement. | |
269 | */ | |
270 | if (cpumask_test_cpu(cpu, cpu_sibling_mask(this_cpu))) | |
271 | doorbell_global_ipi(cpu); | |
272 | else | |
45b21cfe | 273 | ic_cause_ipi(cpu); |
6b3edefe NP |
274 | |
275 | put_cpu(); | |
276 | } | |
277 | ||
243e2511 BH |
278 | static void __init pnv_smp_probe(void) |
279 | { | |
280 | if (xive_enabled()) | |
281 | xive_smp_probe(); | |
282 | else | |
283 | xics_smp_probe(); | |
b866cc21 | 284 | |
6b3edefe | 285 | if (cpu_has_feature(CPU_FTR_DBELL)) { |
45b21cfe ME |
286 | ic_cause_ipi = smp_ops->cause_ipi; |
287 | WARN_ON(!ic_cause_ipi); | |
288 | ||
6b3edefe NP |
289 | if (cpu_has_feature(CPU_FTR_ARCH_300)) { |
290 | if (cpu_has_feature(CPU_FTR_POWER9_DD1)) | |
291 | smp_ops->cause_ipi = pnv_p9_dd1_cause_ipi; | |
292 | else | |
293 | smp_ops->cause_ipi = doorbell_global_ipi; | |
294 | } else { | |
295 | smp_ops->cause_ipi = pnv_cause_ipi; | |
296 | } | |
b866cc21 | 297 | } |
243e2511 BH |
298 | } |
299 | ||
e36d0a2e NP |
300 | static int pnv_system_reset_exception(struct pt_regs *regs) |
301 | { | |
302 | if (smp_handle_nmi_ipi(regs)) | |
303 | return 1; | |
304 | return 0; | |
305 | } | |
306 | ||
307 | static int pnv_cause_nmi_ipi(int cpu) | |
308 | { | |
309 | int64_t rc; | |
310 | ||
311 | if (cpu >= 0) { | |
312 | rc = opal_signal_system_reset(get_hard_smp_processor_id(cpu)); | |
313 | if (rc != OPAL_SUCCESS) | |
314 | return 0; | |
315 | return 1; | |
316 | ||
317 | } else if (cpu == NMI_IPI_ALL_OTHERS) { | |
318 | bool success = true; | |
319 | int c; | |
320 | ||
321 | ||
322 | /* | |
323 | * We do not use broadcasts (yet), because it's not clear | |
324 | * exactly what semantics Linux wants or the firmware should | |
325 | * provide. | |
326 | */ | |
327 | for_each_online_cpu(c) { | |
328 | if (c == smp_processor_id()) | |
329 | continue; | |
330 | ||
331 | rc = opal_signal_system_reset( | |
332 | get_hard_smp_processor_id(c)); | |
333 | if (rc != OPAL_SUCCESS) | |
334 | success = false; | |
335 | } | |
336 | if (success) | |
337 | return 1; | |
338 | ||
339 | /* | |
340 | * Caller will fall back to doorbells, which may pick | |
341 | * up the remainders. | |
342 | */ | |
343 | } | |
344 | ||
345 | return 0; | |
346 | } | |
347 | ||
55190f88 | 348 | static struct smp_ops_t pnv_smp_ops = { |
b866cc21 NP |
349 | .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */ |
350 | .cause_ipi = NULL, /* Filled at runtime by pnv_smp_probe() */ | |
c64af645 | 351 | .cause_nmi_ipi = NULL, |
243e2511 BH |
352 | .probe = pnv_smp_probe, |
353 | .prepare_cpu = pnv_smp_prepare_cpu, | |
14a43e69 | 354 | .kick_cpu = pnv_smp_kick_cpu, |
55190f88 | 355 | .setup_cpu = pnv_smp_setup_cpu, |
d70a54e2 | 356 | .cpu_bootable = pnv_cpu_bootable, |
344eb010 BH |
357 | #ifdef CONFIG_HOTPLUG_CPU |
358 | .cpu_disable = pnv_smp_cpu_disable, | |
359 | .cpu_die = generic_cpu_die, | |
360 | #endif /* CONFIG_HOTPLUG_CPU */ | |
55190f88 BH |
361 | }; |
362 | ||
363 | /* This is called very early during platform setup_arch */ | |
364 | void __init pnv_smp_init(void) | |
365 | { | |
e36d0a2e NP |
366 | if (opal_check_token(OPAL_SIGNAL_SYSTEM_RESET)) { |
367 | ppc_md.system_reset_exception = pnv_system_reset_exception; | |
368 | pnv_smp_ops.cause_nmi_ipi = pnv_cause_nmi_ipi; | |
369 | } | |
55190f88 BH |
370 | smp_ops = &pnv_smp_ops; |
371 | ||
344eb010 BH |
372 | #ifdef CONFIG_HOTPLUG_CPU |
373 | ppc_md.cpu_die = pnv_smp_cpu_kill_self; | |
374 | #endif | |
55190f88 | 375 | } |