[linux-2.6-block.git] / arch / powerpc / platforms / powernv / pci.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __POWERNV_PCI_H
#define __POWERNV_PCI_H

#include <linux/compiler.h>		/* for __printf */
#include <linux/iommu.h>
#include <asm/iommu.h>
#include <asm/msi_bitmap.h>

struct pci_dn;

enum pnv_phb_type {
	PNV_PHB_IODA1		= 0,
	PNV_PHB_IODA2		= 1,
	PNV_PHB_NPU_NVLINK	= 2,
	PNV_PHB_NPU_OCAPI	= 3,
};

/* Precise PHB model for error management */
enum pnv_phb_model {
	PNV_PHB_MODEL_UNKNOWN,
	PNV_PHB_MODEL_P7IOC,
	PNV_PHB_MODEL_PHB3,
	PNV_PHB_MODEL_NPU,
	PNV_PHB_MODEL_NPU2,
};

#define PNV_PCI_DIAG_BUF_SIZE	8192
#define PNV_IODA_PE_DEV		(1 << 0)	/* PE has single PCI device	*/
#define PNV_IODA_PE_BUS		(1 << 1)	/* PE has primary PCI bus	*/
#define PNV_IODA_PE_BUS_ALL	(1 << 2)	/* PE has subordinate buses	*/
#define PNV_IODA_PE_MASTER	(1 << 3)	/* Master PE in compound case	*/
#define PNV_IODA_PE_SLAVE	(1 << 4)	/* Slave PE in compound case	*/
#define PNV_IODA_PE_VF		(1 << 5)	/* PE for one VF 		*/

/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
#define PNV_IODA_STOPPED_STATE	0x8000000000000000

/* Data associated with a PE, including IOMMU tracking etc.. */
struct pnv_phb;
struct pnv_ioda_pe {
	unsigned long		flags;
	struct pnv_phb		*phb;
	int			device_count;

	/* A PE can be associated with a single device or an
	 * entire bus (& children). In the former case, pdev
	 * is populated, in the later case, pbus is.
	 */
#ifdef CONFIG_PCI_IOV
	struct pci_dev          *parent_dev;
#endif
	struct pci_dev		*pdev;
	struct pci_bus		*pbus;

	/* Effective RID (device RID for a device PE and base bus
	 * RID with devfn 0 for a bus PE)
	 */
	unsigned int		rid;

	/* PE number */
	unsigned int		pe_number;

	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
	struct iommu_table_group table_group;
	struct npu_comp		*npucomp;

	/* 64-bit TCE bypass region */
	bool			tce_bypass_enabled;
	uint64_t		tce_bypass_base;

	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	 * and -1 if not supported. (It's actually identical to the
	 * PE number)
	 */
	int			mve_number;

	/* PEs in compound case */
	struct pnv_ioda_pe	*master;
	struct list_head	slaves;

	/* Link in list of PE#s */
	struct list_head	list;
};

#define PNV_PHB_FLAG_EEH	(1 << 0)

struct pnv_phb {
	struct pci_controller	*hose;
	enum pnv_phb_type	type;
	enum pnv_phb_model	model;
	u64			hub_id;
	u64			opal_id;
	int			flags;
	void __iomem		*regs;
	u64			regs_phys;
	int			initialized;
	spinlock_t		lock;

#ifdef CONFIG_DEBUG_FS
	int			has_dbgfs;
	struct dentry		*dbgfs;
#endif

	unsigned int		msi_base;
	unsigned int		msi32_support;
	struct msi_bitmap	msi_bmp;
	int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
			 unsigned int hwirq, unsigned int virq,
			 unsigned int is_64, struct msi_msg *msg);
	void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
	int (*init_m64)(struct pnv_phb *phb);
	int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
	void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
	int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);

	struct {
		/* Global bridge info */
		unsigned int		total_pe_num;
		unsigned int		reserved_pe_idx;
		unsigned int		root_pe_idx;
		bool			root_pe_populated;

		/* 32-bit MMIO window */
		unsigned int		m32_size;
		unsigned int		m32_segsize;
		unsigned int		m32_pci_base;

		/* 64-bit MMIO window */
		unsigned int		m64_bar_idx;
		unsigned long		m64_size;
		unsigned long		m64_segsize;
		unsigned long		m64_base;
		unsigned long		m64_bar_alloc;

		/* IO ports */
		unsigned int		io_size;
		unsigned int		io_segsize;
		unsigned int		io_pci_base;

		/* PE allocation */
		struct mutex		pe_alloc_mutex;
		unsigned long		*pe_alloc;
		struct pnv_ioda_pe	*pe_array;

		/* M32 & IO segment maps */
		unsigned int		*m64_segmap;
		unsigned int		*m32_segmap;
		unsigned int		*io_segmap;

		/* DMA32 segment maps - IODA1 only */
		unsigned int		dma32_count;
		unsigned int		*dma32_segmap;

		/* IRQ chip */
		int			irq_chip_init;
		struct irq_chip		irq_chip;

		/* Sorted list of used PE's based
		 * on the sequence of creation
		 */
		struct list_head	pe_list;
		struct mutex            pe_list_mutex;

		/* Reverse map of PEs, indexed by {bus, devfn} */
		unsigned int		pe_rmap[0x10000];
	} ioda;

	/* PHB and hub diagnostics */
	unsigned int		diag_data_size;
	u8			*diag_data;
};

extern struct pci_ops pnv_pci_ops;

void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
				unsigned char *log_buff);
int pnv_pci_cfg_read(struct pci_dn *pdn,
		     int where, int size, u32 *val);
int pnv_pci_cfg_write(struct pci_dn *pdn,
		      int where, int size, u32 val);
extern struct iommu_table *pnv_pci_table_alloc(int nid);

extern void pnv_pci_init_ioda_hub(struct device_node *np);
extern void pnv_pci_init_ioda2_phb(struct device_node *np);
extern void pnv_pci_init_npu_phb(struct device_node *np);
extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr);
extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);

extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
		__u64 window_size, __u32 levels);
extern int pnv_eeh_post_init(void);

__printf(3, 4)
extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
			    const char *fmt, ...);
#define pe_err(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
#define pe_warn(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
#define pe_info(pe, fmt, ...)					\
	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)

/* Nvlink functions */
extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
extern struct iommu_table_group *pnv_try_setup_npu_table_group(
		struct pnv_ioda_pe *pe);
extern struct iommu_table_group *pnv_npu_compound_attach(
		struct pnv_ioda_pe *pe);

/* pci-ioda-tce.c */
#define POWERNV_IOMMU_DEFAULT_LEVELS	1
#define POWERNV_IOMMU_MAX_LEVELS	5

extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
		unsigned long uaddr, enum dma_data_direction direction,
		unsigned long attrs);
extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
		unsigned long *hpa, enum dma_data_direction *direction,
		bool alloc);
extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index,
		bool alloc);
extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);

extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
		__u32 page_shift, __u64 window_size, __u32 levels,
		bool alloc_userspace_copy, struct iommu_table *tbl);
extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);

extern long pnv_pci_link_table_and_group(int node, int num,
		struct iommu_table *tbl,
		struct iommu_table_group *table_group);
extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
		struct iommu_table_group *table_group);
extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
		void *tce_mem, u64 tce_size,
		u64 dma_offset, unsigned int page_shift);

#endif /* __POWERNV_PCI_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
61305a96 BH	2	#ifndef __POWERNV_PCI_H
	3	#define __POWERNV_PCI_H
	4
1e496391	5	#include <linux/compiler.h> /* for __printf */
f456834a IM	6	#include <linux/iommu.h>
	7	#include <asm/iommu.h>
	8	#include <asm/msi_bitmap.h>
	9
61305a96 BH	10	struct pci_dn;
	11
	12	enum pnv_phb_type {
7f2c39e9 FB	13	PNV_PHB_IODA1 = 0,
	14	PNV_PHB_IODA2 = 1,
	15	PNV_PHB_NPU_NVLINK = 2,
	16	PNV_PHB_NPU_OCAPI = 3,
61305a96 BH	17	};
61305a96 BH	18
cee72d5b BH	19	/* Precise PHB model for error management */
	20	enum pnv_phb_model {
	21	PNV_PHB_MODEL_UNKNOWN,
cee72d5b	22	PNV_PHB_MODEL_P7IOC,
aa0c033f	23	PNV_PHB_MODEL_PHB3,
5d2aa710	24	PNV_PHB_MODEL_NPU,
616badd2	25	PNV_PHB_MODEL_NPU2,
cee72d5b BH	26	};
cee72d5b BH	27
5c9d6d75	28	#define PNV_PCI_DIAG_BUF_SIZE 8192
7ebdf956 GS	29	#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
	30	#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
	31	#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
262af557 GC	32	#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
262af557 GC	33	#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
781a868f	34	#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
cee72d5b	35
31bbd45a RC	36	/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
	37	#define PNV_IODA_STOPPED_STATE 0x8000000000000000
	38
184cd4a3	39	/* Data associated with a PE, including IOMMU tracking etc.. */
4cce9550	40	struct pnv_phb;
184cd4a3	41	struct pnv_ioda_pe {
7ebdf956	42	unsigned long flags;
4cce9550	43	struct pnv_phb *phb;
c5f7700b	44	int device_count;
7ebdf956	45
184cd4a3 BH	46	/* A PE can be associated with a single device or an
	47	* entire bus (& children). In the former case, pdev
	48	* is populated, in the later case, pbus is.
	49	*/
781a868f WY	50	#ifdef CONFIG_PCI_IOV
	51	struct pci_dev *parent_dev;
	52	#endif
184cd4a3 BH	53	struct pci_dev *pdev;
	54	struct pci_bus *pbus;
	55
	56	/* Effective RID (device RID for a device PE and base bus
	57	* RID with devfn 0 for a bus PE)
	58	*/
	59	unsigned int rid;
	60
	61	/* PE number */
	62	unsigned int pe_number;
	63
184cd4a3	64	/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
b348aa65	65	struct iommu_table_group table_group;
0bd97167	66	struct npu_comp *npucomp;
184cd4a3	67
cd15b048 BH	68	/* 64-bit TCE bypass region */
	69	bool tce_bypass_enabled;
	70	uint64_t tce_bypass_base;
184cd4a3 BH	71
	72	/* MSIs. MVE index is identical for for 32 and 64 bit MSI
	73	* and -1 if not supported. (It's actually identical to the
	74	* PE number)
	75	*/
	76	int mve_number;
	77
262af557 GC	78	/* PEs in compound case */
	79	struct pnv_ioda_pe *master;
	80	struct list_head slaves;
	81
184cd4a3	82	/* Link in list of PE#s */
7ebdf956	83	struct list_head list;
184cd4a3 BH	84	};
184cd4a3 BH	85
f5bc6b70 GS	86	#define PNV_PHB_FLAG_EEH (1 << 0)
f5bc6b70 GS	87
61305a96 BH	88	struct pnv_phb {
	89	struct pci_controller *hose;
	90	enum pnv_phb_type type;
cee72d5b	91	enum pnv_phb_model model;
8747f363	92	u64 hub_id;
61305a96	93	u64 opal_id;
f5bc6b70	94	int flags;
61305a96	95	void __iomem *regs;
fd141d1a	96	u64 regs_phys;
db1266c8	97	int initialized;
61305a96 BH	98	spinlock_t lock;
61305a96 BH	99
37c367f2	100	#ifdef CONFIG_DEBUG_FS
7f52a526	101	int has_dbgfs;
37c367f2 GS	102	struct dentry *dbgfs;
	103	#endif
	104
c1a2562a	105	unsigned int msi_base;
c1a2562a	106	unsigned int msi32_support;
fb1b55d6	107	struct msi_bitmap msi_bmp;
c1a2562a	108	int (msi_setup)(struct pnv_phb phb, struct pci_dev *dev,
137436c9 GS	109	unsigned int hwirq, unsigned int virq,
137436c9 GS	110	unsigned int is_64, struct msi_msg *msg);
61305a96	111	void (dma_dev_setup)(struct pnv_phb phb, struct pci_dev *pdev);
262af557	112	int (init_m64)(struct pnv_phb phb);
49dec922 GS	113	int (get_pe_state)(struct pnv_phb phb, int pe_no);
	114	void (freeze_pe)(struct pnv_phb phb, int pe_no);
	115	int (unfreeze_pe)(struct pnv_phb phb, int pe_no, int opt);
61305a96	116
2de50e96 RC	117	struct {
2de50e96 RC	118	/* Global bridge info */
92b8f137 GS	119	unsigned int total_pe_num;
92b8f137 GS	120	unsigned int reserved_pe_idx;
63803c39 GS	121	unsigned int root_pe_idx;
63803c39 GS	122	bool root_pe_populated;
2de50e96 RC	123
	124	/* 32-bit MMIO window */
	125	unsigned int m32_size;
	126	unsigned int m32_segsize;
	127	unsigned int m32_pci_base;
	128
	129	/* 64-bit MMIO window */
	130	unsigned int m64_bar_idx;
	131	unsigned long m64_size;
	132	unsigned long m64_segsize;
	133	unsigned long m64_base;
	134	unsigned long m64_bar_alloc;
	135
	136	/* IO ports */
	137	unsigned int io_size;
	138	unsigned int io_segsize;
	139	unsigned int io_pci_base;
	140
13ce7598	141	/* PE allocation */
2de50e96	142	struct mutex pe_alloc_mutex;
13ce7598 GS	143	unsigned long *pe_alloc;
13ce7598 GS	144	struct pnv_ioda_pe *pe_array;
2de50e96 RC	145
2de50e96 RC	146	/* M32 & IO segment maps */
93289d8c	147	unsigned int *m64_segmap;
2de50e96 RC	148	unsigned int *m32_segmap;
2de50e96 RC	149	unsigned int *io_segmap;
2de50e96	150
2b923ed1 GS	151	/* DMA32 segment maps - IODA1 only */
	152	unsigned int dma32_count;
	153	unsigned int *dma32_segmap;
	154
2de50e96 RC	155	/* IRQ chip */
	156	int irq_chip_init;
	157	struct irq_chip irq_chip;
	158
	159	/* Sorted list of used PE's based
	160	* on the sequence of creation
	161	*/
	162	struct list_head pe_list;
	163	struct mutex pe_list_mutex;
	164
c127562a GS	165	/* Reverse map of PEs, indexed by {bus, devfn} */
c127562a GS	166	unsigned int pe_rmap[0x10000];
2de50e96	167	} ioda;
cee72d5b	168
5cb1f8fd RC	169	/* PHB and hub diagnostics */
	170	unsigned int diag_data_size;
	171	u8 *diag_data;
61305a96 BH	172	};
	173
	174	extern struct pci_ops pnv_pci_ops;
	175
93aef2a7 GS	176	void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
93aef2a7 GS	177	unsigned char *log_buff);
3532a741	178	int pnv_pci_cfg_read(struct pci_dn *pdn,
9bf41be6	179	int where, int size, u32 *val);
3532a741	180	int pnv_pci_cfg_write(struct pci_dn *pdn,
9bf41be6	181	int where, int size, u32 val);
0eaf4def AK	182	extern struct iommu_table *pnv_pci_table_alloc(int nid);
0eaf4def AK	183
184cd4a3	184	extern void pnv_pci_init_ioda_hub(struct device_node *np);
aa0c033f	185	extern void pnv_pci_init_ioda2_phb(struct device_node *np);
5d2aa710	186	extern void pnv_pci_init_npu_phb(struct device_node *np);
7f2c39e9	187	extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
0e759bd7	188	extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr);
d92a208d	189	extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
cadf364d	190	extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
73ed148a	191
92ae0353	192	extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
1bc74f1c	193	extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
92ae0353 DA	194	extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
92ae0353 DA	195	extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
f456834a IM	196	extern struct pnv_ioda_pe pnv_ioda_get_pe(struct pci_dev dev);
f456834a IM	197	extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
25529100	198	extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
0bd97167 AK	199	extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
0bd97167 AK	200	__u64 window_size, __u32 levels);
b9fde58d	201	extern int pnv_eeh_post_init(void);
92ae0353	202
1e496391	203	__printf(3, 4)
7d623e42 AK	204	extern void pe_level_printk(const struct pnv_ioda_pe pe, const char level,
	205	const char *fmt, ...);
	206	#define pe_err(pe, fmt, ...) \
	207	pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
	208	#define pe_warn(pe, fmt, ...) \
	209	pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
	210	#define pe_info(pe, fmt, ...) \
	211	pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
	212
5d2aa710	213	/* Nvlink functions */
f9f83456	214	extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
6b3d12a9	215	extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
b5cb9ab1	216	extern struct pnv_ioda_pe pnv_pci_npu_setup_iommu(struct pnv_ioda_pe npe);
0bd97167 AK	217	extern struct iommu_table_group *pnv_try_setup_npu_table_group(
	218	struct pnv_ioda_pe *pe);
	219	extern struct iommu_table_group *pnv_npu_compound_attach(
	220	struct pnv_ioda_pe *pe);
4361b034	221
191c2287 AK	222	/* pci-ioda-tce.c */
	223	#define POWERNV_IOMMU_DEFAULT_LEVELS 1
	224	#define POWERNV_IOMMU_MAX_LEVELS 5
	225
	226	extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
	227	unsigned long uaddr, enum dma_data_direction direction,
	228	unsigned long attrs);
	229	extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
	230	extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
a68bd126 AK	231	unsigned long hpa, enum dma_data_direction direction,
	232	bool alloc);
	233	extern __be64 pnv_tce_useraddrptr(struct iommu_table tbl, long index,
	234	bool alloc);
191c2287 AK	235	extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
	236
	237	extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
	238	__u32 page_shift, __u64 window_size, __u32 levels,
090bad39	239	bool alloc_userspace_copy, struct iommu_table *tbl);
191c2287 AK	240	extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
	241
	242	extern long pnv_pci_link_table_and_group(int node, int num,
	243	struct iommu_table *tbl,
	244	struct iommu_table_group *table_group);
	245	extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
	246	struct iommu_table_group *table_group);
	247	extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
	248	void *tce_mem, u64 tce_size,
	249	u64 dma_offset, unsigned int page_shift);
	250
61305a96	251	#endif /* __POWERNV_PCI_H */