Commit | Line | Data |
---|---|---|
184cd4a3 BH |
1 | /* |
2 | * Support PCI/PCIe on PowerNV platforms | |
3 | * | |
4 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
cee72d5b | 12 | #undef DEBUG |
184cd4a3 BH |
13 | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/pci.h> | |
361f2a2a | 16 | #include <linux/crash_dump.h> |
37c367f2 | 17 | #include <linux/debugfs.h> |
184cd4a3 BH |
18 | #include <linux/delay.h> |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/msi.h> | |
cd15b048 | 25 | #include <linux/memblock.h> |
ac9a5889 | 26 | #include <linux/iommu.h> |
e57080f1 | 27 | #include <linux/rculist.h> |
4793d65d | 28 | #include <linux/sizes.h> |
184cd4a3 BH |
29 | |
30 | #include <asm/sections.h> | |
31 | #include <asm/io.h> | |
32 | #include <asm/prom.h> | |
33 | #include <asm/pci-bridge.h> | |
34 | #include <asm/machdep.h> | |
fb1b55d6 | 35 | #include <asm/msi_bitmap.h> |
184cd4a3 BH |
36 | #include <asm/ppc-pci.h> |
37 | #include <asm/opal.h> | |
38 | #include <asm/iommu.h> | |
39 | #include <asm/tce.h> | |
137436c9 | 40 | #include <asm/xics.h> |
37c367f2 | 41 | #include <asm/debug.h> |
262af557 | 42 | #include <asm/firmware.h> |
80c49c7e | 43 | #include <asm/pnv-pci.h> |
aca6913f | 44 | #include <asm/mmzone.h> |
80c49c7e | 45 | |
ec249dd8 | 46 | #include <misc/cxl-base.h> |
184cd4a3 BH |
47 | |
48 | #include "powernv.h" | |
49 | #include "pci.h" | |
50 | ||
99451551 GS |
51 | #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ |
52 | #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ | |
acce971c | 53 | #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 |
781a868f | 54 | |
bbb845c4 AK |
55 | #define POWERNV_IOMMU_DEFAULT_LEVELS 1 |
56 | #define POWERNV_IOMMU_MAX_LEVELS 5 | |
57 | ||
aca6913f AK |
58 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); |
59 | ||
6d31c2fa JP |
60 | static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, |
61 | const char *fmt, ...) | |
62 | { | |
63 | struct va_format vaf; | |
64 | va_list args; | |
65 | char pfix[32]; | |
66 | ||
67 | va_start(args, fmt); | |
68 | ||
69 | vaf.fmt = fmt; | |
70 | vaf.va = &args; | |
71 | ||
781a868f | 72 | if (pe->flags & PNV_IODA_PE_DEV) |
6d31c2fa | 73 | strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); |
781a868f | 74 | else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
6d31c2fa JP |
75 | sprintf(pfix, "%04x:%02x ", |
76 | pci_domain_nr(pe->pbus), pe->pbus->number); | |
781a868f WY |
77 | #ifdef CONFIG_PCI_IOV |
78 | else if (pe->flags & PNV_IODA_PE_VF) | |
79 | sprintf(pfix, "%04x:%02x:%2x.%d", | |
80 | pci_domain_nr(pe->parent_dev->bus), | |
81 | (pe->rid & 0xff00) >> 8, | |
82 | PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); | |
83 | #endif /* CONFIG_PCI_IOV*/ | |
6d31c2fa JP |
84 | |
85 | printk("%spci %s: [PE# %.3d] %pV", | |
86 | level, pfix, pe->pe_number, &vaf); | |
87 | ||
88 | va_end(args); | |
89 | } | |
184cd4a3 | 90 | |
6d31c2fa JP |
91 | #define pe_err(pe, fmt, ...) \ |
92 | pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__) | |
93 | #define pe_warn(pe, fmt, ...) \ | |
94 | pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__) | |
95 | #define pe_info(pe, fmt, ...) \ | |
96 | pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__) | |
184cd4a3 | 97 | |
4e287840 TLSC |
98 | static bool pnv_iommu_bypass_disabled __read_mostly; |
99 | ||
100 | static int __init iommu_setup(char *str) | |
101 | { | |
102 | if (!str) | |
103 | return -EINVAL; | |
104 | ||
105 | while (*str) { | |
106 | if (!strncmp(str, "nobypass", 8)) { | |
107 | pnv_iommu_bypass_disabled = true; | |
108 | pr_info("PowerNV: IOMMU bypass window disabled.\n"); | |
109 | break; | |
110 | } | |
111 | str += strcspn(str, ","); | |
112 | if (*str == ',') | |
113 | str++; | |
114 | } | |
115 | ||
116 | return 0; | |
117 | } | |
118 | early_param("iommu", iommu_setup); | |
119 | ||
262af557 GC |
120 | static inline bool pnv_pci_is_mem_pref_64(unsigned long flags) |
121 | { | |
122 | return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) == | |
123 | (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)); | |
124 | } | |
125 | ||
1e916772 GS |
126 | static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) |
127 | { | |
128 | phb->ioda.pe_array[pe_no].phb = phb; | |
129 | phb->ioda.pe_array[pe_no].pe_number = pe_no; | |
130 | ||
131 | return &phb->ioda.pe_array[pe_no]; | |
132 | } | |
133 | ||
4b82ab18 GS |
134 | static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) |
135 | { | |
92b8f137 | 136 | if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { |
4b82ab18 GS |
137 | pr_warn("%s: Invalid PE %d on PHB#%x\n", |
138 | __func__, pe_no, phb->hose->global_number); | |
139 | return; | |
140 | } | |
141 | ||
e9dc4d7f GS |
142 | if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) |
143 | pr_debug("%s: PE %d was reserved on PHB#%x\n", | |
144 | __func__, pe_no, phb->hose->global_number); | |
4b82ab18 | 145 | |
1e916772 | 146 | pnv_ioda_init_pe(phb, pe_no); |
4b82ab18 GS |
147 | } |
148 | ||
1e916772 | 149 | static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) |
184cd4a3 BH |
150 | { |
151 | unsigned long pe; | |
152 | ||
153 | do { | |
154 | pe = find_next_zero_bit(phb->ioda.pe_alloc, | |
92b8f137 GS |
155 | phb->ioda.total_pe_num, 0); |
156 | if (pe >= phb->ioda.total_pe_num) | |
1e916772 | 157 | return NULL; |
184cd4a3 BH |
158 | } while(test_and_set_bit(pe, phb->ioda.pe_alloc)); |
159 | ||
1e916772 | 160 | return pnv_ioda_init_pe(phb, pe); |
184cd4a3 BH |
161 | } |
162 | ||
1e916772 | 163 | static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) |
184cd4a3 | 164 | { |
1e916772 GS |
165 | struct pnv_phb *phb = pe->phb; |
166 | ||
167 | WARN_ON(pe->pdev); | |
184cd4a3 | 168 | |
1e916772 GS |
169 | memset(pe, 0, sizeof(struct pnv_ioda_pe)); |
170 | clear_bit(pe->pe_number, phb->ioda.pe_alloc); | |
184cd4a3 BH |
171 | } |
172 | ||
262af557 GC |
173 | /* The default M64 BAR is shared by all PEs */ |
174 | static int pnv_ioda2_init_m64(struct pnv_phb *phb) | |
175 | { | |
176 | const char *desc; | |
177 | struct resource *r; | |
178 | s64 rc; | |
179 | ||
180 | /* Configure the default M64 BAR */ | |
181 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
182 | OPAL_M64_WINDOW_TYPE, | |
183 | phb->ioda.m64_bar_idx, | |
184 | phb->ioda.m64_base, | |
185 | 0, /* unused */ | |
186 | phb->ioda.m64_size); | |
187 | if (rc != OPAL_SUCCESS) { | |
188 | desc = "configuring"; | |
189 | goto fail; | |
190 | } | |
191 | ||
192 | /* Enable the default M64 BAR */ | |
193 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
194 | OPAL_M64_WINDOW_TYPE, | |
195 | phb->ioda.m64_bar_idx, | |
196 | OPAL_ENABLE_M64_SPLIT); | |
197 | if (rc != OPAL_SUCCESS) { | |
198 | desc = "enabling"; | |
199 | goto fail; | |
200 | } | |
201 | ||
202 | /* Mark the M64 BAR assigned */ | |
203 | set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc); | |
204 | ||
205 | /* | |
206 | * Strip off the segment used by the reserved PE, which is | |
207 | * expected to be 0 or last one of PE capabicity. | |
208 | */ | |
209 | r = &phb->hose->mem_resources[1]; | |
92b8f137 | 210 | if (phb->ioda.reserved_pe_idx == 0) |
262af557 | 211 | r->start += phb->ioda.m64_segsize; |
92b8f137 | 212 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) |
262af557 GC |
213 | r->end -= phb->ioda.m64_segsize; |
214 | else | |
215 | pr_warn(" Cannot strip M64 segment for reserved PE#%d\n", | |
92b8f137 | 216 | phb->ioda.reserved_pe_idx); |
262af557 GC |
217 | |
218 | return 0; | |
219 | ||
220 | fail: | |
221 | pr_warn(" Failure %lld %s M64 BAR#%d\n", | |
222 | rc, desc, phb->ioda.m64_bar_idx); | |
223 | opal_pci_phb_mmio_enable(phb->opal_id, | |
224 | OPAL_M64_WINDOW_TYPE, | |
225 | phb->ioda.m64_bar_idx, | |
226 | OPAL_DISABLE_M64); | |
227 | return -EIO; | |
228 | } | |
229 | ||
c430670a | 230 | static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, |
96a2f92b | 231 | unsigned long *pe_bitmap) |
262af557 | 232 | { |
96a2f92b GS |
233 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
234 | struct pnv_phb *phb = hose->private_data; | |
262af557 | 235 | struct resource *r; |
96a2f92b GS |
236 | resource_size_t base, sgsz, start, end; |
237 | int segno, i; | |
238 | ||
239 | base = phb->ioda.m64_base; | |
240 | sgsz = phb->ioda.m64_segsize; | |
241 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
242 | r = &pdev->resource[i]; | |
243 | if (!r->parent || !pnv_pci_is_mem_pref_64(r->flags)) | |
244 | continue; | |
262af557 | 245 | |
96a2f92b GS |
246 | start = _ALIGN_DOWN(r->start - base, sgsz); |
247 | end = _ALIGN_UP(r->end - base, sgsz); | |
248 | for (segno = start / sgsz; segno < end / sgsz; segno++) { | |
249 | if (pe_bitmap) | |
250 | set_bit(segno, pe_bitmap); | |
251 | else | |
252 | pnv_ioda_reserve_pe(phb, segno); | |
262af557 GC |
253 | } |
254 | } | |
255 | } | |
256 | ||
99451551 GS |
257 | static int pnv_ioda1_init_m64(struct pnv_phb *phb) |
258 | { | |
259 | struct resource *r; | |
260 | int index; | |
261 | ||
262 | /* | |
263 | * There are 16 M64 BARs, each of which has 8 segments. So | |
264 | * there are as many M64 segments as the maximum number of | |
265 | * PEs, which is 128. | |
266 | */ | |
267 | for (index = 0; index < PNV_IODA1_M64_NUM; index++) { | |
268 | unsigned long base, segsz = phb->ioda.m64_segsize; | |
269 | int64_t rc; | |
270 | ||
271 | base = phb->ioda.m64_base + | |
272 | index * PNV_IODA1_M64_SEGS * segsz; | |
273 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
274 | OPAL_M64_WINDOW_TYPE, index, base, 0, | |
275 | PNV_IODA1_M64_SEGS * segsz); | |
276 | if (rc != OPAL_SUCCESS) { | |
277 | pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n", | |
278 | rc, phb->hose->global_number, index); | |
279 | goto fail; | |
280 | } | |
281 | ||
282 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
283 | OPAL_M64_WINDOW_TYPE, index, | |
284 | OPAL_ENABLE_M64_SPLIT); | |
285 | if (rc != OPAL_SUCCESS) { | |
286 | pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n", | |
287 | rc, phb->hose->global_number, index); | |
288 | goto fail; | |
289 | } | |
290 | } | |
291 | ||
292 | /* | |
293 | * Exclude the segment used by the reserved PE, which | |
294 | * is expected to be 0 or last supported PE#. | |
295 | */ | |
296 | r = &phb->hose->mem_resources[1]; | |
297 | if (phb->ioda.reserved_pe_idx == 0) | |
298 | r->start += phb->ioda.m64_segsize; | |
299 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) | |
300 | r->end -= phb->ioda.m64_segsize; | |
301 | else | |
302 | WARN(1, "Wrong reserved PE#%d on PHB#%d\n", | |
303 | phb->ioda.reserved_pe_idx, phb->hose->global_number); | |
304 | ||
305 | return 0; | |
306 | ||
307 | fail: | |
308 | for ( ; index >= 0; index--) | |
309 | opal_pci_phb_mmio_enable(phb->opal_id, | |
310 | OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); | |
311 | ||
312 | return -EIO; | |
313 | } | |
314 | ||
c430670a GS |
315 | static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, |
316 | unsigned long *pe_bitmap, | |
317 | bool all) | |
262af557 | 318 | { |
262af557 | 319 | struct pci_dev *pdev; |
96a2f92b GS |
320 | |
321 | list_for_each_entry(pdev, &bus->devices, bus_list) { | |
c430670a | 322 | pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); |
96a2f92b GS |
323 | |
324 | if (all && pdev->subordinate) | |
c430670a GS |
325 | pnv_ioda_reserve_m64_pe(pdev->subordinate, |
326 | pe_bitmap, all); | |
96a2f92b GS |
327 | } |
328 | } | |
329 | ||
1e916772 | 330 | static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) |
262af557 | 331 | { |
26ba248d GS |
332 | struct pci_controller *hose = pci_bus_to_host(bus); |
333 | struct pnv_phb *phb = hose->private_data; | |
262af557 GC |
334 | struct pnv_ioda_pe *master_pe, *pe; |
335 | unsigned long size, *pe_alloc; | |
26ba248d | 336 | int i; |
262af557 GC |
337 | |
338 | /* Root bus shouldn't use M64 */ | |
339 | if (pci_is_root_bus(bus)) | |
1e916772 | 340 | return NULL; |
262af557 | 341 | |
262af557 | 342 | /* Allocate bitmap */ |
92b8f137 | 343 | size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); |
262af557 GC |
344 | pe_alloc = kzalloc(size, GFP_KERNEL); |
345 | if (!pe_alloc) { | |
346 | pr_warn("%s: Out of memory !\n", | |
347 | __func__); | |
1e916772 | 348 | return NULL; |
262af557 GC |
349 | } |
350 | ||
26ba248d | 351 | /* Figure out reserved PE numbers by the PE */ |
c430670a | 352 | pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); |
262af557 GC |
353 | |
354 | /* | |
355 | * the current bus might not own M64 window and that's all | |
356 | * contributed by its child buses. For the case, we needn't | |
357 | * pick M64 dependent PE#. | |
358 | */ | |
92b8f137 | 359 | if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { |
262af557 | 360 | kfree(pe_alloc); |
1e916772 | 361 | return NULL; |
262af557 GC |
362 | } |
363 | ||
364 | /* | |
365 | * Figure out the master PE and put all slave PEs to master | |
366 | * PE's list to form compound PE. | |
367 | */ | |
262af557 GC |
368 | master_pe = NULL; |
369 | i = -1; | |
92b8f137 GS |
370 | while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < |
371 | phb->ioda.total_pe_num) { | |
262af557 | 372 | pe = &phb->ioda.pe_array[i]; |
262af557 | 373 | |
93289d8c | 374 | phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; |
262af557 GC |
375 | if (!master_pe) { |
376 | pe->flags |= PNV_IODA_PE_MASTER; | |
377 | INIT_LIST_HEAD(&pe->slaves); | |
378 | master_pe = pe; | |
379 | } else { | |
380 | pe->flags |= PNV_IODA_PE_SLAVE; | |
381 | pe->master = master_pe; | |
382 | list_add_tail(&pe->list, &master_pe->slaves); | |
383 | } | |
99451551 GS |
384 | |
385 | /* | |
386 | * P7IOC supports M64DT, which helps mapping M64 segment | |
387 | * to one particular PE#. However, PHB3 has fixed mapping | |
388 | * between M64 segment and PE#. In order to have same logic | |
389 | * for P7IOC and PHB3, we enforce fixed mapping between M64 | |
390 | * segment and PE# on P7IOC. | |
391 | */ | |
392 | if (phb->type == PNV_PHB_IODA1) { | |
393 | int64_t rc; | |
394 | ||
395 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
396 | pe->pe_number, OPAL_M64_WINDOW_TYPE, | |
397 | pe->pe_number / PNV_IODA1_M64_SEGS, | |
398 | pe->pe_number % PNV_IODA1_M64_SEGS); | |
399 | if (rc != OPAL_SUCCESS) | |
400 | pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n", | |
401 | __func__, rc, phb->hose->global_number, | |
402 | pe->pe_number); | |
403 | } | |
262af557 GC |
404 | } |
405 | ||
406 | kfree(pe_alloc); | |
1e916772 | 407 | return master_pe; |
262af557 GC |
408 | } |
409 | ||
410 | static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) | |
411 | { | |
412 | struct pci_controller *hose = phb->hose; | |
413 | struct device_node *dn = hose->dn; | |
414 | struct resource *res; | |
415 | const u32 *r; | |
416 | u64 pci_addr; | |
417 | ||
99451551 | 418 | if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { |
1665c4a8 GS |
419 | pr_info(" Not support M64 window\n"); |
420 | return; | |
421 | } | |
422 | ||
e4d54f71 | 423 | if (!firmware_has_feature(FW_FEATURE_OPAL)) { |
262af557 GC |
424 | pr_info(" Firmware too old to support M64 window\n"); |
425 | return; | |
426 | } | |
427 | ||
428 | r = of_get_property(dn, "ibm,opal-m64-window", NULL); | |
429 | if (!r) { | |
430 | pr_info(" No <ibm,opal-m64-window> on %s\n", | |
431 | dn->full_name); | |
432 | return; | |
433 | } | |
434 | ||
262af557 | 435 | res = &hose->mem_resources[1]; |
e80c4e7c | 436 | res->name = dn->full_name; |
262af557 GC |
437 | res->start = of_translate_address(dn, r + 2); |
438 | res->end = res->start + of_read_number(r + 4, 2) - 1; | |
439 | res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); | |
440 | pci_addr = of_read_number(r, 2); | |
441 | hose->mem_offset[1] = res->start - pci_addr; | |
442 | ||
443 | phb->ioda.m64_size = resource_size(res); | |
92b8f137 | 444 | phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; |
262af557 GC |
445 | phb->ioda.m64_base = pci_addr; |
446 | ||
e9863e68 WY |
447 | pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n", |
448 | res->start, res->end, pci_addr); | |
449 | ||
262af557 GC |
450 | /* Use last M64 BAR to cover M64 window */ |
451 | phb->ioda.m64_bar_idx = 15; | |
99451551 GS |
452 | if (phb->type == PNV_PHB_IODA1) |
453 | phb->init_m64 = pnv_ioda1_init_m64; | |
454 | else | |
455 | phb->init_m64 = pnv_ioda2_init_m64; | |
c430670a GS |
456 | phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; |
457 | phb->pick_m64_pe = pnv_ioda_pick_m64_pe; | |
262af557 GC |
458 | } |
459 | ||
49dec922 GS |
460 | static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) |
461 | { | |
462 | struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; | |
463 | struct pnv_ioda_pe *slave; | |
464 | s64 rc; | |
465 | ||
466 | /* Fetch master PE */ | |
467 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
468 | pe = pe->master; | |
ec8e4e9d GS |
469 | if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) |
470 | return; | |
471 | ||
49dec922 GS |
472 | pe_no = pe->pe_number; |
473 | } | |
474 | ||
475 | /* Freeze master PE */ | |
476 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
477 | pe_no, | |
478 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
479 | if (rc != OPAL_SUCCESS) { | |
480 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
481 | __func__, rc, phb->hose->global_number, pe_no); | |
482 | return; | |
483 | } | |
484 | ||
485 | /* Freeze slave PEs */ | |
486 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
487 | return; | |
488 | ||
489 | list_for_each_entry(slave, &pe->slaves, list) { | |
490 | rc = opal_pci_eeh_freeze_set(phb->opal_id, | |
491 | slave->pe_number, | |
492 | OPAL_EEH_ACTION_SET_FREEZE_ALL); | |
493 | if (rc != OPAL_SUCCESS) | |
494 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", | |
495 | __func__, rc, phb->hose->global_number, | |
496 | slave->pe_number); | |
497 | } | |
498 | } | |
499 | ||
e51df2c1 | 500 | static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) |
49dec922 GS |
501 | { |
502 | struct pnv_ioda_pe *pe, *slave; | |
503 | s64 rc; | |
504 | ||
505 | /* Find master PE */ | |
506 | pe = &phb->ioda.pe_array[pe_no]; | |
507 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
508 | pe = pe->master; | |
509 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
510 | pe_no = pe->pe_number; | |
511 | } | |
512 | ||
513 | /* Clear frozen state for master PE */ | |
514 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); | |
515 | if (rc != OPAL_SUCCESS) { | |
516 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
517 | __func__, rc, opt, phb->hose->global_number, pe_no); | |
518 | return -EIO; | |
519 | } | |
520 | ||
521 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
522 | return 0; | |
523 | ||
524 | /* Clear frozen state for slave PEs */ | |
525 | list_for_each_entry(slave, &pe->slaves, list) { | |
526 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, | |
527 | slave->pe_number, | |
528 | opt); | |
529 | if (rc != OPAL_SUCCESS) { | |
530 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", | |
531 | __func__, rc, opt, phb->hose->global_number, | |
532 | slave->pe_number); | |
533 | return -EIO; | |
534 | } | |
535 | } | |
536 | ||
537 | return 0; | |
538 | } | |
539 | ||
540 | static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) | |
541 | { | |
542 | struct pnv_ioda_pe *slave, *pe; | |
543 | u8 fstate, state; | |
544 | __be16 pcierr; | |
545 | s64 rc; | |
546 | ||
547 | /* Sanity check on PE number */ | |
92b8f137 | 548 | if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) |
49dec922 GS |
549 | return OPAL_EEH_STOPPED_PERM_UNAVAIL; |
550 | ||
551 | /* | |
552 | * Fetch the master PE and the PE instance might be | |
553 | * not initialized yet. | |
554 | */ | |
555 | pe = &phb->ioda.pe_array[pe_no]; | |
556 | if (pe->flags & PNV_IODA_PE_SLAVE) { | |
557 | pe = pe->master; | |
558 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); | |
559 | pe_no = pe->pe_number; | |
560 | } | |
561 | ||
562 | /* Check the master PE */ | |
563 | rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, | |
564 | &state, &pcierr, NULL); | |
565 | if (rc != OPAL_SUCCESS) { | |
566 | pr_warn("%s: Failure %lld getting " | |
567 | "PHB#%x-PE#%x state\n", | |
568 | __func__, rc, | |
569 | phb->hose->global_number, pe_no); | |
570 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
571 | } | |
572 | ||
573 | /* Check the slave PE */ | |
574 | if (!(pe->flags & PNV_IODA_PE_MASTER)) | |
575 | return state; | |
576 | ||
577 | list_for_each_entry(slave, &pe->slaves, list) { | |
578 | rc = opal_pci_eeh_freeze_status(phb->opal_id, | |
579 | slave->pe_number, | |
580 | &fstate, | |
581 | &pcierr, | |
582 | NULL); | |
583 | if (rc != OPAL_SUCCESS) { | |
584 | pr_warn("%s: Failure %lld getting " | |
585 | "PHB#%x-PE#%x state\n", | |
586 | __func__, rc, | |
587 | phb->hose->global_number, slave->pe_number); | |
588 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; | |
589 | } | |
590 | ||
591 | /* | |
592 | * Override the result based on the ascending | |
593 | * priority. | |
594 | */ | |
595 | if (fstate > state) | |
596 | state = fstate; | |
597 | } | |
598 | ||
599 | return state; | |
600 | } | |
601 | ||
184cd4a3 BH |
602 | /* Currently those 2 are only used when MSIs are enabled, this will change |
603 | * but in the meantime, we need to protect them to avoid warnings | |
604 | */ | |
605 | #ifdef CONFIG_PCI_MSI | |
cad5cef6 | 606 | static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) |
184cd4a3 BH |
607 | { |
608 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
609 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 610 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
611 | |
612 | if (!pdn) | |
613 | return NULL; | |
614 | if (pdn->pe_number == IODA_INVALID_PE) | |
615 | return NULL; | |
616 | return &phb->ioda.pe_array[pdn->pe_number]; | |
617 | } | |
184cd4a3 BH |
618 | #endif /* CONFIG_PCI_MSI */ |
619 | ||
b131a842 GS |
620 | static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, |
621 | struct pnv_ioda_pe *parent, | |
622 | struct pnv_ioda_pe *child, | |
623 | bool is_add) | |
624 | { | |
625 | const char *desc = is_add ? "adding" : "removing"; | |
626 | uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : | |
627 | OPAL_REMOVE_PE_FROM_DOMAIN; | |
628 | struct pnv_ioda_pe *slave; | |
629 | long rc; | |
630 | ||
631 | /* Parent PE affects child PE */ | |
632 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, | |
633 | child->pe_number, op); | |
634 | if (rc != OPAL_SUCCESS) { | |
635 | pe_warn(child, "OPAL error %ld %s to parent PELTV\n", | |
636 | rc, desc); | |
637 | return -ENXIO; | |
638 | } | |
639 | ||
640 | if (!(child->flags & PNV_IODA_PE_MASTER)) | |
641 | return 0; | |
642 | ||
643 | /* Compound case: parent PE affects slave PEs */ | |
644 | list_for_each_entry(slave, &child->slaves, list) { | |
645 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, | |
646 | slave->pe_number, op); | |
647 | if (rc != OPAL_SUCCESS) { | |
648 | pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", | |
649 | rc, desc); | |
650 | return -ENXIO; | |
651 | } | |
652 | } | |
653 | ||
654 | return 0; | |
655 | } | |
656 | ||
657 | static int pnv_ioda_set_peltv(struct pnv_phb *phb, | |
658 | struct pnv_ioda_pe *pe, | |
659 | bool is_add) | |
660 | { | |
661 | struct pnv_ioda_pe *slave; | |
781a868f | 662 | struct pci_dev *pdev = NULL; |
b131a842 GS |
663 | int ret; |
664 | ||
665 | /* | |
666 | * Clear PE frozen state. If it's master PE, we need | |
667 | * clear slave PE frozen state as well. | |
668 | */ | |
669 | if (is_add) { | |
670 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, | |
671 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
672 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
673 | list_for_each_entry(slave, &pe->slaves, list) | |
674 | opal_pci_eeh_freeze_clear(phb->opal_id, | |
675 | slave->pe_number, | |
676 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); | |
677 | } | |
678 | } | |
679 | ||
680 | /* | |
681 | * Associate PE in PELT. We need add the PE into the | |
682 | * corresponding PELT-V as well. Otherwise, the error | |
683 | * originated from the PE might contribute to other | |
684 | * PEs. | |
685 | */ | |
686 | ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); | |
687 | if (ret) | |
688 | return ret; | |
689 | ||
690 | /* For compound PEs, any one affects all of them */ | |
691 | if (pe->flags & PNV_IODA_PE_MASTER) { | |
692 | list_for_each_entry(slave, &pe->slaves, list) { | |
693 | ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); | |
694 | if (ret) | |
695 | return ret; | |
696 | } | |
697 | } | |
698 | ||
699 | if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) | |
700 | pdev = pe->pbus->self; | |
781a868f | 701 | else if (pe->flags & PNV_IODA_PE_DEV) |
b131a842 | 702 | pdev = pe->pdev->bus->self; |
781a868f WY |
703 | #ifdef CONFIG_PCI_IOV |
704 | else if (pe->flags & PNV_IODA_PE_VF) | |
283e2d8a | 705 | pdev = pe->parent_dev; |
781a868f | 706 | #endif /* CONFIG_PCI_IOV */ |
b131a842 GS |
707 | while (pdev) { |
708 | struct pci_dn *pdn = pci_get_pdn(pdev); | |
709 | struct pnv_ioda_pe *parent; | |
710 | ||
711 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { | |
712 | parent = &phb->ioda.pe_array[pdn->pe_number]; | |
713 | ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); | |
714 | if (ret) | |
715 | return ret; | |
716 | } | |
717 | ||
718 | pdev = pdev->bus->self; | |
719 | } | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
781a868f WY |
724 | #ifdef CONFIG_PCI_IOV |
725 | static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) | |
726 | { | |
727 | struct pci_dev *parent; | |
728 | uint8_t bcomp, dcomp, fcomp; | |
729 | int64_t rc; | |
730 | long rid_end, rid; | |
731 | ||
732 | /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ | |
733 | if (pe->pbus) { | |
734 | int count; | |
735 | ||
736 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
737 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
738 | parent = pe->pbus->self; | |
739 | if (pe->flags & PNV_IODA_PE_BUS_ALL) | |
740 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
741 | else | |
742 | count = 1; | |
743 | ||
744 | switch(count) { | |
745 | case 1: bcomp = OpalPciBusAll; break; | |
746 | case 2: bcomp = OpalPciBus7Bits; break; | |
747 | case 4: bcomp = OpalPciBus6Bits; break; | |
748 | case 8: bcomp = OpalPciBus5Bits; break; | |
749 | case 16: bcomp = OpalPciBus4Bits; break; | |
750 | case 32: bcomp = OpalPciBus3Bits; break; | |
751 | default: | |
752 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", | |
753 | count); | |
754 | /* Do an exact match only */ | |
755 | bcomp = OpalPciBusAll; | |
756 | } | |
757 | rid_end = pe->rid + (count << 8); | |
758 | } else { | |
759 | if (pe->flags & PNV_IODA_PE_VF) | |
760 | parent = pe->parent_dev; | |
761 | else | |
762 | parent = pe->pdev->bus->self; | |
763 | bcomp = OpalPciBusAll; | |
764 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
765 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
766 | rid_end = pe->rid + 1; | |
767 | } | |
768 | ||
769 | /* Clear the reverse map */ | |
770 | for (rid = pe->rid; rid < rid_end; rid++) | |
771 | phb->ioda.pe_rmap[rid] = 0; | |
772 | ||
773 | /* Release from all parents PELT-V */ | |
774 | while (parent) { | |
775 | struct pci_dn *pdn = pci_get_pdn(parent); | |
776 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { | |
777 | rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, | |
778 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | |
779 | /* XXX What to do in case of error ? */ | |
780 | } | |
781 | parent = parent->bus->self; | |
782 | } | |
783 | ||
f951e510 | 784 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, |
781a868f WY |
785 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
786 | ||
787 | /* Disassociate PE in PELT */ | |
788 | rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, | |
789 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); | |
790 | if (rc) | |
791 | pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); | |
792 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, | |
793 | bcomp, dcomp, fcomp, OPAL_UNMAP_PE); | |
794 | if (rc) | |
795 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
796 | ||
797 | pe->pbus = NULL; | |
798 | pe->pdev = NULL; | |
799 | pe->parent_dev = NULL; | |
800 | ||
801 | return 0; | |
802 | } | |
803 | #endif /* CONFIG_PCI_IOV */ | |
804 | ||
cad5cef6 | 805 | static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
184cd4a3 BH |
806 | { |
807 | struct pci_dev *parent; | |
808 | uint8_t bcomp, dcomp, fcomp; | |
809 | long rc, rid_end, rid; | |
810 | ||
811 | /* Bus validation ? */ | |
812 | if (pe->pbus) { | |
813 | int count; | |
814 | ||
815 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; | |
816 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; | |
817 | parent = pe->pbus->self; | |
fb446ad0 GS |
818 | if (pe->flags & PNV_IODA_PE_BUS_ALL) |
819 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; | |
820 | else | |
821 | count = 1; | |
822 | ||
184cd4a3 BH |
823 | switch(count) { |
824 | case 1: bcomp = OpalPciBusAll; break; | |
825 | case 2: bcomp = OpalPciBus7Bits; break; | |
826 | case 4: bcomp = OpalPciBus6Bits; break; | |
827 | case 8: bcomp = OpalPciBus5Bits; break; | |
828 | case 16: bcomp = OpalPciBus4Bits; break; | |
829 | case 32: bcomp = OpalPciBus3Bits; break; | |
830 | default: | |
781a868f WY |
831 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", |
832 | count); | |
184cd4a3 BH |
833 | /* Do an exact match only */ |
834 | bcomp = OpalPciBusAll; | |
835 | } | |
836 | rid_end = pe->rid + (count << 8); | |
837 | } else { | |
781a868f WY |
838 | #ifdef CONFIG_PCI_IOV |
839 | if (pe->flags & PNV_IODA_PE_VF) | |
840 | parent = pe->parent_dev; | |
841 | else | |
842 | #endif /* CONFIG_PCI_IOV */ | |
843 | parent = pe->pdev->bus->self; | |
184cd4a3 BH |
844 | bcomp = OpalPciBusAll; |
845 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; | |
846 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; | |
847 | rid_end = pe->rid + 1; | |
848 | } | |
849 | ||
631ad691 GS |
850 | /* |
851 | * Associate PE in PELT. We need add the PE into the | |
852 | * corresponding PELT-V as well. Otherwise, the error | |
853 | * originated from the PE might contribute to other | |
854 | * PEs. | |
855 | */ | |
184cd4a3 BH |
856 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, |
857 | bcomp, dcomp, fcomp, OPAL_MAP_PE); | |
858 | if (rc) { | |
859 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); | |
860 | return -ENXIO; | |
861 | } | |
631ad691 | 862 | |
5d2aa710 AP |
863 | /* |
864 | * Configure PELTV. NPUs don't have a PELTV table so skip | |
865 | * configuration on them. | |
866 | */ | |
867 | if (phb->type != PNV_PHB_NPU) | |
868 | pnv_ioda_set_peltv(phb, pe, true); | |
184cd4a3 | 869 | |
184cd4a3 BH |
870 | /* Setup reverse map */ |
871 | for (rid = pe->rid; rid < rid_end; rid++) | |
872 | phb->ioda.pe_rmap[rid] = pe->pe_number; | |
873 | ||
874 | /* Setup one MVTs on IODA1 */ | |
4773f76b GS |
875 | if (phb->type != PNV_PHB_IODA1) { |
876 | pe->mve_number = 0; | |
877 | goto out; | |
878 | } | |
879 | ||
880 | pe->mve_number = pe->pe_number; | |
881 | rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); | |
882 | if (rc != OPAL_SUCCESS) { | |
883 | pe_err(pe, "OPAL error %ld setting up MVE %d\n", | |
884 | rc, pe->mve_number); | |
885 | pe->mve_number = -1; | |
886 | } else { | |
887 | rc = opal_pci_set_mve_enable(phb->opal_id, | |
888 | pe->mve_number, OPAL_ENABLE_MVE); | |
184cd4a3 | 889 | if (rc) { |
4773f76b | 890 | pe_err(pe, "OPAL error %ld enabling MVE %d\n", |
184cd4a3 BH |
891 | rc, pe->mve_number); |
892 | pe->mve_number = -1; | |
184cd4a3 | 893 | } |
4773f76b | 894 | } |
184cd4a3 | 895 | |
4773f76b | 896 | out: |
184cd4a3 BH |
897 | return 0; |
898 | } | |
899 | ||
781a868f WY |
900 | #ifdef CONFIG_PCI_IOV |
901 | static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) | |
902 | { | |
903 | struct pci_dn *pdn = pci_get_pdn(dev); | |
904 | int i; | |
905 | struct resource *res, res2; | |
906 | resource_size_t size; | |
907 | u16 num_vfs; | |
908 | ||
909 | if (!dev->is_physfn) | |
910 | return -EINVAL; | |
911 | ||
912 | /* | |
913 | * "offset" is in VFs. The M64 windows are sized so that when they | |
914 | * are segmented, each segment is the same size as the IOV BAR. | |
915 | * Each segment is in a separate PE, and the high order bits of the | |
916 | * address are the PE number. Therefore, each VF's BAR is in a | |
917 | * separate PE, and changing the IOV BAR start address changes the | |
918 | * range of PEs the VFs are in. | |
919 | */ | |
920 | num_vfs = pdn->num_vfs; | |
921 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
922 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | |
923 | if (!res->flags || !res->parent) | |
924 | continue; | |
925 | ||
781a868f WY |
926 | /* |
927 | * The actual IOV BAR range is determined by the start address | |
928 | * and the actual size for num_vfs VFs BAR. This check is to | |
929 | * make sure that after shifting, the range will not overlap | |
930 | * with another device. | |
931 | */ | |
932 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); | |
933 | res2.flags = res->flags; | |
934 | res2.start = res->start + (size * offset); | |
935 | res2.end = res2.start + (size * num_vfs) - 1; | |
936 | ||
937 | if (res2.end > res->end) { | |
938 | dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", | |
939 | i, &res2, res, num_vfs, offset); | |
940 | return -EBUSY; | |
941 | } | |
942 | } | |
943 | ||
944 | /* | |
945 | * After doing so, there would be a "hole" in the /proc/iomem when | |
946 | * offset is a positive value. It looks like the device return some | |
947 | * mmio back to the system, which actually no one could use it. | |
948 | */ | |
949 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
950 | res = &dev->resource[i + PCI_IOV_RESOURCES]; | |
951 | if (!res->flags || !res->parent) | |
952 | continue; | |
953 | ||
781a868f WY |
954 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); |
955 | res2 = *res; | |
956 | res->start += size * offset; | |
957 | ||
74703cc4 WY |
958 | dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", |
959 | i, &res2, res, (offset > 0) ? "En" : "Dis", | |
960 | num_vfs, offset); | |
781a868f WY |
961 | pci_update_resource(dev, i + PCI_IOV_RESOURCES); |
962 | } | |
963 | return 0; | |
964 | } | |
965 | #endif /* CONFIG_PCI_IOV */ | |
966 | ||
cad5cef6 | 967 | static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) |
184cd4a3 BH |
968 | { |
969 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
970 | struct pnv_phb *phb = hose->private_data; | |
b72c1f65 | 971 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 | 972 | struct pnv_ioda_pe *pe; |
184cd4a3 BH |
973 | |
974 | if (!pdn) { | |
975 | pr_err("%s: Device tree node not associated properly\n", | |
976 | pci_name(dev)); | |
977 | return NULL; | |
978 | } | |
979 | if (pdn->pe_number != IODA_INVALID_PE) | |
980 | return NULL; | |
981 | ||
1e916772 GS |
982 | pe = pnv_ioda_alloc_pe(phb); |
983 | if (!pe) { | |
184cd4a3 BH |
984 | pr_warning("%s: Not enough PE# available, disabling device\n", |
985 | pci_name(dev)); | |
986 | return NULL; | |
987 | } | |
988 | ||
989 | /* NOTE: We get only one ref to the pci_dev for the pdn, not for the | |
990 | * pointer in the PE data structure, both should be destroyed at the | |
991 | * same time. However, this needs to be looked at more closely again | |
992 | * once we actually start removing things (Hotplug, SR-IOV, ...) | |
993 | * | |
994 | * At some point we want to remove the PDN completely anyways | |
995 | */ | |
184cd4a3 BH |
996 | pci_dev_get(dev); |
997 | pdn->pcidev = dev; | |
1e916772 | 998 | pdn->pe_number = pe->pe_number; |
5d2aa710 | 999 | pe->flags = PNV_IODA_PE_DEV; |
184cd4a3 BH |
1000 | pe->pdev = dev; |
1001 | pe->pbus = NULL; | |
184cd4a3 BH |
1002 | pe->mve_number = -1; |
1003 | pe->rid = dev->bus->number << 8 | pdn->devfn; | |
1004 | ||
1005 | pe_info(pe, "Associated device to PE\n"); | |
1006 | ||
1007 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1008 | /* XXX What do we do here ? */ | |
1e916772 | 1009 | pnv_ioda_free_pe(pe); |
184cd4a3 BH |
1010 | pdn->pe_number = IODA_INVALID_PE; |
1011 | pe->pdev = NULL; | |
1012 | pci_dev_put(dev); | |
1013 | return NULL; | |
1014 | } | |
1015 | ||
184cd4a3 BH |
1016 | return pe; |
1017 | } | |
1018 | ||
1019 | static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) | |
1020 | { | |
1021 | struct pci_dev *dev; | |
1022 | ||
1023 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b72c1f65 | 1024 | struct pci_dn *pdn = pci_get_pdn(dev); |
184cd4a3 BH |
1025 | |
1026 | if (pdn == NULL) { | |
1027 | pr_warn("%s: No device node associated with device !\n", | |
1028 | pci_name(dev)); | |
1029 | continue; | |
1030 | } | |
94973b24 | 1031 | pdn->pcidev = dev; |
184cd4a3 | 1032 | pdn->pe_number = pe->pe_number; |
fb446ad0 | 1033 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
184cd4a3 BH |
1034 | pnv_ioda_setup_same_PE(dev->subordinate, pe); |
1035 | } | |
1036 | } | |
1037 | ||
fb446ad0 GS |
1038 | /* |
1039 | * There're 2 types of PCI bus sensitive PEs: One that is compromised of | |
1040 | * single PCI bus. Another one that contains the primary PCI bus and its | |
1041 | * subordinate PCI devices and buses. The second type of PE is normally | |
1042 | * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. | |
1043 | */ | |
1e916772 | 1044 | static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) |
184cd4a3 | 1045 | { |
fb446ad0 | 1046 | struct pci_controller *hose = pci_bus_to_host(bus); |
184cd4a3 | 1047 | struct pnv_phb *phb = hose->private_data; |
1e916772 | 1048 | struct pnv_ioda_pe *pe = NULL; |
262af557 GC |
1049 | |
1050 | /* Check if PE is determined by M64 */ | |
1051 | if (phb->pick_m64_pe) | |
1e916772 | 1052 | pe = phb->pick_m64_pe(bus, all); |
262af557 GC |
1053 | |
1054 | /* The PE number isn't pinned by M64 */ | |
1e916772 GS |
1055 | if (!pe) |
1056 | pe = pnv_ioda_alloc_pe(phb); | |
184cd4a3 | 1057 | |
1e916772 | 1058 | if (!pe) { |
fb446ad0 GS |
1059 | pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", |
1060 | __func__, pci_domain_nr(bus), bus->number); | |
1e916772 | 1061 | return NULL; |
184cd4a3 BH |
1062 | } |
1063 | ||
262af557 | 1064 | pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); |
184cd4a3 BH |
1065 | pe->pbus = bus; |
1066 | pe->pdev = NULL; | |
184cd4a3 | 1067 | pe->mve_number = -1; |
b918c62e | 1068 | pe->rid = bus->busn_res.start << 8; |
184cd4a3 | 1069 | |
fb446ad0 GS |
1070 | if (all) |
1071 | pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n", | |
1e916772 | 1072 | bus->busn_res.start, bus->busn_res.end, pe->pe_number); |
fb446ad0 GS |
1073 | else |
1074 | pe_info(pe, "Secondary bus %d associated with PE#%d\n", | |
1e916772 | 1075 | bus->busn_res.start, pe->pe_number); |
184cd4a3 BH |
1076 | |
1077 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1078 | /* XXX What do we do here ? */ | |
1e916772 | 1079 | pnv_ioda_free_pe(pe); |
184cd4a3 | 1080 | pe->pbus = NULL; |
1e916772 | 1081 | return NULL; |
184cd4a3 BH |
1082 | } |
1083 | ||
1084 | /* Associate it with all child devices */ | |
1085 | pnv_ioda_setup_same_PE(bus, pe); | |
1086 | ||
7ebdf956 GS |
1087 | /* Put PE to the list */ |
1088 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1e916772 GS |
1089 | |
1090 | return pe; | |
184cd4a3 BH |
1091 | } |
1092 | ||
b521549a AP |
1093 | static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) |
1094 | { | |
1095 | int pe_num, found_pe = false, rc; | |
1096 | long rid; | |
1097 | struct pnv_ioda_pe *pe; | |
1098 | struct pci_dev *gpu_pdev; | |
1099 | struct pci_dn *npu_pdn; | |
1100 | struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); | |
1101 | struct pnv_phb *phb = hose->private_data; | |
1102 | ||
1103 | /* | |
1104 | * Due to a hardware errata PE#0 on the NPU is reserved for | |
1105 | * error handling. This means we only have three PEs remaining | |
1106 | * which need to be assigned to four links, implying some | |
1107 | * links must share PEs. | |
1108 | * | |
1109 | * To achieve this we assign PEs such that NPUs linking the | |
1110 | * same GPU get assigned the same PE. | |
1111 | */ | |
1112 | gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); | |
92b8f137 | 1113 | for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { |
b521549a AP |
1114 | pe = &phb->ioda.pe_array[pe_num]; |
1115 | if (!pe->pdev) | |
1116 | continue; | |
1117 | ||
1118 | if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { | |
1119 | /* | |
1120 | * This device has the same peer GPU so should | |
1121 | * be assigned the same PE as the existing | |
1122 | * peer NPU. | |
1123 | */ | |
1124 | dev_info(&npu_pdev->dev, | |
1125 | "Associating to existing PE %d\n", pe_num); | |
1126 | pci_dev_get(npu_pdev); | |
1127 | npu_pdn = pci_get_pdn(npu_pdev); | |
1128 | rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; | |
1129 | npu_pdn->pcidev = npu_pdev; | |
1130 | npu_pdn->pe_number = pe_num; | |
b521549a AP |
1131 | phb->ioda.pe_rmap[rid] = pe->pe_number; |
1132 | ||
1133 | /* Map the PE to this link */ | |
1134 | rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, | |
1135 | OpalPciBusAll, | |
1136 | OPAL_COMPARE_RID_DEVICE_NUMBER, | |
1137 | OPAL_COMPARE_RID_FUNCTION_NUMBER, | |
1138 | OPAL_MAP_PE); | |
1139 | WARN_ON(rc != OPAL_SUCCESS); | |
1140 | found_pe = true; | |
1141 | break; | |
1142 | } | |
1143 | } | |
1144 | ||
1145 | if (!found_pe) | |
1146 | /* | |
1147 | * Could not find an existing PE so allocate a new | |
1148 | * one. | |
1149 | */ | |
1150 | return pnv_ioda_setup_dev_PE(npu_pdev); | |
1151 | else | |
1152 | return pe; | |
1153 | } | |
1154 | ||
1155 | static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) | |
5d2aa710 | 1156 | { |
5d2aa710 AP |
1157 | struct pci_dev *pdev; |
1158 | ||
1159 | list_for_each_entry(pdev, &bus->devices, bus_list) | |
b521549a | 1160 | pnv_ioda_setup_npu_PE(pdev); |
5d2aa710 AP |
1161 | } |
1162 | ||
cad5cef6 | 1163 | static void pnv_ioda_setup_PEs(struct pci_bus *bus) |
184cd4a3 BH |
1164 | { |
1165 | struct pci_dev *dev; | |
fb446ad0 | 1166 | |
d1203852 | 1167 | pnv_ioda_setup_bus_PE(bus, false); |
184cd4a3 BH |
1168 | |
1169 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
fb446ad0 GS |
1170 | if (dev->subordinate) { |
1171 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) | |
d1203852 | 1172 | pnv_ioda_setup_bus_PE(dev->subordinate, true); |
fb446ad0 GS |
1173 | else |
1174 | pnv_ioda_setup_PEs(dev->subordinate); | |
1175 | } | |
1176 | } | |
1177 | } | |
1178 | ||
1179 | /* | |
1180 | * Configure PEs so that the downstream PCI buses and devices | |
1181 | * could have their associated PE#. Unfortunately, we didn't | |
1182 | * figure out the way to identify the PLX bridge yet. So we | |
1183 | * simply put the PCI bus and the subordinate behind the root | |
1184 | * port to PE# here. The game rule here is expected to be changed | |
1185 | * as soon as we can detected PLX bridge correctly. | |
1186 | */ | |
cad5cef6 | 1187 | static void pnv_pci_ioda_setup_PEs(void) |
fb446ad0 GS |
1188 | { |
1189 | struct pci_controller *hose, *tmp; | |
262af557 | 1190 | struct pnv_phb *phb; |
fb446ad0 GS |
1191 | |
1192 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
262af557 GC |
1193 | phb = hose->private_data; |
1194 | ||
1195 | /* M64 layout might affect PE allocation */ | |
5ef73567 | 1196 | if (phb->reserve_m64_pe) |
96a2f92b | 1197 | phb->reserve_m64_pe(hose->bus, NULL, true); |
262af557 | 1198 | |
5d2aa710 AP |
1199 | /* |
1200 | * On NPU PHB, we expect separate PEs for individual PCI | |
1201 | * functions. PCI bus dependent PEs are required for the | |
1202 | * remaining types of PHBs. | |
1203 | */ | |
08f48f32 AP |
1204 | if (phb->type == PNV_PHB_NPU) { |
1205 | /* PE#0 is needed for error reporting */ | |
1206 | pnv_ioda_reserve_pe(phb, 0); | |
b521549a | 1207 | pnv_ioda_setup_npu_PEs(hose->bus); |
08f48f32 | 1208 | } else |
5d2aa710 | 1209 | pnv_ioda_setup_PEs(hose->bus); |
184cd4a3 BH |
1210 | } |
1211 | } | |
1212 | ||
a8b2f828 | 1213 | #ifdef CONFIG_PCI_IOV |
ee8222fe | 1214 | static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) |
781a868f WY |
1215 | { |
1216 | struct pci_bus *bus; | |
1217 | struct pci_controller *hose; | |
1218 | struct pnv_phb *phb; | |
1219 | struct pci_dn *pdn; | |
02639b0e | 1220 | int i, j; |
ee8222fe | 1221 | int m64_bars; |
781a868f WY |
1222 | |
1223 | bus = pdev->bus; | |
1224 | hose = pci_bus_to_host(bus); | |
1225 | phb = hose->private_data; | |
1226 | pdn = pci_get_pdn(pdev); | |
1227 | ||
ee8222fe WY |
1228 | if (pdn->m64_single_mode) |
1229 | m64_bars = num_vfs; | |
1230 | else | |
1231 | m64_bars = 1; | |
1232 | ||
02639b0e | 1233 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) |
ee8222fe WY |
1234 | for (j = 0; j < m64_bars; j++) { |
1235 | if (pdn->m64_map[j][i] == IODA_INVALID_M64) | |
02639b0e WY |
1236 | continue; |
1237 | opal_pci_phb_mmio_enable(phb->opal_id, | |
ee8222fe WY |
1238 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); |
1239 | clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); | |
1240 | pdn->m64_map[j][i] = IODA_INVALID_M64; | |
02639b0e | 1241 | } |
781a868f | 1242 | |
ee8222fe | 1243 | kfree(pdn->m64_map); |
781a868f WY |
1244 | return 0; |
1245 | } | |
1246 | ||
02639b0e | 1247 | static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) |
781a868f WY |
1248 | { |
1249 | struct pci_bus *bus; | |
1250 | struct pci_controller *hose; | |
1251 | struct pnv_phb *phb; | |
1252 | struct pci_dn *pdn; | |
1253 | unsigned int win; | |
1254 | struct resource *res; | |
02639b0e | 1255 | int i, j; |
781a868f | 1256 | int64_t rc; |
02639b0e WY |
1257 | int total_vfs; |
1258 | resource_size_t size, start; | |
1259 | int pe_num; | |
ee8222fe | 1260 | int m64_bars; |
781a868f WY |
1261 | |
1262 | bus = pdev->bus; | |
1263 | hose = pci_bus_to_host(bus); | |
1264 | phb = hose->private_data; | |
1265 | pdn = pci_get_pdn(pdev); | |
02639b0e | 1266 | total_vfs = pci_sriov_get_totalvfs(pdev); |
781a868f | 1267 | |
ee8222fe WY |
1268 | if (pdn->m64_single_mode) |
1269 | m64_bars = num_vfs; | |
1270 | else | |
1271 | m64_bars = 1; | |
1272 | ||
1273 | pdn->m64_map = kmalloc(sizeof(*pdn->m64_map) * m64_bars, GFP_KERNEL); | |
1274 | if (!pdn->m64_map) | |
1275 | return -ENOMEM; | |
1276 | /* Initialize the m64_map to IODA_INVALID_M64 */ | |
1277 | for (i = 0; i < m64_bars ; i++) | |
1278 | for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) | |
1279 | pdn->m64_map[i][j] = IODA_INVALID_M64; | |
02639b0e | 1280 | |
781a868f WY |
1281 | |
1282 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
1283 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
1284 | if (!res->flags || !res->parent) | |
1285 | continue; | |
1286 | ||
ee8222fe | 1287 | for (j = 0; j < m64_bars; j++) { |
02639b0e WY |
1288 | do { |
1289 | win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, | |
1290 | phb->ioda.m64_bar_idx + 1, 0); | |
1291 | ||
1292 | if (win >= phb->ioda.m64_bar_idx + 1) | |
1293 | goto m64_failed; | |
1294 | } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); | |
1295 | ||
ee8222fe | 1296 | pdn->m64_map[j][i] = win; |
02639b0e | 1297 | |
ee8222fe | 1298 | if (pdn->m64_single_mode) { |
02639b0e WY |
1299 | size = pci_iov_resource_size(pdev, |
1300 | PCI_IOV_RESOURCES + i); | |
02639b0e WY |
1301 | start = res->start + size * j; |
1302 | } else { | |
1303 | size = resource_size(res); | |
1304 | start = res->start; | |
1305 | } | |
1306 | ||
1307 | /* Map the M64 here */ | |
ee8222fe | 1308 | if (pdn->m64_single_mode) { |
be283eeb | 1309 | pe_num = pdn->pe_num_map[j]; |
02639b0e WY |
1310 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
1311 | pe_num, OPAL_M64_WINDOW_TYPE, | |
ee8222fe | 1312 | pdn->m64_map[j][i], 0); |
02639b0e WY |
1313 | } |
1314 | ||
1315 | rc = opal_pci_set_phb_mem_window(phb->opal_id, | |
1316 | OPAL_M64_WINDOW_TYPE, | |
ee8222fe | 1317 | pdn->m64_map[j][i], |
02639b0e WY |
1318 | start, |
1319 | 0, /* unused */ | |
1320 | size); | |
781a868f | 1321 | |
781a868f | 1322 | |
02639b0e WY |
1323 | if (rc != OPAL_SUCCESS) { |
1324 | dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", | |
1325 | win, rc); | |
1326 | goto m64_failed; | |
1327 | } | |
781a868f | 1328 | |
ee8222fe | 1329 | if (pdn->m64_single_mode) |
02639b0e | 1330 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
ee8222fe | 1331 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); |
02639b0e WY |
1332 | else |
1333 | rc = opal_pci_phb_mmio_enable(phb->opal_id, | |
ee8222fe | 1334 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); |
781a868f | 1335 | |
02639b0e WY |
1336 | if (rc != OPAL_SUCCESS) { |
1337 | dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", | |
1338 | win, rc); | |
1339 | goto m64_failed; | |
1340 | } | |
781a868f WY |
1341 | } |
1342 | } | |
1343 | return 0; | |
1344 | ||
1345 | m64_failed: | |
ee8222fe | 1346 | pnv_pci_vf_release_m64(pdev, num_vfs); |
781a868f WY |
1347 | return -EBUSY; |
1348 | } | |
1349 | ||
c035e37b AK |
1350 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, |
1351 | int num); | |
1352 | static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable); | |
1353 | ||
781a868f WY |
1354 | static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) |
1355 | { | |
781a868f | 1356 | struct iommu_table *tbl; |
781a868f WY |
1357 | int64_t rc; |
1358 | ||
b348aa65 | 1359 | tbl = pe->table_group.tables[0]; |
c035e37b | 1360 | rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
781a868f WY |
1361 | if (rc) |
1362 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); | |
1363 | ||
c035e37b | 1364 | pnv_pci_ioda2_set_bypass(pe, false); |
0eaf4def AK |
1365 | if (pe->table_group.group) { |
1366 | iommu_group_put(pe->table_group.group); | |
1367 | BUG_ON(pe->table_group.group); | |
ac9a5889 | 1368 | } |
aca6913f | 1369 | pnv_pci_ioda2_table_free_pages(tbl); |
781a868f | 1370 | iommu_free_table(tbl, of_node_full_name(dev->dev.of_node)); |
781a868f WY |
1371 | } |
1372 | ||
ee8222fe | 1373 | static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) |
781a868f WY |
1374 | { |
1375 | struct pci_bus *bus; | |
1376 | struct pci_controller *hose; | |
1377 | struct pnv_phb *phb; | |
1378 | struct pnv_ioda_pe *pe, *pe_n; | |
1379 | struct pci_dn *pdn; | |
1380 | ||
1381 | bus = pdev->bus; | |
1382 | hose = pci_bus_to_host(bus); | |
1383 | phb = hose->private_data; | |
02639b0e | 1384 | pdn = pci_get_pdn(pdev); |
781a868f WY |
1385 | |
1386 | if (!pdev->is_physfn) | |
1387 | return; | |
1388 | ||
781a868f WY |
1389 | list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { |
1390 | if (pe->parent_dev != pdev) | |
1391 | continue; | |
1392 | ||
1393 | pnv_pci_ioda2_release_dma_pe(pdev, pe); | |
1394 | ||
1395 | /* Remove from list */ | |
1396 | mutex_lock(&phb->ioda.pe_list_mutex); | |
1397 | list_del(&pe->list); | |
1398 | mutex_unlock(&phb->ioda.pe_list_mutex); | |
1399 | ||
1400 | pnv_ioda_deconfigure_pe(phb, pe); | |
1401 | ||
1e916772 | 1402 | pnv_ioda_free_pe(pe); |
781a868f WY |
1403 | } |
1404 | } | |
1405 | ||
1406 | void pnv_pci_sriov_disable(struct pci_dev *pdev) | |
1407 | { | |
1408 | struct pci_bus *bus; | |
1409 | struct pci_controller *hose; | |
1410 | struct pnv_phb *phb; | |
1e916772 | 1411 | struct pnv_ioda_pe *pe; |
781a868f WY |
1412 | struct pci_dn *pdn; |
1413 | struct pci_sriov *iov; | |
be283eeb | 1414 | u16 num_vfs, i; |
781a868f WY |
1415 | |
1416 | bus = pdev->bus; | |
1417 | hose = pci_bus_to_host(bus); | |
1418 | phb = hose->private_data; | |
1419 | pdn = pci_get_pdn(pdev); | |
1420 | iov = pdev->sriov; | |
1421 | num_vfs = pdn->num_vfs; | |
1422 | ||
1423 | /* Release VF PEs */ | |
ee8222fe | 1424 | pnv_ioda_release_vf_PE(pdev); |
781a868f WY |
1425 | |
1426 | if (phb->type == PNV_PHB_IODA2) { | |
ee8222fe | 1427 | if (!pdn->m64_single_mode) |
be283eeb | 1428 | pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); |
781a868f WY |
1429 | |
1430 | /* Release M64 windows */ | |
ee8222fe | 1431 | pnv_pci_vf_release_m64(pdev, num_vfs); |
781a868f WY |
1432 | |
1433 | /* Release PE numbers */ | |
be283eeb WY |
1434 | if (pdn->m64_single_mode) { |
1435 | for (i = 0; i < num_vfs; i++) { | |
1e916772 GS |
1436 | if (pdn->pe_num_map[i] == IODA_INVALID_PE) |
1437 | continue; | |
1438 | ||
1439 | pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; | |
1440 | pnv_ioda_free_pe(pe); | |
be283eeb WY |
1441 | } |
1442 | } else | |
1443 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
1444 | /* Releasing pe_num_map */ | |
1445 | kfree(pdn->pe_num_map); | |
781a868f WY |
1446 | } |
1447 | } | |
1448 | ||
1449 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | |
1450 | struct pnv_ioda_pe *pe); | |
1451 | static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) | |
1452 | { | |
1453 | struct pci_bus *bus; | |
1454 | struct pci_controller *hose; | |
1455 | struct pnv_phb *phb; | |
1456 | struct pnv_ioda_pe *pe; | |
1457 | int pe_num; | |
1458 | u16 vf_index; | |
1459 | struct pci_dn *pdn; | |
1460 | ||
1461 | bus = pdev->bus; | |
1462 | hose = pci_bus_to_host(bus); | |
1463 | phb = hose->private_data; | |
1464 | pdn = pci_get_pdn(pdev); | |
1465 | ||
1466 | if (!pdev->is_physfn) | |
1467 | return; | |
1468 | ||
1469 | /* Reserve PE for each VF */ | |
1470 | for (vf_index = 0; vf_index < num_vfs; vf_index++) { | |
be283eeb WY |
1471 | if (pdn->m64_single_mode) |
1472 | pe_num = pdn->pe_num_map[vf_index]; | |
1473 | else | |
1474 | pe_num = *pdn->pe_num_map + vf_index; | |
781a868f WY |
1475 | |
1476 | pe = &phb->ioda.pe_array[pe_num]; | |
1477 | pe->pe_number = pe_num; | |
1478 | pe->phb = phb; | |
1479 | pe->flags = PNV_IODA_PE_VF; | |
1480 | pe->pbus = NULL; | |
1481 | pe->parent_dev = pdev; | |
781a868f WY |
1482 | pe->mve_number = -1; |
1483 | pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) | | |
1484 | pci_iov_virtfn_devfn(pdev, vf_index); | |
1485 | ||
1486 | pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n", | |
1487 | hose->global_number, pdev->bus->number, | |
1488 | PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), | |
1489 | PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num); | |
1490 | ||
1491 | if (pnv_ioda_configure_pe(phb, pe)) { | |
1492 | /* XXX What do we do here ? */ | |
1e916772 | 1493 | pnv_ioda_free_pe(pe); |
781a868f WY |
1494 | pe->pdev = NULL; |
1495 | continue; | |
1496 | } | |
1497 | ||
781a868f WY |
1498 | /* Put PE to the list */ |
1499 | mutex_lock(&phb->ioda.pe_list_mutex); | |
1500 | list_add_tail(&pe->list, &phb->ioda.pe_list); | |
1501 | mutex_unlock(&phb->ioda.pe_list_mutex); | |
1502 | ||
1503 | pnv_pci_ioda2_setup_dma_pe(phb, pe); | |
1504 | } | |
1505 | } | |
1506 | ||
1507 | int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | |
1508 | { | |
1509 | struct pci_bus *bus; | |
1510 | struct pci_controller *hose; | |
1511 | struct pnv_phb *phb; | |
1e916772 | 1512 | struct pnv_ioda_pe *pe; |
781a868f WY |
1513 | struct pci_dn *pdn; |
1514 | int ret; | |
be283eeb | 1515 | u16 i; |
781a868f WY |
1516 | |
1517 | bus = pdev->bus; | |
1518 | hose = pci_bus_to_host(bus); | |
1519 | phb = hose->private_data; | |
1520 | pdn = pci_get_pdn(pdev); | |
1521 | ||
1522 | if (phb->type == PNV_PHB_IODA2) { | |
b0331854 WY |
1523 | if (!pdn->vfs_expanded) { |
1524 | dev_info(&pdev->dev, "don't support this SRIOV device" | |
1525 | " with non 64bit-prefetchable IOV BAR\n"); | |
1526 | return -ENOSPC; | |
1527 | } | |
1528 | ||
ee8222fe WY |
1529 | /* |
1530 | * When M64 BARs functions in Single PE mode, the number of VFs | |
1531 | * could be enabled must be less than the number of M64 BARs. | |
1532 | */ | |
1533 | if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { | |
1534 | dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); | |
1535 | return -EBUSY; | |
1536 | } | |
1537 | ||
be283eeb WY |
1538 | /* Allocating pe_num_map */ |
1539 | if (pdn->m64_single_mode) | |
1540 | pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map) * num_vfs, | |
1541 | GFP_KERNEL); | |
1542 | else | |
1543 | pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); | |
1544 | ||
1545 | if (!pdn->pe_num_map) | |
1546 | return -ENOMEM; | |
1547 | ||
1548 | if (pdn->m64_single_mode) | |
1549 | for (i = 0; i < num_vfs; i++) | |
1550 | pdn->pe_num_map[i] = IODA_INVALID_PE; | |
1551 | ||
781a868f | 1552 | /* Calculate available PE for required VFs */ |
be283eeb WY |
1553 | if (pdn->m64_single_mode) { |
1554 | for (i = 0; i < num_vfs; i++) { | |
1e916772 GS |
1555 | pe = pnv_ioda_alloc_pe(phb); |
1556 | if (!pe) { | |
be283eeb WY |
1557 | ret = -EBUSY; |
1558 | goto m64_failed; | |
1559 | } | |
1e916772 GS |
1560 | |
1561 | pdn->pe_num_map[i] = pe->pe_number; | |
be283eeb WY |
1562 | } |
1563 | } else { | |
1564 | mutex_lock(&phb->ioda.pe_alloc_mutex); | |
1565 | *pdn->pe_num_map = bitmap_find_next_zero_area( | |
92b8f137 | 1566 | phb->ioda.pe_alloc, phb->ioda.total_pe_num, |
be283eeb | 1567 | 0, num_vfs, 0); |
92b8f137 | 1568 | if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { |
be283eeb WY |
1569 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
1570 | dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); | |
1571 | kfree(pdn->pe_num_map); | |
1572 | return -EBUSY; | |
1573 | } | |
1574 | bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
781a868f | 1575 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
781a868f | 1576 | } |
781a868f | 1577 | pdn->num_vfs = num_vfs; |
781a868f WY |
1578 | |
1579 | /* Assign M64 window accordingly */ | |
02639b0e | 1580 | ret = pnv_pci_vf_assign_m64(pdev, num_vfs); |
781a868f WY |
1581 | if (ret) { |
1582 | dev_info(&pdev->dev, "Not enough M64 window resources\n"); | |
1583 | goto m64_failed; | |
1584 | } | |
1585 | ||
1586 | /* | |
1587 | * When using one M64 BAR to map one IOV BAR, we need to shift | |
1588 | * the IOV BAR according to the PE# allocated to the VFs. | |
1589 | * Otherwise, the PE# for the VF will conflict with others. | |
1590 | */ | |
ee8222fe | 1591 | if (!pdn->m64_single_mode) { |
be283eeb | 1592 | ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); |
02639b0e WY |
1593 | if (ret) |
1594 | goto m64_failed; | |
1595 | } | |
781a868f WY |
1596 | } |
1597 | ||
1598 | /* Setup VF PEs */ | |
1599 | pnv_ioda_setup_vf_PE(pdev, num_vfs); | |
1600 | ||
1601 | return 0; | |
1602 | ||
1603 | m64_failed: | |
be283eeb WY |
1604 | if (pdn->m64_single_mode) { |
1605 | for (i = 0; i < num_vfs; i++) { | |
1e916772 GS |
1606 | if (pdn->pe_num_map[i] == IODA_INVALID_PE) |
1607 | continue; | |
1608 | ||
1609 | pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; | |
1610 | pnv_ioda_free_pe(pe); | |
be283eeb WY |
1611 | } |
1612 | } else | |
1613 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); | |
1614 | ||
1615 | /* Releasing pe_num_map */ | |
1616 | kfree(pdn->pe_num_map); | |
781a868f WY |
1617 | |
1618 | return ret; | |
1619 | } | |
1620 | ||
a8b2f828 GS |
1621 | int pcibios_sriov_disable(struct pci_dev *pdev) |
1622 | { | |
781a868f WY |
1623 | pnv_pci_sriov_disable(pdev); |
1624 | ||
a8b2f828 GS |
1625 | /* Release PCI data */ |
1626 | remove_dev_pci_data(pdev); | |
1627 | return 0; | |
1628 | } | |
1629 | ||
1630 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | |
1631 | { | |
1632 | /* Allocate PCI data */ | |
1633 | add_dev_pci_data(pdev); | |
781a868f | 1634 | |
ee8222fe | 1635 | return pnv_pci_sriov_enable(pdev, num_vfs); |
a8b2f828 GS |
1636 | } |
1637 | #endif /* CONFIG_PCI_IOV */ | |
1638 | ||
959c9bdd | 1639 | static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) |
184cd4a3 | 1640 | { |
b72c1f65 | 1641 | struct pci_dn *pdn = pci_get_pdn(pdev); |
959c9bdd | 1642 | struct pnv_ioda_pe *pe; |
184cd4a3 | 1643 | |
959c9bdd GS |
1644 | /* |
1645 | * The function can be called while the PE# | |
1646 | * hasn't been assigned. Do nothing for the | |
1647 | * case. | |
1648 | */ | |
1649 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) | |
1650 | return; | |
184cd4a3 | 1651 | |
959c9bdd | 1652 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
cd15b048 | 1653 | WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); |
0e1ffef0 | 1654 | set_dma_offset(&pdev->dev, pe->tce_bypass_base); |
b348aa65 | 1655 | set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); |
4617082e AK |
1656 | /* |
1657 | * Note: iommu_add_device() will fail here as | |
1658 | * for physical PE: the device is already added by now; | |
1659 | * for virtual PE: sysfs entries are not ready yet and | |
1660 | * tce_iommu_bus_notifier will add the device to a group later. | |
1661 | */ | |
184cd4a3 BH |
1662 | } |
1663 | ||
763d2d8d | 1664 | static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) |
cd15b048 | 1665 | { |
763d2d8d DA |
1666 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
1667 | struct pnv_phb *phb = hose->private_data; | |
cd15b048 BH |
1668 | struct pci_dn *pdn = pci_get_pdn(pdev); |
1669 | struct pnv_ioda_pe *pe; | |
1670 | uint64_t top; | |
1671 | bool bypass = false; | |
5d2aa710 AP |
1672 | struct pci_dev *linked_npu_dev; |
1673 | int i; | |
cd15b048 BH |
1674 | |
1675 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
1676 | return -ENODEV;; | |
1677 | ||
1678 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
1679 | if (pe->tce_bypass_enabled) { | |
1680 | top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; | |
1681 | bypass = (dma_mask >= top); | |
1682 | } | |
1683 | ||
1684 | if (bypass) { | |
1685 | dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); | |
1686 | set_dma_ops(&pdev->dev, &dma_direct_ops); | |
cd15b048 BH |
1687 | } else { |
1688 | dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); | |
1689 | set_dma_ops(&pdev->dev, &dma_iommu_ops); | |
cd15b048 | 1690 | } |
a32305bf | 1691 | *pdev->dev.dma_mask = dma_mask; |
5d2aa710 AP |
1692 | |
1693 | /* Update peer npu devices */ | |
1694 | if (pe->flags & PNV_IODA_PE_PEER) | |
419dbd5e AP |
1695 | for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { |
1696 | if (!pe->peers[i]) | |
1697 | continue; | |
1698 | ||
5d2aa710 AP |
1699 | linked_npu_dev = pe->peers[i]->pdev; |
1700 | if (dma_get_mask(&linked_npu_dev->dev) != dma_mask) | |
1701 | dma_set_mask(&linked_npu_dev->dev, dma_mask); | |
1702 | } | |
1703 | ||
cd15b048 BH |
1704 | return 0; |
1705 | } | |
1706 | ||
53522982 | 1707 | static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) |
fe7e85c6 | 1708 | { |
53522982 AD |
1709 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
1710 | struct pnv_phb *phb = hose->private_data; | |
fe7e85c6 GS |
1711 | struct pci_dn *pdn = pci_get_pdn(pdev); |
1712 | struct pnv_ioda_pe *pe; | |
1713 | u64 end, mask; | |
1714 | ||
1715 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) | |
1716 | return 0; | |
1717 | ||
1718 | pe = &phb->ioda.pe_array[pdn->pe_number]; | |
1719 | if (!pe->tce_bypass_enabled) | |
1720 | return __dma_get_required_mask(&pdev->dev); | |
1721 | ||
1722 | ||
1723 | end = pe->tce_bypass_base + memblock_end_of_DRAM(); | |
1724 | mask = 1ULL << (fls64(end) - 1); | |
1725 | mask += mask - 1; | |
1726 | ||
1727 | return mask; | |
1728 | } | |
1729 | ||
dff4a39e | 1730 | static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, |
ea30e99e | 1731 | struct pci_bus *bus) |
74251fe2 BH |
1732 | { |
1733 | struct pci_dev *dev; | |
1734 | ||
1735 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
b348aa65 | 1736 | set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); |
e91c2511 | 1737 | set_dma_offset(&dev->dev, pe->tce_bypass_base); |
4617082e | 1738 | iommu_add_device(&dev->dev); |
dff4a39e | 1739 | |
5c89a87d | 1740 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
ea30e99e | 1741 | pnv_ioda_setup_bus_dma(pe, dev->subordinate); |
74251fe2 BH |
1742 | } |
1743 | } | |
1744 | ||
decbda25 AK |
1745 | static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl, |
1746 | unsigned long index, unsigned long npages, bool rm) | |
4cce9550 | 1747 | { |
0eaf4def AK |
1748 | struct iommu_table_group_link *tgl = list_first_entry_or_null( |
1749 | &tbl->it_group_list, struct iommu_table_group_link, | |
1750 | next); | |
1751 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, | |
b348aa65 | 1752 | struct pnv_ioda_pe, table_group); |
3ad26e5c | 1753 | __be64 __iomem *invalidate = rm ? |
5780fb04 AK |
1754 | (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : |
1755 | pe->phb->ioda.tce_inval_reg; | |
4cce9550 | 1756 | unsigned long start, end, inc; |
b0376c9b | 1757 | const unsigned shift = tbl->it_page_shift; |
4cce9550 | 1758 | |
decbda25 AK |
1759 | start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); |
1760 | end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + | |
1761 | npages - 1); | |
4cce9550 GS |
1762 | |
1763 | /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */ | |
1764 | if (tbl->it_busno) { | |
b0376c9b AK |
1765 | start <<= shift; |
1766 | end <<= shift; | |
1767 | inc = 128ull << shift; | |
4cce9550 GS |
1768 | start |= tbl->it_busno; |
1769 | end |= tbl->it_busno; | |
1770 | } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) { | |
1771 | /* p7ioc-style invalidation, 2 TCEs per write */ | |
1772 | start |= (1ull << 63); | |
1773 | end |= (1ull << 63); | |
1774 | inc = 16; | |
1775 | } else { | |
1776 | /* Default (older HW) */ | |
1777 | inc = 128; | |
1778 | } | |
1779 | ||
1780 | end |= inc - 1; /* round up end to be different than start */ | |
1781 | ||
1782 | mb(); /* Ensure above stores are visible */ | |
1783 | while (start <= end) { | |
8e0a1611 | 1784 | if (rm) |
3ad26e5c | 1785 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 1786 | else |
3ad26e5c | 1787 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
1788 | start += inc; |
1789 | } | |
1790 | ||
1791 | /* | |
1792 | * The iommu layer will do another mb() for us on build() | |
1793 | * and we don't care on free() | |
1794 | */ | |
1795 | } | |
1796 | ||
decbda25 AK |
1797 | static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, |
1798 | long npages, unsigned long uaddr, | |
1799 | enum dma_data_direction direction, | |
1800 | struct dma_attrs *attrs) | |
1801 | { | |
1802 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, | |
1803 | attrs); | |
1804 | ||
1805 | if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) | |
1806 | pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); | |
1807 | ||
1808 | return ret; | |
1809 | } | |
1810 | ||
05c6cfb9 AK |
1811 | #ifdef CONFIG_IOMMU_API |
1812 | static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, | |
1813 | unsigned long *hpa, enum dma_data_direction *direction) | |
1814 | { | |
1815 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); | |
1816 | ||
1817 | if (!ret && (tbl->it_type & | |
1818 | (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) | |
1819 | pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false); | |
1820 | ||
1821 | return ret; | |
1822 | } | |
1823 | #endif | |
1824 | ||
decbda25 AK |
1825 | static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, |
1826 | long npages) | |
1827 | { | |
1828 | pnv_tce_free(tbl, index, npages); | |
1829 | ||
1830 | if (tbl->it_type & TCE_PCI_SWINV_FREE) | |
1831 | pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false); | |
1832 | } | |
1833 | ||
da004c36 | 1834 | static struct iommu_table_ops pnv_ioda1_iommu_ops = { |
decbda25 | 1835 | .set = pnv_ioda1_tce_build, |
05c6cfb9 AK |
1836 | #ifdef CONFIG_IOMMU_API |
1837 | .exchange = pnv_ioda1_tce_xchg, | |
1838 | #endif | |
decbda25 | 1839 | .clear = pnv_ioda1_tce_free, |
da004c36 AK |
1840 | .get = pnv_tce_get, |
1841 | }; | |
1842 | ||
5780fb04 AK |
1843 | static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe) |
1844 | { | |
1845 | /* 01xb - invalidate TCEs that match the specified PE# */ | |
1846 | unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF); | |
1847 | struct pnv_phb *phb = pe->phb; | |
5d2aa710 AP |
1848 | struct pnv_ioda_pe *npe; |
1849 | int i; | |
5780fb04 AK |
1850 | |
1851 | if (!phb->ioda.tce_inval_reg) | |
1852 | return; | |
1853 | ||
1854 | mb(); /* Ensure above stores are visible */ | |
1855 | __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg); | |
5d2aa710 AP |
1856 | |
1857 | if (pe->flags & PNV_IODA_PE_PEER) | |
1858 | for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { | |
1859 | npe = pe->peers[i]; | |
1860 | if (!npe || npe->phb->type != PNV_PHB_NPU) | |
1861 | continue; | |
1862 | ||
1863 | pnv_npu_tce_invalidate_entire(npe); | |
1864 | } | |
5780fb04 AK |
1865 | } |
1866 | ||
e57080f1 AK |
1867 | static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm, |
1868 | __be64 __iomem *invalidate, unsigned shift, | |
1869 | unsigned long index, unsigned long npages) | |
4cce9550 GS |
1870 | { |
1871 | unsigned long start, end, inc; | |
4cce9550 GS |
1872 | |
1873 | /* We'll invalidate DMA address in PE scope */ | |
b0376c9b | 1874 | start = 0x2ull << 60; |
e57080f1 | 1875 | start |= (pe_number & 0xFF); |
4cce9550 GS |
1876 | end = start; |
1877 | ||
1878 | /* Figure out the start, end and step */ | |
decbda25 AK |
1879 | start |= (index << shift); |
1880 | end |= ((index + npages - 1) << shift); | |
b0376c9b | 1881 | inc = (0x1ull << shift); |
4cce9550 GS |
1882 | mb(); |
1883 | ||
1884 | while (start <= end) { | |
8e0a1611 | 1885 | if (rm) |
3ad26e5c | 1886 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
8e0a1611 | 1887 | else |
3ad26e5c | 1888 | __raw_writeq(cpu_to_be64(start), invalidate); |
4cce9550 GS |
1889 | start += inc; |
1890 | } | |
1891 | } | |
1892 | ||
e57080f1 AK |
1893 | static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, |
1894 | unsigned long index, unsigned long npages, bool rm) | |
1895 | { | |
1896 | struct iommu_table_group_link *tgl; | |
1897 | ||
1898 | list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) { | |
5d2aa710 | 1899 | struct pnv_ioda_pe *npe; |
e57080f1 AK |
1900 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, |
1901 | struct pnv_ioda_pe, table_group); | |
1902 | __be64 __iomem *invalidate = rm ? | |
1903 | (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys : | |
1904 | pe->phb->ioda.tce_inval_reg; | |
5d2aa710 | 1905 | int i; |
e57080f1 AK |
1906 | |
1907 | pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm, | |
1908 | invalidate, tbl->it_page_shift, | |
1909 | index, npages); | |
5d2aa710 AP |
1910 | |
1911 | if (pe->flags & PNV_IODA_PE_PEER) | |
1912 | /* Invalidate PEs using the same TCE table */ | |
1913 | for (i = 0; i < PNV_IODA_MAX_PEER_PES; i++) { | |
1914 | npe = pe->peers[i]; | |
1915 | if (!npe || npe->phb->type != PNV_PHB_NPU) | |
1916 | continue; | |
1917 | ||
1918 | pnv_npu_tce_invalidate(npe, tbl, index, | |
1919 | npages, rm); | |
1920 | } | |
e57080f1 AK |
1921 | } |
1922 | } | |
1923 | ||
decbda25 AK |
1924 | static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, |
1925 | long npages, unsigned long uaddr, | |
1926 | enum dma_data_direction direction, | |
1927 | struct dma_attrs *attrs) | |
4cce9550 | 1928 | { |
decbda25 AK |
1929 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, |
1930 | attrs); | |
4cce9550 | 1931 | |
decbda25 AK |
1932 | if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE)) |
1933 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); | |
1934 | ||
1935 | return ret; | |
1936 | } | |
1937 | ||
05c6cfb9 AK |
1938 | #ifdef CONFIG_IOMMU_API |
1939 | static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, | |
1940 | unsigned long *hpa, enum dma_data_direction *direction) | |
1941 | { | |
1942 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); | |
1943 | ||
1944 | if (!ret && (tbl->it_type & | |
1945 | (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE))) | |
1946 | pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); | |
1947 | ||
1948 | return ret; | |
1949 | } | |
1950 | #endif | |
1951 | ||
decbda25 AK |
1952 | static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, |
1953 | long npages) | |
1954 | { | |
1955 | pnv_tce_free(tbl, index, npages); | |
1956 | ||
1957 | if (tbl->it_type & TCE_PCI_SWINV_FREE) | |
1958 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); | |
4cce9550 GS |
1959 | } |
1960 | ||
4793d65d AK |
1961 | static void pnv_ioda2_table_free(struct iommu_table *tbl) |
1962 | { | |
1963 | pnv_pci_ioda2_table_free_pages(tbl); | |
1964 | iommu_free_table(tbl, "pnv"); | |
1965 | } | |
1966 | ||
da004c36 | 1967 | static struct iommu_table_ops pnv_ioda2_iommu_ops = { |
decbda25 | 1968 | .set = pnv_ioda2_tce_build, |
05c6cfb9 AK |
1969 | #ifdef CONFIG_IOMMU_API |
1970 | .exchange = pnv_ioda2_tce_xchg, | |
1971 | #endif | |
decbda25 | 1972 | .clear = pnv_ioda2_tce_free, |
da004c36 | 1973 | .get = pnv_tce_get, |
4793d65d | 1974 | .free = pnv_ioda2_table_free, |
da004c36 AK |
1975 | }; |
1976 | ||
801846d1 GS |
1977 | static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) |
1978 | { | |
1979 | unsigned int *weight = (unsigned int *)data; | |
1980 | ||
1981 | /* This is quite simplistic. The "base" weight of a device | |
1982 | * is 10. 0 means no DMA is to be accounted for it. | |
1983 | */ | |
1984 | if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) | |
1985 | return 0; | |
1986 | ||
1987 | if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || | |
1988 | dev->class == PCI_CLASS_SERIAL_USB_OHCI || | |
1989 | dev->class == PCI_CLASS_SERIAL_USB_EHCI) | |
1990 | *weight += 3; | |
1991 | else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) | |
1992 | *weight += 15; | |
1993 | else | |
1994 | *weight += 10; | |
1995 | ||
1996 | return 0; | |
1997 | } | |
1998 | ||
1999 | static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) | |
2000 | { | |
2001 | unsigned int weight = 0; | |
2002 | ||
2003 | /* SRIOV VF has same DMA32 weight as its PF */ | |
2004 | #ifdef CONFIG_PCI_IOV | |
2005 | if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { | |
2006 | pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); | |
2007 | return weight; | |
2008 | } | |
2009 | #endif | |
2010 | ||
2011 | if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { | |
2012 | pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); | |
2013 | } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { | |
2014 | struct pci_dev *pdev; | |
2015 | ||
2016 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) | |
2017 | pnv_pci_ioda_dev_dma_weight(pdev, &weight); | |
2018 | } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { | |
2019 | pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); | |
2020 | } | |
2021 | ||
2022 | return weight; | |
2023 | } | |
2024 | ||
b30d936f | 2025 | static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, |
2b923ed1 | 2026 | struct pnv_ioda_pe *pe) |
184cd4a3 BH |
2027 | { |
2028 | ||
2029 | struct page *tce_mem = NULL; | |
184cd4a3 | 2030 | struct iommu_table *tbl; |
2b923ed1 GS |
2031 | unsigned int weight, total_weight = 0; |
2032 | unsigned int tce32_segsz, base, segs, avail, i; | |
184cd4a3 BH |
2033 | int64_t rc; |
2034 | void *addr; | |
2035 | ||
184cd4a3 BH |
2036 | /* XXX FIXME: Handle 64-bit only DMA devices */ |
2037 | /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ | |
2038 | /* XXX FIXME: Allocate multi-level tables on PHB3 */ | |
2b923ed1 GS |
2039 | weight = pnv_pci_ioda_pe_dma_weight(pe); |
2040 | if (!weight) | |
2041 | return; | |
2042 | ||
2043 | pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, | |
2044 | &total_weight); | |
2045 | segs = (weight * phb->ioda.dma32_count) / total_weight; | |
2046 | if (!segs) | |
2047 | segs = 1; | |
184cd4a3 | 2048 | |
2b923ed1 GS |
2049 | /* |
2050 | * Allocate contiguous DMA32 segments. We begin with the expected | |
2051 | * number of segments. With one more attempt, the number of DMA32 | |
2052 | * segments to be allocated is decreased by one until one segment | |
2053 | * is allocated successfully. | |
2054 | */ | |
2055 | do { | |
2056 | for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { | |
2057 | for (avail = 0, i = base; i < base + segs; i++) { | |
2058 | if (phb->ioda.dma32_segmap[i] == | |
2059 | IODA_INVALID_PE) | |
2060 | avail++; | |
2061 | } | |
2062 | ||
2063 | if (avail == segs) | |
2064 | goto found; | |
2065 | } | |
2066 | } while (--segs); | |
2067 | ||
2068 | if (!segs) { | |
2069 | pe_warn(pe, "No available DMA32 segments\n"); | |
2070 | return; | |
2071 | } | |
2072 | ||
2073 | found: | |
0eaf4def | 2074 | tbl = pnv_pci_table_alloc(phb->hose->node); |
b348aa65 AK |
2075 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
2076 | pe->pe_number); | |
0eaf4def | 2077 | pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); |
c5773822 | 2078 | |
184cd4a3 | 2079 | /* Grab a 32-bit TCE table */ |
2b923ed1 GS |
2080 | pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", |
2081 | weight, total_weight, base, segs); | |
184cd4a3 | 2082 | pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", |
acce971c GS |
2083 | base * PNV_IODA1_DMA32_SEGSIZE, |
2084 | (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); | |
184cd4a3 BH |
2085 | |
2086 | /* XXX Currently, we allocate one big contiguous table for the | |
2087 | * TCEs. We only really need one chunk per 256M of TCE space | |
2088 | * (ie per segment) but that's an optimization for later, it | |
2089 | * requires some added smarts with our get/put_tce implementation | |
acce971c GS |
2090 | * |
2091 | * Each TCE page is 4KB in size and each TCE entry occupies 8 | |
2092 | * bytes | |
184cd4a3 | 2093 | */ |
acce971c | 2094 | tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); |
184cd4a3 | 2095 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, |
acce971c | 2096 | get_order(tce32_segsz * segs)); |
184cd4a3 BH |
2097 | if (!tce_mem) { |
2098 | pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); | |
2099 | goto fail; | |
2100 | } | |
2101 | addr = page_address(tce_mem); | |
acce971c | 2102 | memset(addr, 0, tce32_segsz * segs); |
184cd4a3 BH |
2103 | |
2104 | /* Configure HW */ | |
2105 | for (i = 0; i < segs; i++) { | |
2106 | rc = opal_pci_map_pe_dma_window(phb->opal_id, | |
2107 | pe->pe_number, | |
2108 | base + i, 1, | |
acce971c GS |
2109 | __pa(addr) + tce32_segsz * i, |
2110 | tce32_segsz, IOMMU_PAGE_SIZE_4K); | |
184cd4a3 BH |
2111 | if (rc) { |
2112 | pe_err(pe, " Failed to configure 32-bit TCE table," | |
2113 | " err %ld\n", rc); | |
2114 | goto fail; | |
2115 | } | |
2116 | } | |
2117 | ||
2b923ed1 GS |
2118 | /* Setup DMA32 segment mapping */ |
2119 | for (i = base; i < base + segs; i++) | |
2120 | phb->ioda.dma32_segmap[i] = pe->pe_number; | |
2121 | ||
184cd4a3 | 2122 | /* Setup linux iommu table */ |
acce971c GS |
2123 | pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, |
2124 | base * PNV_IODA1_DMA32_SEGSIZE, | |
2125 | IOMMU_PAGE_SHIFT_4K); | |
184cd4a3 BH |
2126 | |
2127 | /* OPAL variant of P7IOC SW invalidated TCEs */ | |
5780fb04 | 2128 | if (phb->ioda.tce_inval_reg) |
65fd766b GS |
2129 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | |
2130 | TCE_PCI_SWINV_FREE | | |
2131 | TCE_PCI_SWINV_PAIR); | |
5780fb04 | 2132 | |
da004c36 | 2133 | tbl->it_ops = &pnv_ioda1_iommu_ops; |
4793d65d AK |
2134 | pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; |
2135 | pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; | |
184cd4a3 BH |
2136 | iommu_init_table(tbl, phb->hose->node); |
2137 | ||
781a868f | 2138 | if (pe->flags & PNV_IODA_PE_DEV) { |
4617082e AK |
2139 | /* |
2140 | * Setting table base here only for carrying iommu_group | |
2141 | * further down to let iommu_add_device() do the job. | |
2142 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. | |
2143 | */ | |
2144 | set_iommu_table_base(&pe->pdev->dev, tbl); | |
2145 | iommu_add_device(&pe->pdev->dev); | |
c5773822 | 2146 | } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
ea30e99e | 2147 | pnv_ioda_setup_bus_dma(pe, pe->pbus); |
74251fe2 | 2148 | |
184cd4a3 BH |
2149 | return; |
2150 | fail: | |
2151 | /* XXX Failure: Try to fallback to 64-bit only ? */ | |
184cd4a3 | 2152 | if (tce_mem) |
acce971c | 2153 | __free_pages(tce_mem, get_order(tce32_segsz * segs)); |
0eaf4def AK |
2154 | if (tbl) { |
2155 | pnv_pci_unlink_table_and_group(tbl, &pe->table_group); | |
2156 | iommu_free_table(tbl, "pnv"); | |
2157 | } | |
184cd4a3 BH |
2158 | } |
2159 | ||
43cb60ab AK |
2160 | static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, |
2161 | int num, struct iommu_table *tbl) | |
2162 | { | |
2163 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2164 | table_group); | |
2165 | struct pnv_phb *phb = pe->phb; | |
2166 | int64_t rc; | |
bbb845c4 AK |
2167 | const unsigned long size = tbl->it_indirect_levels ? |
2168 | tbl->it_level_size : tbl->it_size; | |
43cb60ab AK |
2169 | const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; |
2170 | const __u64 win_size = tbl->it_size << tbl->it_page_shift; | |
2171 | ||
4793d65d | 2172 | pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, |
43cb60ab AK |
2173 | start_addr, start_addr + win_size - 1, |
2174 | IOMMU_PAGE_SIZE(tbl)); | |
2175 | ||
2176 | /* | |
2177 | * Map TCE table through TVT. The TVE index is the PE number | |
2178 | * shifted by 1 bit for 32-bits DMA space. | |
2179 | */ | |
2180 | rc = opal_pci_map_pe_dma_window(phb->opal_id, | |
2181 | pe->pe_number, | |
4793d65d | 2182 | (pe->pe_number << 1) + num, |
bbb845c4 | 2183 | tbl->it_indirect_levels + 1, |
43cb60ab | 2184 | __pa(tbl->it_base), |
bbb845c4 | 2185 | size << 3, |
43cb60ab AK |
2186 | IOMMU_PAGE_SIZE(tbl)); |
2187 | if (rc) { | |
2188 | pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); | |
2189 | return rc; | |
2190 | } | |
2191 | ||
2192 | pnv_pci_link_table_and_group(phb->hose->node, num, | |
2193 | tbl, &pe->table_group); | |
2194 | pnv_pci_ioda2_tce_invalidate_entire(pe); | |
2195 | ||
2196 | return 0; | |
2197 | } | |
2198 | ||
f87a8864 | 2199 | static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) |
cd15b048 | 2200 | { |
cd15b048 BH |
2201 | uint16_t window_id = (pe->pe_number << 1 ) + 1; |
2202 | int64_t rc; | |
2203 | ||
2204 | pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); | |
2205 | if (enable) { | |
2206 | phys_addr_t top = memblock_end_of_DRAM(); | |
2207 | ||
2208 | top = roundup_pow_of_two(top); | |
2209 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
2210 | pe->pe_number, | |
2211 | window_id, | |
2212 | pe->tce_bypass_base, | |
2213 | top); | |
2214 | } else { | |
2215 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, | |
2216 | pe->pe_number, | |
2217 | window_id, | |
2218 | pe->tce_bypass_base, | |
2219 | 0); | |
cd15b048 BH |
2220 | } |
2221 | if (rc) | |
2222 | pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); | |
2223 | else | |
2224 | pe->tce_bypass_enabled = enable; | |
2225 | } | |
2226 | ||
4793d65d AK |
2227 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
2228 | __u32 page_shift, __u64 window_size, __u32 levels, | |
2229 | struct iommu_table *tbl); | |
2230 | ||
2231 | static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, | |
2232 | int num, __u32 page_shift, __u64 window_size, __u32 levels, | |
2233 | struct iommu_table **ptbl) | |
2234 | { | |
2235 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2236 | table_group); | |
2237 | int nid = pe->phb->hose->node; | |
2238 | __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; | |
2239 | long ret; | |
2240 | struct iommu_table *tbl; | |
2241 | ||
2242 | tbl = pnv_pci_table_alloc(nid); | |
2243 | if (!tbl) | |
2244 | return -ENOMEM; | |
2245 | ||
2246 | ret = pnv_pci_ioda2_table_alloc_pages(nid, | |
2247 | bus_offset, page_shift, window_size, | |
2248 | levels, tbl); | |
2249 | if (ret) { | |
2250 | iommu_free_table(tbl, "pnv"); | |
2251 | return ret; | |
2252 | } | |
2253 | ||
2254 | tbl->it_ops = &pnv_ioda2_iommu_ops; | |
2255 | if (pe->phb->ioda.tce_inval_reg) | |
2256 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); | |
2257 | ||
2258 | *ptbl = tbl; | |
2259 | ||
2260 | return 0; | |
2261 | } | |
2262 | ||
46d3e1e1 AK |
2263 | static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) |
2264 | { | |
2265 | struct iommu_table *tbl = NULL; | |
2266 | long rc; | |
2267 | ||
fa144869 NA |
2268 | /* |
2269 | * crashkernel= specifies the kdump kernel's maximum memory at | |
2270 | * some offset and there is no guaranteed the result is a power | |
2271 | * of 2, which will cause errors later. | |
2272 | */ | |
2273 | const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); | |
2274 | ||
bb005455 NA |
2275 | /* |
2276 | * In memory constrained environments, e.g. kdump kernel, the | |
2277 | * DMA window can be larger than available memory, which will | |
2278 | * cause errors later. | |
2279 | */ | |
fa144869 | 2280 | const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); |
bb005455 | 2281 | |
46d3e1e1 AK |
2282 | rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, |
2283 | IOMMU_PAGE_SHIFT_4K, | |
bb005455 | 2284 | window_size, |
46d3e1e1 AK |
2285 | POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); |
2286 | if (rc) { | |
2287 | pe_err(pe, "Failed to create 32-bit TCE table, err %ld", | |
2288 | rc); | |
2289 | return rc; | |
2290 | } | |
2291 | ||
2292 | iommu_init_table(tbl, pe->phb->hose->node); | |
2293 | ||
2294 | rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); | |
2295 | if (rc) { | |
2296 | pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", | |
2297 | rc); | |
2298 | pnv_ioda2_table_free(tbl); | |
2299 | return rc; | |
2300 | } | |
2301 | ||
2302 | if (!pnv_iommu_bypass_disabled) | |
2303 | pnv_pci_ioda2_set_bypass(pe, true); | |
2304 | ||
2305 | /* OPAL variant of PHB3 invalidated TCEs */ | |
2306 | if (pe->phb->ioda.tce_inval_reg) | |
2307 | tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE); | |
2308 | ||
2309 | /* | |
2310 | * Setting table base here only for carrying iommu_group | |
2311 | * further down to let iommu_add_device() do the job. | |
2312 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. | |
2313 | */ | |
2314 | if (pe->flags & PNV_IODA_PE_DEV) | |
2315 | set_iommu_table_base(&pe->pdev->dev, tbl); | |
2316 | ||
2317 | return 0; | |
2318 | } | |
2319 | ||
b5926430 AK |
2320 | #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) |
2321 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, | |
2322 | int num) | |
2323 | { | |
2324 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2325 | table_group); | |
2326 | struct pnv_phb *phb = pe->phb; | |
2327 | long ret; | |
2328 | ||
2329 | pe_info(pe, "Removing DMA window #%d\n", num); | |
2330 | ||
2331 | ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, | |
2332 | (pe->pe_number << 1) + num, | |
2333 | 0/* levels */, 0/* table address */, | |
2334 | 0/* table size */, 0/* page size */); | |
2335 | if (ret) | |
2336 | pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); | |
2337 | else | |
2338 | pnv_pci_ioda2_tce_invalidate_entire(pe); | |
2339 | ||
2340 | pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); | |
2341 | ||
2342 | return ret; | |
2343 | } | |
2344 | #endif | |
2345 | ||
f87a8864 | 2346 | #ifdef CONFIG_IOMMU_API |
00547193 AK |
2347 | static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, |
2348 | __u64 window_size, __u32 levels) | |
2349 | { | |
2350 | unsigned long bytes = 0; | |
2351 | const unsigned window_shift = ilog2(window_size); | |
2352 | unsigned entries_shift = window_shift - page_shift; | |
2353 | unsigned table_shift = entries_shift + 3; | |
2354 | unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); | |
2355 | unsigned long direct_table_size; | |
2356 | ||
2357 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || | |
2358 | (window_size > memory_hotplug_max()) || | |
2359 | !is_power_of_2(window_size)) | |
2360 | return 0; | |
2361 | ||
2362 | /* Calculate a direct table size from window_size and levels */ | |
2363 | entries_shift = (entries_shift + levels - 1) / levels; | |
2364 | table_shift = entries_shift + 3; | |
2365 | table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); | |
2366 | direct_table_size = 1UL << table_shift; | |
2367 | ||
2368 | for ( ; levels; --levels) { | |
2369 | bytes += _ALIGN_UP(tce_table_size, direct_table_size); | |
2370 | ||
2371 | tce_table_size /= direct_table_size; | |
2372 | tce_table_size <<= 3; | |
2373 | tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size); | |
2374 | } | |
2375 | ||
2376 | return bytes; | |
2377 | } | |
2378 | ||
f87a8864 | 2379 | static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) |
cd15b048 | 2380 | { |
f87a8864 AK |
2381 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
2382 | table_group); | |
46d3e1e1 AK |
2383 | /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ |
2384 | struct iommu_table *tbl = pe->table_group.tables[0]; | |
cd15b048 | 2385 | |
f87a8864 | 2386 | pnv_pci_ioda2_set_bypass(pe, false); |
46d3e1e1 AK |
2387 | pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
2388 | pnv_ioda2_table_free(tbl); | |
f87a8864 | 2389 | } |
cd15b048 | 2390 | |
f87a8864 AK |
2391 | static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) |
2392 | { | |
2393 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, | |
2394 | table_group); | |
2395 | ||
46d3e1e1 | 2396 | pnv_pci_ioda2_setup_default_config(pe); |
cd15b048 BH |
2397 | } |
2398 | ||
f87a8864 | 2399 | static struct iommu_table_group_ops pnv_pci_ioda2_ops = { |
00547193 | 2400 | .get_table_size = pnv_pci_ioda2_get_table_size, |
4793d65d AK |
2401 | .create_table = pnv_pci_ioda2_create_table, |
2402 | .set_window = pnv_pci_ioda2_set_window, | |
2403 | .unset_window = pnv_pci_ioda2_unset_window, | |
f87a8864 AK |
2404 | .take_ownership = pnv_ioda2_take_ownership, |
2405 | .release_ownership = pnv_ioda2_release_ownership, | |
2406 | }; | |
2407 | #endif | |
2408 | ||
5780fb04 AK |
2409 | static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb) |
2410 | { | |
2411 | const __be64 *swinvp; | |
2412 | ||
2413 | /* OPAL variant of PHB3 invalidated TCEs */ | |
2414 | swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL); | |
2415 | if (!swinvp) | |
2416 | return; | |
2417 | ||
2418 | phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp); | |
2419 | phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8); | |
2420 | } | |
2421 | ||
bbb845c4 AK |
2422 | static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, |
2423 | unsigned levels, unsigned long limit, | |
3ba3a73e | 2424 | unsigned long *current_offset, unsigned long *total_allocated) |
373f5657 GS |
2425 | { |
2426 | struct page *tce_mem = NULL; | |
bbb845c4 | 2427 | __be64 *addr, *tmp; |
aca6913f | 2428 | unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; |
bbb845c4 AK |
2429 | unsigned long allocated = 1UL << (order + PAGE_SHIFT); |
2430 | unsigned entries = 1UL << (shift - 3); | |
2431 | long i; | |
aca6913f AK |
2432 | |
2433 | tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); | |
2434 | if (!tce_mem) { | |
2435 | pr_err("Failed to allocate a TCE memory, order=%d\n", order); | |
2436 | return NULL; | |
2437 | } | |
2438 | addr = page_address(tce_mem); | |
bbb845c4 | 2439 | memset(addr, 0, allocated); |
3ba3a73e | 2440 | *total_allocated += allocated; |
bbb845c4 AK |
2441 | |
2442 | --levels; | |
2443 | if (!levels) { | |
2444 | *current_offset += allocated; | |
2445 | return addr; | |
2446 | } | |
2447 | ||
2448 | for (i = 0; i < entries; ++i) { | |
2449 | tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, | |
3ba3a73e | 2450 | levels, limit, current_offset, total_allocated); |
bbb845c4 AK |
2451 | if (!tmp) |
2452 | break; | |
2453 | ||
2454 | addr[i] = cpu_to_be64(__pa(tmp) | | |
2455 | TCE_PCI_READ | TCE_PCI_WRITE); | |
2456 | ||
2457 | if (*current_offset >= limit) | |
2458 | break; | |
2459 | } | |
aca6913f AK |
2460 | |
2461 | return addr; | |
2462 | } | |
2463 | ||
bbb845c4 AK |
2464 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
2465 | unsigned long size, unsigned level); | |
2466 | ||
aca6913f | 2467 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
bbb845c4 AK |
2468 | __u32 page_shift, __u64 window_size, __u32 levels, |
2469 | struct iommu_table *tbl) | |
aca6913f | 2470 | { |
373f5657 | 2471 | void *addr; |
3ba3a73e | 2472 | unsigned long offset = 0, level_shift, total_allocated = 0; |
aca6913f AK |
2473 | const unsigned window_shift = ilog2(window_size); |
2474 | unsigned entries_shift = window_shift - page_shift; | |
2475 | unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); | |
2476 | const unsigned long tce_table_size = 1UL << table_shift; | |
2477 | ||
bbb845c4 AK |
2478 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) |
2479 | return -EINVAL; | |
2480 | ||
aca6913f AK |
2481 | if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) |
2482 | return -EINVAL; | |
2483 | ||
bbb845c4 AK |
2484 | /* Adjust direct table size from window_size and levels */ |
2485 | entries_shift = (entries_shift + levels - 1) / levels; | |
2486 | level_shift = entries_shift + 3; | |
2487 | level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); | |
2488 | ||
aca6913f | 2489 | /* Allocate TCE table */ |
bbb845c4 | 2490 | addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, |
3ba3a73e | 2491 | levels, tce_table_size, &offset, &total_allocated); |
bbb845c4 AK |
2492 | |
2493 | /* addr==NULL means that the first level allocation failed */ | |
aca6913f AK |
2494 | if (!addr) |
2495 | return -ENOMEM; | |
2496 | ||
bbb845c4 AK |
2497 | /* |
2498 | * First level was allocated but some lower level failed as | |
2499 | * we did not allocate as much as we wanted, | |
2500 | * release partially allocated table. | |
2501 | */ | |
2502 | if (offset < tce_table_size) { | |
2503 | pnv_pci_ioda2_table_do_free_pages(addr, | |
2504 | 1ULL << (level_shift - 3), levels - 1); | |
2505 | return -ENOMEM; | |
2506 | } | |
2507 | ||
aca6913f AK |
2508 | /* Setup linux iommu table */ |
2509 | pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, | |
2510 | page_shift); | |
bbb845c4 AK |
2511 | tbl->it_level_size = 1ULL << (level_shift - 3); |
2512 | tbl->it_indirect_levels = levels - 1; | |
3ba3a73e | 2513 | tbl->it_allocated_size = total_allocated; |
aca6913f AK |
2514 | |
2515 | pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", | |
2516 | window_size, tce_table_size, bus_offset); | |
2517 | ||
2518 | return 0; | |
2519 | } | |
2520 | ||
bbb845c4 AK |
2521 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
2522 | unsigned long size, unsigned level) | |
2523 | { | |
2524 | const unsigned long addr_ul = (unsigned long) addr & | |
2525 | ~(TCE_PCI_READ | TCE_PCI_WRITE); | |
2526 | ||
2527 | if (level) { | |
2528 | long i; | |
2529 | u64 *tmp = (u64 *) addr_ul; | |
2530 | ||
2531 | for (i = 0; i < size; ++i) { | |
2532 | unsigned long hpa = be64_to_cpu(tmp[i]); | |
2533 | ||
2534 | if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) | |
2535 | continue; | |
2536 | ||
2537 | pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, | |
2538 | level - 1); | |
2539 | } | |
2540 | } | |
2541 | ||
2542 | free_pages(addr_ul, get_order(size << 3)); | |
2543 | } | |
2544 | ||
aca6913f AK |
2545 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) |
2546 | { | |
bbb845c4 AK |
2547 | const unsigned long size = tbl->it_indirect_levels ? |
2548 | tbl->it_level_size : tbl->it_size; | |
2549 | ||
aca6913f AK |
2550 | if (!tbl->it_size) |
2551 | return; | |
2552 | ||
bbb845c4 AK |
2553 | pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, |
2554 | tbl->it_indirect_levels); | |
aca6913f AK |
2555 | } |
2556 | ||
2557 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, | |
2558 | struct pnv_ioda_pe *pe) | |
2559 | { | |
373f5657 GS |
2560 | int64_t rc; |
2561 | ||
f87a8864 AK |
2562 | /* TVE #1 is selected by PCI address bit 59 */ |
2563 | pe->tce_bypass_base = 1ull << 59; | |
2564 | ||
b348aa65 AK |
2565 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
2566 | pe->pe_number); | |
c5773822 | 2567 | |
373f5657 | 2568 | /* The PE will reserve all possible 32-bits space */ |
373f5657 | 2569 | pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", |
aca6913f | 2570 | phb->ioda.m32_pci_base); |
373f5657 | 2571 | |
aca6913f | 2572 | /* Setup linux iommu table */ |
4793d65d AK |
2573 | pe->table_group.tce32_start = 0; |
2574 | pe->table_group.tce32_size = phb->ioda.m32_pci_base; | |
2575 | pe->table_group.max_dynamic_windows_supported = | |
2576 | IOMMU_TABLE_GROUP_MAX_TABLES; | |
2577 | pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; | |
2578 | pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; | |
e5aad1e6 AK |
2579 | #ifdef CONFIG_IOMMU_API |
2580 | pe->table_group.ops = &pnv_pci_ioda2_ops; | |
2581 | #endif | |
2582 | ||
46d3e1e1 | 2583 | rc = pnv_pci_ioda2_setup_default_config(pe); |
801846d1 | 2584 | if (rc) |
46d3e1e1 | 2585 | return; |
373f5657 | 2586 | |
46d3e1e1 | 2587 | if (pe->flags & PNV_IODA_PE_DEV) |
4617082e | 2588 | iommu_add_device(&pe->pdev->dev); |
46d3e1e1 | 2589 | else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
ea30e99e | 2590 | pnv_ioda_setup_bus_dma(pe, pe->pbus); |
373f5657 GS |
2591 | } |
2592 | ||
cad5cef6 | 2593 | static void pnv_ioda_setup_dma(struct pnv_phb *phb) |
184cd4a3 BH |
2594 | { |
2595 | struct pci_controller *hose = phb->hose; | |
184cd4a3 | 2596 | struct pnv_ioda_pe *pe; |
2b923ed1 | 2597 | unsigned int weight; |
801846d1 | 2598 | |
184cd4a3 BH |
2599 | /* If we have more PE# than segments available, hand out one |
2600 | * per PE until we run out and let the rest fail. If not, | |
2601 | * then we assign at least one segment per PE, plus more based | |
2602 | * on the amount of devices under that PE | |
2603 | */ | |
2b923ed1 GS |
2604 | pr_info("PCI: Domain %04x has %d available 32-bit DMA segments\n", |
2605 | hose->global_number, phb->ioda.dma32_count); | |
184cd4a3 | 2606 | |
5780fb04 AK |
2607 | pnv_pci_ioda_setup_opal_tce_kill(phb); |
2608 | ||
2b923ed1 | 2609 | /* Walk our PE list and configure their DMA segments */ |
801846d1 GS |
2610 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { |
2611 | weight = pnv_pci_ioda_pe_dma_weight(pe); | |
2612 | if (!weight) | |
184cd4a3 | 2613 | continue; |
801846d1 | 2614 | |
373f5657 GS |
2615 | /* |
2616 | * For IODA2 compliant PHB3, we needn't care about the weight. | |
2617 | * The all available 32-bits DMA space will be assigned to | |
2618 | * the specific PE. | |
2619 | */ | |
2620 | if (phb->type == PNV_PHB_IODA1) { | |
2b923ed1 | 2621 | pnv_pci_ioda1_setup_dma_pe(phb, pe); |
5d2aa710 | 2622 | } else if (phb->type == PNV_PHB_IODA2) { |
373f5657 | 2623 | pe_info(pe, "Assign DMA32 space\n"); |
373f5657 | 2624 | pnv_pci_ioda2_setup_dma_pe(phb, pe); |
5d2aa710 AP |
2625 | } else if (phb->type == PNV_PHB_NPU) { |
2626 | /* | |
2627 | * We initialise the DMA space for an NPU PHB | |
2628 | * after setup of the PHB is complete as we | |
2629 | * point the NPU TVT to the the same location | |
2630 | * as the PHB3 TVT. | |
2631 | */ | |
373f5657 | 2632 | } |
184cd4a3 BH |
2633 | } |
2634 | } | |
2635 | ||
2636 | #ifdef CONFIG_PCI_MSI | |
137436c9 GS |
2637 | static void pnv_ioda2_msi_eoi(struct irq_data *d) |
2638 | { | |
2639 | unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); | |
2640 | struct irq_chip *chip = irq_data_get_irq_chip(d); | |
2641 | struct pnv_phb *phb = container_of(chip, struct pnv_phb, | |
2642 | ioda.irq_chip); | |
2643 | int64_t rc; | |
2644 | ||
2645 | rc = opal_pci_msi_eoi(phb->opal_id, hw_irq); | |
2646 | WARN_ON_ONCE(rc); | |
2647 | ||
2648 | icp_native_eoi(d); | |
2649 | } | |
2650 | ||
fd9a1c26 IM |
2651 | |
2652 | static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) | |
2653 | { | |
2654 | struct irq_data *idata; | |
2655 | struct irq_chip *ichip; | |
2656 | ||
2657 | if (phb->type != PNV_PHB_IODA2) | |
2658 | return; | |
2659 | ||
2660 | if (!phb->ioda.irq_chip_init) { | |
2661 | /* | |
2662 | * First time we setup an MSI IRQ, we need to setup the | |
2663 | * corresponding IRQ chip to route correctly. | |
2664 | */ | |
2665 | idata = irq_get_irq_data(virq); | |
2666 | ichip = irq_data_get_irq_chip(idata); | |
2667 | phb->ioda.irq_chip_init = 1; | |
2668 | phb->ioda.irq_chip = *ichip; | |
2669 | phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; | |
2670 | } | |
2671 | irq_set_chip(virq, &phb->ioda.irq_chip); | |
2672 | } | |
2673 | ||
80c49c7e IM |
2674 | #ifdef CONFIG_CXL_BASE |
2675 | ||
6f963ec2 | 2676 | struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev) |
80c49c7e IM |
2677 | { |
2678 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2679 | ||
6f963ec2 | 2680 | return of_node_get(hose->dn); |
80c49c7e | 2681 | } |
6f963ec2 | 2682 | EXPORT_SYMBOL(pnv_pci_get_phb_node); |
80c49c7e | 2683 | |
1212aa1c | 2684 | int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode) |
80c49c7e IM |
2685 | { |
2686 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2687 | struct pnv_phb *phb = hose->private_data; | |
2688 | struct pnv_ioda_pe *pe; | |
2689 | int rc; | |
2690 | ||
2691 | pe = pnv_ioda_get_pe(dev); | |
2692 | if (!pe) | |
2693 | return -ENODEV; | |
2694 | ||
2695 | pe_info(pe, "Switching PHB to CXL\n"); | |
2696 | ||
1212aa1c | 2697 | rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); |
80c49c7e IM |
2698 | if (rc) |
2699 | dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); | |
2700 | ||
2701 | return rc; | |
2702 | } | |
1212aa1c | 2703 | EXPORT_SYMBOL(pnv_phb_to_cxl_mode); |
80c49c7e IM |
2704 | |
2705 | /* Find PHB for cxl dev and allocate MSI hwirqs? | |
2706 | * Returns the absolute hardware IRQ number | |
2707 | */ | |
2708 | int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num) | |
2709 | { | |
2710 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2711 | struct pnv_phb *phb = hose->private_data; | |
2712 | int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num); | |
2713 | ||
2714 | if (hwirq < 0) { | |
2715 | dev_warn(&dev->dev, "Failed to find a free MSI\n"); | |
2716 | return -ENOSPC; | |
2717 | } | |
2718 | ||
2719 | return phb->msi_base + hwirq; | |
2720 | } | |
2721 | EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs); | |
2722 | ||
2723 | void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num) | |
2724 | { | |
2725 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2726 | struct pnv_phb *phb = hose->private_data; | |
2727 | ||
2728 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num); | |
2729 | } | |
2730 | EXPORT_SYMBOL(pnv_cxl_release_hwirqs); | |
2731 | ||
2732 | void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, | |
2733 | struct pci_dev *dev) | |
2734 | { | |
2735 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2736 | struct pnv_phb *phb = hose->private_data; | |
2737 | int i, hwirq; | |
2738 | ||
2739 | for (i = 1; i < CXL_IRQ_RANGES; i++) { | |
2740 | if (!irqs->range[i]) | |
2741 | continue; | |
2742 | pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n", | |
2743 | i, irqs->offset[i], | |
2744 | irqs->range[i]); | |
2745 | hwirq = irqs->offset[i] - phb->msi_base; | |
2746 | msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, | |
2747 | irqs->range[i]); | |
2748 | } | |
2749 | } | |
2750 | EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges); | |
2751 | ||
2752 | int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, | |
2753 | struct pci_dev *dev, int num) | |
2754 | { | |
2755 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2756 | struct pnv_phb *phb = hose->private_data; | |
2757 | int i, hwirq, try; | |
2758 | ||
2759 | memset(irqs, 0, sizeof(struct cxl_irq_ranges)); | |
2760 | ||
2761 | /* 0 is reserved for the multiplexed PSL DSI interrupt */ | |
2762 | for (i = 1; i < CXL_IRQ_RANGES && num; i++) { | |
2763 | try = num; | |
2764 | while (try) { | |
2765 | hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try); | |
2766 | if (hwirq >= 0) | |
2767 | break; | |
2768 | try /= 2; | |
2769 | } | |
2770 | if (!try) | |
2771 | goto fail; | |
2772 | ||
2773 | irqs->offset[i] = phb->msi_base + hwirq; | |
2774 | irqs->range[i] = try; | |
2775 | pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n", | |
2776 | i, irqs->offset[i], irqs->range[i]); | |
2777 | num -= try; | |
2778 | } | |
2779 | if (num) | |
2780 | goto fail; | |
2781 | ||
2782 | return 0; | |
2783 | fail: | |
2784 | pnv_cxl_release_hwirq_ranges(irqs, dev); | |
2785 | return -ENOSPC; | |
2786 | } | |
2787 | EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges); | |
2788 | ||
2789 | int pnv_cxl_get_irq_count(struct pci_dev *dev) | |
2790 | { | |
2791 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2792 | struct pnv_phb *phb = hose->private_data; | |
2793 | ||
2794 | return phb->msi_bmp.irq_count; | |
2795 | } | |
2796 | EXPORT_SYMBOL(pnv_cxl_get_irq_count); | |
2797 | ||
2798 | int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, | |
2799 | unsigned int virq) | |
2800 | { | |
2801 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
2802 | struct pnv_phb *phb = hose->private_data; | |
2803 | unsigned int xive_num = hwirq - phb->msi_base; | |
2804 | struct pnv_ioda_pe *pe; | |
2805 | int rc; | |
2806 | ||
2807 | if (!(pe = pnv_ioda_get_pe(dev))) | |
2808 | return -ENODEV; | |
2809 | ||
2810 | /* Assign XIVE to PE */ | |
2811 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); | |
2812 | if (rc) { | |
2813 | pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x " | |
2814 | "hwirq 0x%x XIVE 0x%x PE\n", | |
2815 | pci_name(dev), rc, phb->msi_base, hwirq, xive_num); | |
2816 | return -EIO; | |
2817 | } | |
2818 | set_msi_irq_chip(phb, virq); | |
2819 | ||
2820 | return 0; | |
2821 | } | |
2822 | EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup); | |
2823 | #endif | |
2824 | ||
184cd4a3 | 2825 | static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, |
137436c9 GS |
2826 | unsigned int hwirq, unsigned int virq, |
2827 | unsigned int is_64, struct msi_msg *msg) | |
184cd4a3 BH |
2828 | { |
2829 | struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); | |
2830 | unsigned int xive_num = hwirq - phb->msi_base; | |
3a1a4661 | 2831 | __be32 data; |
184cd4a3 BH |
2832 | int rc; |
2833 | ||
2834 | /* No PE assigned ? bail out ... no MSI for you ! */ | |
2835 | if (pe == NULL) | |
2836 | return -ENXIO; | |
2837 | ||
2838 | /* Check if we have an MVE */ | |
2839 | if (pe->mve_number < 0) | |
2840 | return -ENXIO; | |
2841 | ||
b72c1f65 | 2842 | /* Force 32-bit MSI on some broken devices */ |
36074381 | 2843 | if (dev->no_64bit_msi) |
b72c1f65 BH |
2844 | is_64 = 0; |
2845 | ||
184cd4a3 BH |
2846 | /* Assign XIVE to PE */ |
2847 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); | |
2848 | if (rc) { | |
2849 | pr_warn("%s: OPAL error %d setting XIVE %d PE\n", | |
2850 | pci_name(dev), rc, xive_num); | |
2851 | return -EIO; | |
2852 | } | |
2853 | ||
2854 | if (is_64) { | |
3a1a4661 BH |
2855 | __be64 addr64; |
2856 | ||
184cd4a3 BH |
2857 | rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, |
2858 | &addr64, &data); | |
2859 | if (rc) { | |
2860 | pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", | |
2861 | pci_name(dev), rc); | |
2862 | return -EIO; | |
2863 | } | |
3a1a4661 BH |
2864 | msg->address_hi = be64_to_cpu(addr64) >> 32; |
2865 | msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; | |
184cd4a3 | 2866 | } else { |
3a1a4661 BH |
2867 | __be32 addr32; |
2868 | ||
184cd4a3 BH |
2869 | rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, |
2870 | &addr32, &data); | |
2871 | if (rc) { | |
2872 | pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", | |
2873 | pci_name(dev), rc); | |
2874 | return -EIO; | |
2875 | } | |
2876 | msg->address_hi = 0; | |
3a1a4661 | 2877 | msg->address_lo = be32_to_cpu(addr32); |
184cd4a3 | 2878 | } |
3a1a4661 | 2879 | msg->data = be32_to_cpu(data); |
184cd4a3 | 2880 | |
fd9a1c26 | 2881 | set_msi_irq_chip(phb, virq); |
137436c9 | 2882 | |
184cd4a3 BH |
2883 | pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," |
2884 | " address=%x_%08x data=%x PE# %d\n", | |
2885 | pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, | |
2886 | msg->address_hi, msg->address_lo, data, pe->pe_number); | |
2887 | ||
2888 | return 0; | |
2889 | } | |
2890 | ||
2891 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) | |
2892 | { | |
fb1b55d6 | 2893 | unsigned int count; |
184cd4a3 BH |
2894 | const __be32 *prop = of_get_property(phb->hose->dn, |
2895 | "ibm,opal-msi-ranges", NULL); | |
2896 | if (!prop) { | |
2897 | /* BML Fallback */ | |
2898 | prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); | |
2899 | } | |
2900 | if (!prop) | |
2901 | return; | |
2902 | ||
2903 | phb->msi_base = be32_to_cpup(prop); | |
fb1b55d6 GS |
2904 | count = be32_to_cpup(prop + 1); |
2905 | if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { | |
184cd4a3 BH |
2906 | pr_err("PCI %d: Failed to allocate MSI bitmap !\n", |
2907 | phb->hose->global_number); | |
2908 | return; | |
2909 | } | |
fb1b55d6 | 2910 | |
184cd4a3 BH |
2911 | phb->msi_setup = pnv_pci_ioda_msi_setup; |
2912 | phb->msi32_support = 1; | |
2913 | pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", | |
fb1b55d6 | 2914 | count, phb->msi_base); |
184cd4a3 BH |
2915 | } |
2916 | #else | |
2917 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } | |
2918 | #endif /* CONFIG_PCI_MSI */ | |
2919 | ||
6e628c7d WY |
2920 | #ifdef CONFIG_PCI_IOV |
2921 | static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) | |
2922 | { | |
f2dd0afe WY |
2923 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
2924 | struct pnv_phb *phb = hose->private_data; | |
2925 | const resource_size_t gate = phb->ioda.m64_segsize >> 2; | |
6e628c7d WY |
2926 | struct resource *res; |
2927 | int i; | |
dfcc8d45 | 2928 | resource_size_t size, total_vf_bar_sz; |
6e628c7d | 2929 | struct pci_dn *pdn; |
5b88ec22 | 2930 | int mul, total_vfs; |
6e628c7d WY |
2931 | |
2932 | if (!pdev->is_physfn || pdev->is_added) | |
2933 | return; | |
2934 | ||
6e628c7d WY |
2935 | pdn = pci_get_pdn(pdev); |
2936 | pdn->vfs_expanded = 0; | |
ee8222fe | 2937 | pdn->m64_single_mode = false; |
6e628c7d | 2938 | |
5b88ec22 | 2939 | total_vfs = pci_sriov_get_totalvfs(pdev); |
92b8f137 | 2940 | mul = phb->ioda.total_pe_num; |
dfcc8d45 | 2941 | total_vf_bar_sz = 0; |
5b88ec22 WY |
2942 | |
2943 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
2944 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
2945 | if (!res->flags || res->parent) | |
2946 | continue; | |
2947 | if (!pnv_pci_is_mem_pref_64(res->flags)) { | |
b0331854 WY |
2948 | dev_warn(&pdev->dev, "Don't support SR-IOV with" |
2949 | " non M64 VF BAR%d: %pR. \n", | |
5b88ec22 | 2950 | i, res); |
b0331854 | 2951 | goto truncate_iov; |
5b88ec22 WY |
2952 | } |
2953 | ||
dfcc8d45 WY |
2954 | total_vf_bar_sz += pci_iov_resource_size(pdev, |
2955 | i + PCI_IOV_RESOURCES); | |
5b88ec22 | 2956 | |
f2dd0afe WY |
2957 | /* |
2958 | * If bigger than quarter of M64 segment size, just round up | |
2959 | * power of two. | |
2960 | * | |
2961 | * Generally, one M64 BAR maps one IOV BAR. To avoid conflict | |
2962 | * with other devices, IOV BAR size is expanded to be | |
2963 | * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 | |
2964 | * segment size , the expanded size would equal to half of the | |
2965 | * whole M64 space size, which will exhaust the M64 Space and | |
2966 | * limit the system flexibility. This is a design decision to | |
2967 | * set the boundary to quarter of the M64 segment size. | |
2968 | */ | |
dfcc8d45 | 2969 | if (total_vf_bar_sz > gate) { |
5b88ec22 | 2970 | mul = roundup_pow_of_two(total_vfs); |
dfcc8d45 WY |
2971 | dev_info(&pdev->dev, |
2972 | "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", | |
2973 | total_vf_bar_sz, gate, mul); | |
ee8222fe | 2974 | pdn->m64_single_mode = true; |
5b88ec22 WY |
2975 | break; |
2976 | } | |
2977 | } | |
2978 | ||
6e628c7d WY |
2979 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
2980 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
2981 | if (!res->flags || res->parent) | |
2982 | continue; | |
6e628c7d | 2983 | |
6e628c7d | 2984 | size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); |
ee8222fe WY |
2985 | /* |
2986 | * On PHB3, the minimum size alignment of M64 BAR in single | |
2987 | * mode is 32MB. | |
2988 | */ | |
2989 | if (pdn->m64_single_mode && (size < SZ_32M)) | |
2990 | goto truncate_iov; | |
2991 | dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); | |
5b88ec22 | 2992 | res->end = res->start + size * mul - 1; |
6e628c7d WY |
2993 | dev_dbg(&pdev->dev, " %pR\n", res); |
2994 | dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", | |
5b88ec22 | 2995 | i, res, mul); |
6e628c7d | 2996 | } |
5b88ec22 | 2997 | pdn->vfs_expanded = mul; |
b0331854 WY |
2998 | |
2999 | return; | |
3000 | ||
3001 | truncate_iov: | |
3002 | /* To save MMIO space, IOV BAR is truncated. */ | |
3003 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { | |
3004 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; | |
3005 | res->flags = 0; | |
3006 | res->end = res->start - 1; | |
3007 | } | |
6e628c7d WY |
3008 | } |
3009 | #endif /* CONFIG_PCI_IOV */ | |
3010 | ||
23e79425 GS |
3011 | static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, |
3012 | struct resource *res) | |
3013 | { | |
3014 | struct pnv_phb *phb = pe->phb; | |
3015 | struct pci_bus_region region; | |
3016 | int index; | |
3017 | int64_t rc; | |
3018 | ||
3019 | if (!res || !res->flags || res->start > res->end) | |
3020 | return; | |
3021 | ||
3022 | if (res->flags & IORESOURCE_IO) { | |
3023 | region.start = res->start - phb->ioda.io_pci_base; | |
3024 | region.end = res->end - phb->ioda.io_pci_base; | |
3025 | index = region.start / phb->ioda.io_segsize; | |
3026 | ||
3027 | while (index < phb->ioda.total_pe_num && | |
3028 | region.start <= region.end) { | |
3029 | phb->ioda.io_segmap[index] = pe->pe_number; | |
3030 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
3031 | pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); | |
3032 | if (rc != OPAL_SUCCESS) { | |
3033 | pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n", | |
3034 | __func__, rc, index, pe->pe_number); | |
3035 | break; | |
3036 | } | |
3037 | ||
3038 | region.start += phb->ioda.io_segsize; | |
3039 | index++; | |
3040 | } | |
3041 | } else if ((res->flags & IORESOURCE_MEM) && | |
3042 | !pnv_pci_is_mem_pref_64(res->flags)) { | |
3043 | region.start = res->start - | |
3044 | phb->hose->mem_offset[0] - | |
3045 | phb->ioda.m32_pci_base; | |
3046 | region.end = res->end - | |
3047 | phb->hose->mem_offset[0] - | |
3048 | phb->ioda.m32_pci_base; | |
3049 | index = region.start / phb->ioda.m32_segsize; | |
3050 | ||
3051 | while (index < phb->ioda.total_pe_num && | |
3052 | region.start <= region.end) { | |
3053 | phb->ioda.m32_segmap[index] = pe->pe_number; | |
3054 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, | |
3055 | pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); | |
3056 | if (rc != OPAL_SUCCESS) { | |
3057 | pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d", | |
3058 | __func__, rc, index, pe->pe_number); | |
3059 | break; | |
3060 | } | |
3061 | ||
3062 | region.start += phb->ioda.m32_segsize; | |
3063 | index++; | |
3064 | } | |
3065 | } | |
3066 | } | |
3067 | ||
11685bec GS |
3068 | /* |
3069 | * This function is supposed to be called on basis of PE from top | |
3070 | * to bottom style. So the the I/O or MMIO segment assigned to | |
3071 | * parent PE could be overrided by its child PEs if necessary. | |
3072 | */ | |
23e79425 | 3073 | static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) |
11685bec | 3074 | { |
69d733e7 | 3075 | struct pci_dev *pdev; |
23e79425 | 3076 | int i; |
11685bec GS |
3077 | |
3078 | /* | |
3079 | * NOTE: We only care PCI bus based PE for now. For PCI | |
3080 | * device based PE, for example SRIOV sensitive VF should | |
3081 | * be figured out later. | |
3082 | */ | |
3083 | BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); | |
3084 | ||
69d733e7 GS |
3085 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { |
3086 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
3087 | pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); | |
3088 | ||
3089 | /* | |
3090 | * If the PE contains all subordinate PCI buses, the | |
3091 | * windows of the child bridges should be mapped to | |
3092 | * the PE as well. | |
3093 | */ | |
3094 | if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) | |
3095 | continue; | |
3096 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
3097 | pnv_ioda_setup_pe_res(pe, | |
3098 | &pdev->resource[PCI_BRIDGE_RESOURCES + i]); | |
3099 | } | |
11685bec GS |
3100 | } |
3101 | ||
cad5cef6 | 3102 | static void pnv_pci_ioda_setup_seg(void) |
11685bec GS |
3103 | { |
3104 | struct pci_controller *tmp, *hose; | |
3105 | struct pnv_phb *phb; | |
3106 | struct pnv_ioda_pe *pe; | |
3107 | ||
3108 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
3109 | phb = hose->private_data; | |
5d2aa710 AP |
3110 | |
3111 | /* NPU PHB does not support IO or MMIO segmentation */ | |
3112 | if (phb->type == PNV_PHB_NPU) | |
3113 | continue; | |
3114 | ||
11685bec | 3115 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { |
23e79425 | 3116 | pnv_ioda_setup_pe_seg(pe); |
11685bec GS |
3117 | } |
3118 | } | |
3119 | } | |
3120 | ||
cad5cef6 | 3121 | static void pnv_pci_ioda_setup_DMA(void) |
13395c48 GS |
3122 | { |
3123 | struct pci_controller *hose, *tmp; | |
db1266c8 | 3124 | struct pnv_phb *phb; |
13395c48 GS |
3125 | |
3126 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
3127 | pnv_ioda_setup_dma(hose->private_data); | |
db1266c8 GS |
3128 | |
3129 | /* Mark the PHB initialization done */ | |
3130 | phb = hose->private_data; | |
3131 | phb->initialized = 1; | |
13395c48 GS |
3132 | } |
3133 | } | |
3134 | ||
37c367f2 GS |
3135 | static void pnv_pci_ioda_create_dbgfs(void) |
3136 | { | |
3137 | #ifdef CONFIG_DEBUG_FS | |
3138 | struct pci_controller *hose, *tmp; | |
3139 | struct pnv_phb *phb; | |
3140 | char name[16]; | |
3141 | ||
3142 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
3143 | phb = hose->private_data; | |
3144 | ||
3145 | sprintf(name, "PCI%04x", hose->global_number); | |
3146 | phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); | |
3147 | if (!phb->dbgfs) | |
3148 | pr_warning("%s: Error on creating debugfs on PHB#%x\n", | |
3149 | __func__, hose->global_number); | |
3150 | } | |
3151 | #endif /* CONFIG_DEBUG_FS */ | |
3152 | } | |
3153 | ||
5d2aa710 AP |
3154 | static void pnv_npu_ioda_fixup(void) |
3155 | { | |
3156 | bool enable_bypass; | |
3157 | struct pci_controller *hose, *tmp; | |
3158 | struct pnv_phb *phb; | |
3159 | struct pnv_ioda_pe *pe; | |
801846d1 | 3160 | unsigned int weight; |
5d2aa710 AP |
3161 | |
3162 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
3163 | phb = hose->private_data; | |
3164 | if (phb->type != PNV_PHB_NPU) | |
3165 | continue; | |
3166 | ||
801846d1 GS |
3167 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { |
3168 | weight = pnv_pci_ioda_pe_dma_weight(pe); | |
3169 | if (WARN_ON(!weight)) | |
3170 | continue; | |
3171 | ||
5d2aa710 AP |
3172 | enable_bypass = dma_get_mask(&pe->pdev->dev) == |
3173 | DMA_BIT_MASK(64); | |
3174 | pnv_npu_init_dma_pe(pe); | |
3175 | pnv_npu_dma_set_bypass(pe, enable_bypass); | |
3176 | } | |
3177 | } | |
3178 | } | |
3179 | ||
cad5cef6 | 3180 | static void pnv_pci_ioda_fixup(void) |
fb446ad0 GS |
3181 | { |
3182 | pnv_pci_ioda_setup_PEs(); | |
11685bec | 3183 | pnv_pci_ioda_setup_seg(); |
13395c48 | 3184 | pnv_pci_ioda_setup_DMA(); |
e9cc17d4 | 3185 | |
37c367f2 GS |
3186 | pnv_pci_ioda_create_dbgfs(); |
3187 | ||
e9cc17d4 | 3188 | #ifdef CONFIG_EEH |
e9cc17d4 | 3189 | eeh_init(); |
dadcd6d6 | 3190 | eeh_addr_cache_build(); |
e9cc17d4 | 3191 | #endif |
5d2aa710 AP |
3192 | |
3193 | /* Link NPU IODA tables to their PCI devices. */ | |
3194 | pnv_npu_ioda_fixup(); | |
fb446ad0 GS |
3195 | } |
3196 | ||
271fd03a GS |
3197 | /* |
3198 | * Returns the alignment for I/O or memory windows for P2P | |
3199 | * bridges. That actually depends on how PEs are segmented. | |
3200 | * For now, we return I/O or M32 segment size for PE sensitive | |
3201 | * P2P bridges. Otherwise, the default values (4KiB for I/O, | |
3202 | * 1MiB for memory) will be returned. | |
3203 | * | |
3204 | * The current PCI bus might be put into one PE, which was | |
3205 | * create against the parent PCI bridge. For that case, we | |
3206 | * needn't enlarge the alignment so that we can save some | |
3207 | * resources. | |
3208 | */ | |
3209 | static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, | |
3210 | unsigned long type) | |
3211 | { | |
3212 | struct pci_dev *bridge; | |
3213 | struct pci_controller *hose = pci_bus_to_host(bus); | |
3214 | struct pnv_phb *phb = hose->private_data; | |
3215 | int num_pci_bridges = 0; | |
3216 | ||
3217 | bridge = bus->self; | |
3218 | while (bridge) { | |
3219 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { | |
3220 | num_pci_bridges++; | |
3221 | if (num_pci_bridges >= 2) | |
3222 | return 1; | |
3223 | } | |
3224 | ||
3225 | bridge = bridge->bus->self; | |
3226 | } | |
3227 | ||
262af557 GC |
3228 | /* We fail back to M32 if M64 isn't supported */ |
3229 | if (phb->ioda.m64_segsize && | |
3230 | pnv_pci_is_mem_pref_64(type)) | |
3231 | return phb->ioda.m64_segsize; | |
271fd03a GS |
3232 | if (type & IORESOURCE_MEM) |
3233 | return phb->ioda.m32_segsize; | |
3234 | ||
3235 | return phb->ioda.io_segsize; | |
3236 | } | |
3237 | ||
5350ab3f WY |
3238 | #ifdef CONFIG_PCI_IOV |
3239 | static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, | |
3240 | int resno) | |
3241 | { | |
ee8222fe WY |
3242 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
3243 | struct pnv_phb *phb = hose->private_data; | |
5350ab3f | 3244 | struct pci_dn *pdn = pci_get_pdn(pdev); |
7fbe7a93 | 3245 | resource_size_t align; |
5350ab3f | 3246 | |
7fbe7a93 WY |
3247 | /* |
3248 | * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the | |
3249 | * SR-IOV. While from hardware perspective, the range mapped by M64 | |
3250 | * BAR should be size aligned. | |
3251 | * | |
ee8222fe WY |
3252 | * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra |
3253 | * powernv-specific hardware restriction is gone. But if just use the | |
3254 | * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with | |
3255 | * in one segment of M64 #15, which introduces the PE conflict between | |
3256 | * PF and VF. Based on this, the minimum alignment of an IOV BAR is | |
3257 | * m64_segsize. | |
3258 | * | |
7fbe7a93 WY |
3259 | * This function returns the total IOV BAR size if M64 BAR is in |
3260 | * Shared PE mode or just VF BAR size if not. | |
ee8222fe WY |
3261 | * If the M64 BAR is in Single PE mode, return the VF BAR size or |
3262 | * M64 segment size if IOV BAR size is less. | |
7fbe7a93 | 3263 | */ |
5350ab3f | 3264 | align = pci_iov_resource_size(pdev, resno); |
7fbe7a93 WY |
3265 | if (!pdn->vfs_expanded) |
3266 | return align; | |
ee8222fe WY |
3267 | if (pdn->m64_single_mode) |
3268 | return max(align, (resource_size_t)phb->ioda.m64_segsize); | |
5350ab3f | 3269 | |
7fbe7a93 | 3270 | return pdn->vfs_expanded * align; |
5350ab3f WY |
3271 | } |
3272 | #endif /* CONFIG_PCI_IOV */ | |
3273 | ||
184cd4a3 BH |
3274 | /* Prevent enabling devices for which we couldn't properly |
3275 | * assign a PE | |
3276 | */ | |
c88c2a18 | 3277 | static bool pnv_pci_enable_device_hook(struct pci_dev *dev) |
184cd4a3 | 3278 | { |
db1266c8 GS |
3279 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
3280 | struct pnv_phb *phb = hose->private_data; | |
3281 | struct pci_dn *pdn; | |
184cd4a3 | 3282 | |
db1266c8 GS |
3283 | /* The function is probably called while the PEs have |
3284 | * not be created yet. For example, resource reassignment | |
3285 | * during PCI probe period. We just skip the check if | |
3286 | * PEs isn't ready. | |
3287 | */ | |
3288 | if (!phb->initialized) | |
c88c2a18 | 3289 | return true; |
db1266c8 | 3290 | |
b72c1f65 | 3291 | pdn = pci_get_pdn(dev); |
184cd4a3 | 3292 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
c88c2a18 | 3293 | return false; |
db1266c8 | 3294 | |
c88c2a18 | 3295 | return true; |
184cd4a3 BH |
3296 | } |
3297 | ||
7a8e6bbf | 3298 | static void pnv_pci_ioda_shutdown(struct pci_controller *hose) |
73ed148a | 3299 | { |
7a8e6bbf MN |
3300 | struct pnv_phb *phb = hose->private_data; |
3301 | ||
d1a85eee | 3302 | opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, |
73ed148a BH |
3303 | OPAL_ASSERT_RESET); |
3304 | } | |
3305 | ||
92ae0353 | 3306 | static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { |
cb4224c5 GS |
3307 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
3308 | .dma_bus_setup = pnv_pci_dma_bus_setup, | |
92ae0353 | 3309 | #ifdef CONFIG_PCI_MSI |
cb4224c5 GS |
3310 | .setup_msi_irqs = pnv_setup_msi_irqs, |
3311 | .teardown_msi_irqs = pnv_teardown_msi_irqs, | |
92ae0353 | 3312 | #endif |
cb4224c5 GS |
3313 | .enable_device_hook = pnv_pci_enable_device_hook, |
3314 | .window_alignment = pnv_pci_window_alignment, | |
3315 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, | |
3316 | .dma_set_mask = pnv_pci_ioda_dma_set_mask, | |
3317 | .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, | |
3318 | .shutdown = pnv_pci_ioda_shutdown, | |
92ae0353 DA |
3319 | }; |
3320 | ||
5d2aa710 | 3321 | static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { |
cb4224c5 | 3322 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
5d2aa710 | 3323 | #ifdef CONFIG_PCI_MSI |
cb4224c5 GS |
3324 | .setup_msi_irqs = pnv_setup_msi_irqs, |
3325 | .teardown_msi_irqs = pnv_teardown_msi_irqs, | |
5d2aa710 | 3326 | #endif |
cb4224c5 GS |
3327 | .enable_device_hook = pnv_pci_enable_device_hook, |
3328 | .window_alignment = pnv_pci_window_alignment, | |
3329 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, | |
3330 | .dma_set_mask = pnv_npu_dma_set_mask, | |
3331 | .shutdown = pnv_pci_ioda_shutdown, | |
5d2aa710 AP |
3332 | }; |
3333 | ||
e51df2c1 AB |
3334 | static void __init pnv_pci_init_ioda_phb(struct device_node *np, |
3335 | u64 hub_id, int ioda_type) | |
184cd4a3 BH |
3336 | { |
3337 | struct pci_controller *hose; | |
184cd4a3 | 3338 | struct pnv_phb *phb; |
2b923ed1 GS |
3339 | unsigned long size, m64map_off, m32map_off, pemap_off; |
3340 | unsigned long iomap_off = 0, dma32map_off = 0; | |
c681b93c | 3341 | const __be64 *prop64; |
3a1a4661 | 3342 | const __be32 *prop32; |
f1b7cc3e | 3343 | int len; |
3fa23ff8 | 3344 | unsigned int segno; |
184cd4a3 BH |
3345 | u64 phb_id; |
3346 | void *aux; | |
3347 | long rc; | |
3348 | ||
58d714ec | 3349 | pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name); |
184cd4a3 BH |
3350 | |
3351 | prop64 = of_get_property(np, "ibm,opal-phbid", NULL); | |
3352 | if (!prop64) { | |
3353 | pr_err(" Missing \"ibm,opal-phbid\" property !\n"); | |
3354 | return; | |
3355 | } | |
3356 | phb_id = be64_to_cpup(prop64); | |
3357 | pr_debug(" PHB-ID : 0x%016llx\n", phb_id); | |
3358 | ||
e39f223f | 3359 | phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); |
58d714ec GS |
3360 | |
3361 | /* Allocate PCI controller */ | |
58d714ec GS |
3362 | phb->hose = hose = pcibios_alloc_controller(np); |
3363 | if (!phb->hose) { | |
3364 | pr_err(" Can't allocate PCI controller for %s\n", | |
184cd4a3 | 3365 | np->full_name); |
e39f223f | 3366 | memblock_free(__pa(phb), sizeof(struct pnv_phb)); |
184cd4a3 BH |
3367 | return; |
3368 | } | |
3369 | ||
3370 | spin_lock_init(&phb->lock); | |
f1b7cc3e GS |
3371 | prop32 = of_get_property(np, "bus-range", &len); |
3372 | if (prop32 && len == 8) { | |
3a1a4661 BH |
3373 | hose->first_busno = be32_to_cpu(prop32[0]); |
3374 | hose->last_busno = be32_to_cpu(prop32[1]); | |
f1b7cc3e GS |
3375 | } else { |
3376 | pr_warn(" Broken <bus-range> on %s\n", np->full_name); | |
3377 | hose->first_busno = 0; | |
3378 | hose->last_busno = 0xff; | |
3379 | } | |
184cd4a3 | 3380 | hose->private_data = phb; |
e9cc17d4 | 3381 | phb->hub_id = hub_id; |
184cd4a3 | 3382 | phb->opal_id = phb_id; |
aa0c033f | 3383 | phb->type = ioda_type; |
781a868f | 3384 | mutex_init(&phb->ioda.pe_alloc_mutex); |
184cd4a3 | 3385 | |
cee72d5b BH |
3386 | /* Detect specific models for error handling */ |
3387 | if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) | |
3388 | phb->model = PNV_PHB_MODEL_P7IOC; | |
f3d40c25 | 3389 | else if (of_device_is_compatible(np, "ibm,power8-pciex")) |
aa0c033f | 3390 | phb->model = PNV_PHB_MODEL_PHB3; |
5d2aa710 AP |
3391 | else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) |
3392 | phb->model = PNV_PHB_MODEL_NPU; | |
cee72d5b BH |
3393 | else |
3394 | phb->model = PNV_PHB_MODEL_UNKNOWN; | |
3395 | ||
aa0c033f | 3396 | /* Parse 32-bit and IO ranges (if any) */ |
2f1ec02e | 3397 | pci_process_bridge_OF_ranges(hose, np, !hose->global_number); |
184cd4a3 | 3398 | |
aa0c033f | 3399 | /* Get registers */ |
184cd4a3 BH |
3400 | phb->regs = of_iomap(np, 0); |
3401 | if (phb->regs == NULL) | |
3402 | pr_err(" Failed to map registers !\n"); | |
3403 | ||
184cd4a3 | 3404 | /* Initialize more IODA stuff */ |
92b8f137 | 3405 | phb->ioda.total_pe_num = 1; |
aa0c033f | 3406 | prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); |
36954dc7 | 3407 | if (prop32) |
92b8f137 | 3408 | phb->ioda.total_pe_num = be32_to_cpup(prop32); |
36954dc7 GS |
3409 | prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); |
3410 | if (prop32) | |
92b8f137 | 3411 | phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); |
262af557 GC |
3412 | |
3413 | /* Parse 64-bit MMIO range */ | |
3414 | pnv_ioda_parse_m64_window(phb); | |
3415 | ||
184cd4a3 | 3416 | phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); |
aa0c033f | 3417 | /* FW Has already off top 64k of M32 space (MSI space) */ |
184cd4a3 BH |
3418 | phb->ioda.m32_size += 0x10000; |
3419 | ||
92b8f137 | 3420 | phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; |
3fd47f06 | 3421 | phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; |
184cd4a3 | 3422 | phb->ioda.io_size = hose->pci_io_size; |
92b8f137 | 3423 | phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; |
184cd4a3 BH |
3424 | phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ |
3425 | ||
2b923ed1 GS |
3426 | /* Calculate how many 32-bit TCE segments we have */ |
3427 | phb->ioda.dma32_count = phb->ioda.m32_pci_base / | |
3428 | PNV_IODA1_DMA32_SEGSIZE; | |
3429 | ||
c35d2a8c | 3430 | /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ |
92b8f137 | 3431 | size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); |
93289d8c GS |
3432 | m64map_off = size; |
3433 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); | |
184cd4a3 | 3434 | m32map_off = size; |
92b8f137 | 3435 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); |
c35d2a8c GS |
3436 | if (phb->type == PNV_PHB_IODA1) { |
3437 | iomap_off = size; | |
92b8f137 | 3438 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); |
2b923ed1 GS |
3439 | dma32map_off = size; |
3440 | size += phb->ioda.dma32_count * | |
3441 | sizeof(phb->ioda.dma32_segmap[0]); | |
c35d2a8c | 3442 | } |
184cd4a3 | 3443 | pemap_off = size; |
92b8f137 | 3444 | size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); |
e39f223f | 3445 | aux = memblock_virt_alloc(size, 0); |
184cd4a3 | 3446 | phb->ioda.pe_alloc = aux; |
93289d8c | 3447 | phb->ioda.m64_segmap = aux + m64map_off; |
184cd4a3 | 3448 | phb->ioda.m32_segmap = aux + m32map_off; |
93289d8c GS |
3449 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { |
3450 | phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; | |
3fa23ff8 | 3451 | phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; |
93289d8c | 3452 | } |
3fa23ff8 | 3453 | if (phb->type == PNV_PHB_IODA1) { |
c35d2a8c | 3454 | phb->ioda.io_segmap = aux + iomap_off; |
3fa23ff8 GS |
3455 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) |
3456 | phb->ioda.io_segmap[segno] = IODA_INVALID_PE; | |
2b923ed1 GS |
3457 | |
3458 | phb->ioda.dma32_segmap = aux + dma32map_off; | |
3459 | for (segno = 0; segno < phb->ioda.dma32_count; segno++) | |
3460 | phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; | |
3fa23ff8 | 3461 | } |
184cd4a3 | 3462 | phb->ioda.pe_array = aux + pemap_off; |
92b8f137 | 3463 | set_bit(phb->ioda.reserved_pe_idx, phb->ioda.pe_alloc); |
184cd4a3 BH |
3464 | |
3465 | INIT_LIST_HEAD(&phb->ioda.pe_list); | |
781a868f | 3466 | mutex_init(&phb->ioda.pe_list_mutex); |
184cd4a3 BH |
3467 | |
3468 | /* Calculate how many 32-bit TCE segments we have */ | |
2b923ed1 | 3469 | phb->ioda.dma32_count = phb->ioda.m32_pci_base / |
acce971c | 3470 | PNV_IODA1_DMA32_SEGSIZE; |
184cd4a3 | 3471 | |
aa0c033f | 3472 | #if 0 /* We should really do that ... */ |
184cd4a3 BH |
3473 | rc = opal_pci_set_phb_mem_window(opal->phb_id, |
3474 | window_type, | |
3475 | window_num, | |
3476 | starting_real_address, | |
3477 | starting_pci_address, | |
3478 | segment_size); | |
3479 | #endif | |
3480 | ||
262af557 | 3481 | pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", |
92b8f137 | 3482 | phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, |
262af557 GC |
3483 | phb->ioda.m32_size, phb->ioda.m32_segsize); |
3484 | if (phb->ioda.m64_size) | |
3485 | pr_info(" M64: 0x%lx [segment=0x%lx]\n", | |
3486 | phb->ioda.m64_size, phb->ioda.m64_segsize); | |
3487 | if (phb->ioda.io_size) | |
3488 | pr_info(" IO: 0x%x [segment=0x%x]\n", | |
3489 | phb->ioda.io_size, phb->ioda.io_segsize); | |
3490 | ||
184cd4a3 | 3491 | |
184cd4a3 | 3492 | phb->hose->ops = &pnv_pci_ops; |
49dec922 GS |
3493 | phb->get_pe_state = pnv_ioda_get_pe_state; |
3494 | phb->freeze_pe = pnv_ioda_freeze_pe; | |
3495 | phb->unfreeze_pe = pnv_ioda_unfreeze_pe; | |
184cd4a3 | 3496 | |
184cd4a3 BH |
3497 | /* Setup TCEs */ |
3498 | phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; | |
3499 | ||
3500 | /* Setup MSI support */ | |
3501 | pnv_pci_init_ioda_msis(phb); | |
3502 | ||
c40a4210 GS |
3503 | /* |
3504 | * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here | |
3505 | * to let the PCI core do resource assignment. It's supposed | |
3506 | * that the PCI core will do correct I/O and MMIO alignment | |
3507 | * for the P2P bridge bars so that each PCI bus (excluding | |
3508 | * the child P2P bridges) can form individual PE. | |
184cd4a3 | 3509 | */ |
fb446ad0 | 3510 | ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; |
5d2aa710 AP |
3511 | |
3512 | if (phb->type == PNV_PHB_NPU) | |
3513 | hose->controller_ops = pnv_npu_ioda_controller_ops; | |
3514 | else | |
3515 | hose->controller_ops = pnv_pci_ioda_controller_ops; | |
ad30cb99 | 3516 | |
6e628c7d WY |
3517 | #ifdef CONFIG_PCI_IOV |
3518 | ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; | |
5350ab3f | 3519 | ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; |
ad30cb99 ME |
3520 | #endif |
3521 | ||
c40a4210 | 3522 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
184cd4a3 BH |
3523 | |
3524 | /* Reset IODA tables to a clean state */ | |
d1a85eee | 3525 | rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); |
184cd4a3 | 3526 | if (rc) |
f11fe552 | 3527 | pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); |
361f2a2a GS |
3528 | |
3529 | /* If we're running in kdump kerenl, the previous kerenl never | |
3530 | * shutdown PCI devices correctly. We already got IODA table | |
3531 | * cleaned out. So we have to issue PHB reset to stop all PCI | |
3532 | * transactions from previous kerenl. | |
3533 | */ | |
3534 | if (is_kdump_kernel()) { | |
3535 | pr_info(" Issue PHB reset ...\n"); | |
cadf364d GS |
3536 | pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); |
3537 | pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); | |
361f2a2a | 3538 | } |
262af557 | 3539 | |
9e9e8935 GS |
3540 | /* Remove M64 resource if we can't configure it successfully */ |
3541 | if (!phb->init_m64 || phb->init_m64(phb)) | |
262af557 | 3542 | hose->mem_resources[1].flags = 0; |
aa0c033f GS |
3543 | } |
3544 | ||
67975005 | 3545 | void __init pnv_pci_init_ioda2_phb(struct device_node *np) |
aa0c033f | 3546 | { |
e9cc17d4 | 3547 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); |
184cd4a3 BH |
3548 | } |
3549 | ||
5d2aa710 AP |
3550 | void __init pnv_pci_init_npu_phb(struct device_node *np) |
3551 | { | |
3552 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); | |
3553 | } | |
3554 | ||
184cd4a3 BH |
3555 | void __init pnv_pci_init_ioda_hub(struct device_node *np) |
3556 | { | |
3557 | struct device_node *phbn; | |
c681b93c | 3558 | const __be64 *prop64; |
184cd4a3 BH |
3559 | u64 hub_id; |
3560 | ||
3561 | pr_info("Probing IODA IO-Hub %s\n", np->full_name); | |
3562 | ||
3563 | prop64 = of_get_property(np, "ibm,opal-hubid", NULL); | |
3564 | if (!prop64) { | |
3565 | pr_err(" Missing \"ibm,opal-hubid\" property !\n"); | |
3566 | return; | |
3567 | } | |
3568 | hub_id = be64_to_cpup(prop64); | |
3569 | pr_devel(" HUB-ID : 0x%016llx\n", hub_id); | |
3570 | ||
3571 | /* Count child PHBs */ | |
3572 | for_each_child_of_node(np, phbn) { | |
3573 | /* Look for IODA1 PHBs */ | |
3574 | if (of_device_is_compatible(phbn, "ibm,ioda-phb")) | |
e9cc17d4 | 3575 | pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); |
184cd4a3 BH |
3576 | } |
3577 | } |