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Merge remote-tracking branches 'regulator/topic/s2mps11', 'regulator/topic/s5m8767...
[linux-2.6-block.git] / arch / powerpc / platforms / powernv / eeh-ioda.c
CommitLineData
8747f363
GS		 1/*
2 * The file intends to implement the functions needed by EEH, which is
3 * built on IODA compliant chip. Actually, lots of functions related
4 * to EEH would be built based on the OPAL APIs.
5 *
6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/bootmem.h>
8998897b 15#include <linux/debugfs.h>
8747f363
GS		 16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/kernel.h>
21#include <linux/msi.h>
7cb9d93d 22#include <linux/notifier.h>
8747f363
GS		 23#include <linux/pci.h>
24#include <linux/string.h>
25
26#include <asm/eeh.h>
27#include <asm/eeh_event.h>
28#include <asm/io.h>
29#include <asm/iommu.h>
30#include <asm/msi_bitmap.h>
31#include <asm/opal.h>
32#include <asm/pci-bridge.h>
33#include <asm/ppc-pci.h>
34#include <asm/tce.h>
35
36#include "powernv.h"
37#include "pci.h"
38
7cb9d93d
GS		 39static int ioda_eeh_nb_init = 0;
40
41static int ioda_eeh_event(struct notifier_block *nb,
42 unsigned long events, void *change)
43{
44 uint64_t changed_evts = (uint64_t)change;
45
46 /* We simply send special EEH event */
47 if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
48 (events & OPAL_EVENT_PCI_ERROR))
49 eeh_send_failure_event(NULL);
50
51 return 0;
52}
53
54static struct notifier_block ioda_eeh_nb = {
55 .notifier_call = ioda_eeh_event,
56 .next = NULL,
57 .priority = 0
58};
70f942db 59
8998897b 60#ifdef CONFIG_DEBUG_FS
ff6bdcd9 61static int ioda_eeh_dbgfs_set(void *data, int offset, u64 val)
8998897b
GS		 62{
63 struct pci_controller *hose = data;
64 struct pnv_phb *phb = hose->private_data;
65
ff6bdcd9 66 out_be64(phb->regs + offset, val);
8998897b
GS		 67 return 0;
68}
69
ff6bdcd9 70static int ioda_eeh_dbgfs_get(void *data, int offset, u64 *val)
8998897b
GS		 71{
72 struct pci_controller *hose = data;
73 struct pnv_phb *phb = hose->private_data;
74
ff6bdcd9 75 *val = in_be64(phb->regs + offset);
8998897b
GS		 76 return 0;
77}
78
ff6bdcd9
GS		 79static int ioda_eeh_outb_dbgfs_set(void *data, u64 val)
80{
81 return ioda_eeh_dbgfs_set(data, 0xD10, val);
82}
83
84static int ioda_eeh_outb_dbgfs_get(void *data, u64 *val)
85{
86 return ioda_eeh_dbgfs_get(data, 0xD10, val);
87}
88
89static int ioda_eeh_inbA_dbgfs_set(void *data, u64 val)
90{
91 return ioda_eeh_dbgfs_set(data, 0xD90, val);
92}
93
94static int ioda_eeh_inbA_dbgfs_get(void *data, u64 *val)
95{
96 return ioda_eeh_dbgfs_get(data, 0xD90, val);
97}
98
99static int ioda_eeh_inbB_dbgfs_set(void *data, u64 val)
100{
101 return ioda_eeh_dbgfs_set(data, 0xE10, val);
102}
103
104static int ioda_eeh_inbB_dbgfs_get(void *data, u64 *val)
105{
106 return ioda_eeh_dbgfs_get(data, 0xE10, val);
107}
108
109DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_outb_dbgfs_ops, ioda_eeh_outb_dbgfs_get,
110 ioda_eeh_outb_dbgfs_set, "0x%llx\n");
111DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbA_dbgfs_ops, ioda_eeh_inbA_dbgfs_get,
112 ioda_eeh_inbA_dbgfs_set, "0x%llx\n");
113DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_inbB_dbgfs_ops, ioda_eeh_inbB_dbgfs_get,
114 ioda_eeh_inbB_dbgfs_set, "0x%llx\n");
8998897b
GS		 115#endif /* CONFIG_DEBUG_FS */
116
73370c66
GS		 117/**
118 * ioda_eeh_post_init - Chip dependent post initialization
119 * @hose: PCI controller
120 *
121 * The function will be called after eeh PEs and devices
122 * have been built. That means the EEH is ready to supply
123 * service with I/O cache.
124 */
125static int ioda_eeh_post_init(struct pci_controller *hose)
126{
127 struct pnv_phb *phb = hose->private_data;
7cb9d93d
GS		 128 int ret;
129
130 /* Register OPAL event notifier */
131 if (!ioda_eeh_nb_init) {
132 ret = opal_notifier_register(&ioda_eeh_nb);
133 if (ret) {
134 pr_err("%s: Can't register OPAL event notifier (%d)\n",
135 __func__, ret);
136 return ret;
137 }
138
139 ioda_eeh_nb_init = 1;
140 }
73370c66 141
8998897b 142#ifdef CONFIG_DEBUG_FS
ff6bdcd9
GS		 143 if (phb->dbgfs) {
144 debugfs_create_file("err_injct_outbound", 0600,
145 phb->dbgfs, hose,
146 &ioda_eeh_outb_dbgfs_ops);
147 debugfs_create_file("err_injct_inboundA", 0600,
20bb842b 148 phb->dbgfs, hose,
ff6bdcd9
GS		 149 &ioda_eeh_inbA_dbgfs_ops);
150 debugfs_create_file("err_injct_inboundB", 0600,
151 phb->dbgfs, hose,
152 &ioda_eeh_inbB_dbgfs_ops);
153 }
8998897b
GS		 154#endif
155
20bb842b 156 phb->eeh_state |= PNV_EEH_STATE_ENABLED;
73370c66
GS		 157
158 return 0;
159}
160
eb005983
GS		 161/**
162 * ioda_eeh_set_option - Set EEH operation or I/O setting
163 * @pe: EEH PE
164 * @option: options
165 *
166 * Enable or disable EEH option for the indicated PE. The
167 * function also can be used to enable I/O or DMA for the
168 * PE.
169 */
170static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
171{
172 s64 ret;
173 u32 pe_no;
174 struct pci_controller *hose = pe->phb;
175 struct pnv_phb *phb = hose->private_data;
176
177 /* Check on PE number */
178 if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
179 pr_err("%s: PE address %x out of range [0, %x] "
180 "on PHB#%x\n",
181 __func__, pe->addr, phb->ioda.total_pe,
182 hose->global_number);
183 return -EINVAL;
184 }
185
186 pe_no = pe->addr;
187 switch (option) {
188 case EEH_OPT_DISABLE:
189 ret = -EEXIST;
190 break;
191 case EEH_OPT_ENABLE:
192 ret = 0;
193 break;
194 case EEH_OPT_THAW_MMIO:
195 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
196 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
197 if (ret) {
198 pr_warning("%s: Failed to enable MMIO for "
199 "PHB#%x-PE#%x, err=%lld\n",
200 __func__, hose->global_number, pe_no, ret);
201 return -EIO;
202 }
203
204 break;
205 case EEH_OPT_THAW_DMA:
206 ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
207 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
208 if (ret) {
209 pr_warning("%s: Failed to enable DMA for "
210 "PHB#%x-PE#%x, err=%lld\n",
211 __func__, hose->global_number, pe_no, ret);
212 return -EIO;
213 }
214
215 break;
216 default:
217 pr_warning("%s: Invalid option %d\n", __func__, option);
218 return -EINVAL;
219 }
220
221 return ret;
222}
223
8c41a7f3
GS		 224/**
225 * ioda_eeh_get_state - Retrieve the state of PE
226 * @pe: EEH PE
227 *
228 * The PE's state should be retrieved from the PEEV, PEST
229 * IODA tables. Since the OPAL has exported the function
230 * to do it, it'd better to use that.
231 */
232static int ioda_eeh_get_state(struct eeh_pe *pe)
233{
234 s64 ret = 0;
235 u8 fstate;
236 u16 pcierr;
237 u32 pe_no;
238 int result;
239 struct pci_controller *hose = pe->phb;
240 struct pnv_phb *phb = hose->private_data;
241
242 /*
243 * Sanity check on PE address. The PHB PE address should
244 * be zero.
245 */
246 if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
247 pr_err("%s: PE address %x out of range [0, %x] "
248 "on PHB#%x\n",
249 __func__, pe->addr, phb->ioda.total_pe,
250 hose->global_number);
251 return EEH_STATE_NOT_SUPPORT;
252 }
253
254 /* Retrieve PE status through OPAL */
255 pe_no = pe->addr;
256 ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
257 &fstate, &pcierr, NULL);
258 if (ret) {
259 pr_err("%s: Failed to get EEH status on "
260 "PHB#%x-PE#%x\n, err=%lld\n",
261 __func__, hose->global_number, pe_no, ret);
262 return EEH_STATE_NOT_SUPPORT;
263 }
264
265 /* Check PHB status */
266 if (pe->type & EEH_PE_PHB) {
267 result = 0;
268 result &= ~EEH_STATE_RESET_ACTIVE;
269
270 if (pcierr != OPAL_EEH_PHB_ERROR) {
271 result |= EEH_STATE_MMIO_ACTIVE;
272 result |= EEH_STATE_DMA_ACTIVE;
273 result |= EEH_STATE_MMIO_ENABLED;
274 result |= EEH_STATE_DMA_ENABLED;
275 }
276
277 return result;
278 }
279
280 /* Parse result out */
281 result = 0;
282 switch (fstate) {
283 case OPAL_EEH_STOPPED_NOT_FROZEN:
284 result &= ~EEH_STATE_RESET_ACTIVE;
285 result |= EEH_STATE_MMIO_ACTIVE;
286 result |= EEH_STATE_DMA_ACTIVE;
287 result |= EEH_STATE_MMIO_ENABLED;
288 result |= EEH_STATE_DMA_ENABLED;
289 break;
290 case OPAL_EEH_STOPPED_MMIO_FREEZE:
291 result &= ~EEH_STATE_RESET_ACTIVE;
292 result |= EEH_STATE_DMA_ACTIVE;
293 result |= EEH_STATE_DMA_ENABLED;
294 break;
295 case OPAL_EEH_STOPPED_DMA_FREEZE:
296 result &= ~EEH_STATE_RESET_ACTIVE;
297 result |= EEH_STATE_MMIO_ACTIVE;
298 result |= EEH_STATE_MMIO_ENABLED;
299 break;
300 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
301 result &= ~EEH_STATE_RESET_ACTIVE;
302 break;
303 case OPAL_EEH_STOPPED_RESET:
304 result |= EEH_STATE_RESET_ACTIVE;
305 break;
306 case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
307 result |= EEH_STATE_UNAVAILABLE;
308 break;
309 case OPAL_EEH_STOPPED_PERM_UNAVAIL:
310 result |= EEH_STATE_NOT_SUPPORT;
311 break;
312 default:
313 pr_warning("%s: Unexpected EEH status 0x%x "
314 "on PHB#%x-PE#%x\n",
315 __func__, fstate, hose->global_number, pe_no);
316 }
317
318 return result;
319}
320
9d5cab00
GS		 321static int ioda_eeh_pe_clear(struct eeh_pe *pe)
322{
323 struct pci_controller *hose;
324 struct pnv_phb *phb;
325 u32 pe_no;
326 u8 fstate;
327 u16 pcierr;
328 s64 ret;
329
330 pe_no = pe->addr;
331 hose = pe->phb;
332 phb = pe->phb->private_data;
333
334 /* Clear the EEH error on the PE */
335 ret = opal_pci_eeh_freeze_clear(phb->opal_id,
336 pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
337 if (ret) {
338 pr_err("%s: Failed to clear EEH error for "
339 "PHB#%x-PE#%x, err=%lld\n",
340 __func__, hose->global_number, pe_no, ret);
341 return -EIO;
342 }
343
344 /*
345 * Read the PE state back and verify that the frozen
346 * state has been removed.
347 */
348 ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
349 &fstate, &pcierr, NULL);
350 if (ret) {
351 pr_err("%s: Failed to get EEH status on "
352 "PHB#%x-PE#%x\n, err=%lld\n",
353 __func__, hose->global_number, pe_no, ret);
354 return -EIO;
355 }
356
357 if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) {
358 pr_err("%s: Frozen state not cleared on "
359 "PHB#%x-PE#%x, sts=%x\n",
360 __func__, hose->global_number, pe_no, fstate);
361 return -EIO;
362 }
363
364 return 0;
365}
366
367static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
368{
369 s64 rc = OPAL_HARDWARE;
370
371 while (1) {
372 rc = opal_pci_poll(phb->opal_id);
373 if (rc <= 0)
374 break;
375
376 msleep(rc);
377 }
378
379 return rc;
380}
381
382static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
383{
384 struct pnv_phb *phb = hose->private_data;
385 s64 rc = OPAL_HARDWARE;
386
387 pr_debug("%s: Reset PHB#%x, option=%d\n",
388 __func__, hose->global_number, option);
389
390 /* Issue PHB complete reset request */
391 if (option == EEH_RESET_FUNDAMENTAL ||
392 option == EEH_RESET_HOT)
393 rc = opal_pci_reset(phb->opal_id,
394 OPAL_PHB_COMPLETE,
395 OPAL_ASSERT_RESET);
396 else if (option == EEH_RESET_DEACTIVATE)
397 rc = opal_pci_reset(phb->opal_id,
398 OPAL_PHB_COMPLETE,
399 OPAL_DEASSERT_RESET);
400 if (rc < 0)
401 goto out;
402
403 /*
404 * Poll state of the PHB until the request is done
405 * successfully.
406 */
407 rc = ioda_eeh_phb_poll(phb);
408out:
409 if (rc != OPAL_SUCCESS)
410 return -EIO;
411
412 return 0;
413}
414
415static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
416{
417 struct pnv_phb *phb = hose->private_data;
418 s64 rc = OPAL_SUCCESS;
419
420 pr_debug("%s: Reset PHB#%x, option=%d\n",
421 __func__, hose->global_number, option);
422
423 /*
424 * During the reset deassert time, we needn't care
425 * the reset scope because the firmware does nothing
426 * for fundamental or hot reset during deassert phase.
427 */
428 if (option == EEH_RESET_FUNDAMENTAL)
429 rc = opal_pci_reset(phb->opal_id,
430 OPAL_PCI_FUNDAMENTAL_RESET,
431 OPAL_ASSERT_RESET);
432 else if (option == EEH_RESET_HOT)
433 rc = opal_pci_reset(phb->opal_id,
434 OPAL_PCI_HOT_RESET,
435 OPAL_ASSERT_RESET);
436 else if (option == EEH_RESET_DEACTIVATE)
437 rc = opal_pci_reset(phb->opal_id,
438 OPAL_PCI_HOT_RESET,
439 OPAL_DEASSERT_RESET);
440 if (rc < 0)
441 goto out;
442
443 /* Poll state of the PHB until the request is done */
444 rc = ioda_eeh_phb_poll(phb);
445out:
446 if (rc != OPAL_SUCCESS)
447 return -EIO;
448
449 return 0;
450}
451
452static int ioda_eeh_bridge_reset(struct pci_controller *hose,
453 struct pci_dev *dev, int option)
454{
455 u16 ctrl;
456
457 pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n",
458 __func__, hose->global_number, dev->bus->number,
459 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option);
460
461 switch (option) {
462 case EEH_RESET_FUNDAMENTAL:
463 case EEH_RESET_HOT:
464 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
465 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
466 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
467 break;
468 case EEH_RESET_DEACTIVATE:
469 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
470 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
471 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
472 break;
473 }
474
475 return 0;
476}
477
478/**
479 * ioda_eeh_reset - Reset the indicated PE
480 * @pe: EEH PE
481 * @option: reset option
482 *
483 * Do reset on the indicated PE. For PCI bus sensitive PE,
484 * we need to reset the parent p2p bridge. The PHB has to
485 * be reinitialized if the p2p bridge is root bridge. For
486 * PCI device sensitive PE, we will try to reset the device
487 * through FLR. For now, we don't have OPAL APIs to do HARD
488 * reset yet, so all reset would be SOFT (HOT) reset.
489 */
490static int ioda_eeh_reset(struct eeh_pe *pe, int option)
491{
492 struct pci_controller *hose = pe->phb;
493 struct eeh_dev *edev;
494 struct pci_dev *dev;
495 int ret;
496
497 /*
498 * Anyway, we have to clear the problematic state for the
499 * corresponding PE. However, we needn't do it if the PE
500 * is PHB associated. That means the PHB is having fatal
501 * errors and it needs reset. Further more, the AIB interface
502 * isn't reliable any more.
503 */
504 if (!(pe->type & EEH_PE_PHB) &&
505 (option == EEH_RESET_HOT ||
506 option == EEH_RESET_FUNDAMENTAL)) {
507 ret = ioda_eeh_pe_clear(pe);
508 if (ret)
509 return -EIO;
510 }
511
512 /*
513 * The rules applied to reset, either fundamental or hot reset:
514 *
515 * We always reset the direct upstream bridge of the PE. If the
516 * direct upstream bridge isn't root bridge, we always take hot
517 * reset no matter what option (fundamental or hot) is. Otherwise,
518 * we should do the reset according to the required option.
519 */
520 if (pe->type & EEH_PE_PHB) {
521 ret = ioda_eeh_phb_reset(hose, option);
522 } else {
523 if (pe->type & EEH_PE_DEVICE) {
524 /*
525 * If it's device PE, we didn't refer to the parent
526 * PCI bus yet. So we have to figure it out indirectly.
527 */
528 edev = list_first_entry(&pe->edevs,
529 struct eeh_dev, list);
530 dev = eeh_dev_to_pci_dev(edev);
531 dev = dev->bus->self;
532 } else {
533 /*
534 * If it's bus PE, the parent PCI bus is already there
535 * and just pick it up.
536 */
537 dev = pe->bus->self;
538 }
539
540 /*
541 * Do reset based on the fact that the direct upstream bridge
542 * is root bridge (port) or not.
543 */
544 if (dev->bus->number == 0)
545 ret = ioda_eeh_root_reset(hose, option);
546 else
547 ret = ioda_eeh_bridge_reset(hose, dev, option);
548 }
549
550 return ret;
551}
552
bf90dfea
GS		 553/**
554 * ioda_eeh_get_log - Retrieve error log
555 * @pe: EEH PE
556 * @severity: Severity level of the log
557 * @drv_log: buffer to store the log
558 * @len: space of the log buffer
559 *
560 * The function is used to retrieve error log from P7IOC.
561 */
562static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
563 char *drv_log, unsigned long len)
564{
565 s64 ret;
566 unsigned long flags;
567 struct pci_controller *hose = pe->phb;
568 struct pnv_phb *phb = hose->private_data;
569
570 spin_lock_irqsave(&phb->lock, flags);
571
572 ret = opal_pci_get_phb_diag_data2(phb->opal_id,
573 phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
574 if (ret) {
575 spin_unlock_irqrestore(&phb->lock, flags);
98cea5fe
GS		 576 pr_warning("%s: Can't get log for PHB#%x-PE#%x (%lld)\n",
577 __func__, hose->global_number, pe->addr, ret);
bf90dfea
GS		 578 return -EIO;
579 }
580
581 /*
582 * FIXME: We probably need log the error in somewhere.
583 * Lets make it up in future.
584 */
585 /* pr_info("%s", phb->diag.blob); */
586
587 spin_unlock_irqrestore(&phb->lock, flags);
588
589 return 0;
590}
591
592/**
593 * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
594 * @pe: EEH PE
595 *
596 * For particular PE, it might have included PCI bridges. In order
597 * to make the PE work properly, those PCI bridges should be configured
598 * correctly. However, we need do nothing on P7IOC since the reset
599 * function will do everything that should be covered by the function.
600 */
601static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
602{
603 return 0;
604}
605
70f942db
GS		 606static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
607{
608 /* GEM */
609 pr_info(" GEM XFIR: %016llx\n", data->gemXfir);
610 pr_info(" GEM RFIR: %016llx\n", data->gemRfir);
611 pr_info(" GEM RIRQFIR: %016llx\n", data->gemRirqfir);
612 pr_info(" GEM Mask: %016llx\n", data->gemMask);
613 pr_info(" GEM RWOF: %016llx\n", data->gemRwof);
614
615 /* LEM */
616 pr_info(" LEM FIR: %016llx\n", data->lemFir);
617 pr_info(" LEM Error Mask: %016llx\n", data->lemErrMask);
618 pr_info(" LEM Action 0: %016llx\n", data->lemAction0);
619 pr_info(" LEM Action 1: %016llx\n", data->lemAction1);
620 pr_info(" LEM WOF: %016llx\n", data->lemWof);
621}
622
623static void ioda_eeh_hub_diag(struct pci_controller *hose)
624{
625 struct pnv_phb *phb = hose->private_data;
ca1de5de 626 struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
70f942db
GS		 627 long rc;
628
ca1de5de 629 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
70f942db
GS		 630 if (rc != OPAL_SUCCESS) {
631 pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n",
632 __func__, phb->hub_id, rc);
633 return;
634 }
635
636 switch (data->type) {
637 case OPAL_P7IOC_DIAG_TYPE_RGC:
638 pr_info("P7IOC diag-data for RGC\n\n");
639 ioda_eeh_hub_diag_common(data);
640 pr_info(" RGC Status: %016llx\n", data->rgc.rgcStatus);
641 pr_info(" RGC LDCP: %016llx\n", data->rgc.rgcLdcp);
642 break;
643 case OPAL_P7IOC_DIAG_TYPE_BI:
644 pr_info("P7IOC diag-data for BI %s\n\n",
645 data->bi.biDownbound ? "Downbound" : "Upbound");
646 ioda_eeh_hub_diag_common(data);
647 pr_info(" BI LDCP 0: %016llx\n", data->bi.biLdcp0);
648 pr_info(" BI LDCP 1: %016llx\n", data->bi.biLdcp1);
649 pr_info(" BI LDCP 2: %016llx\n", data->bi.biLdcp2);
650 pr_info(" BI Fence Status: %016llx\n", data->bi.biFenceStatus);
651 break;
652 case OPAL_P7IOC_DIAG_TYPE_CI:
653 pr_info("P7IOC diag-data for CI Port %d\\nn",
654 data->ci.ciPort);
655 ioda_eeh_hub_diag_common(data);
656 pr_info(" CI Port Status: %016llx\n", data->ci.ciPortStatus);
657 pr_info(" CI Port LDCP: %016llx\n", data->ci.ciPortLdcp);
658 break;
659 case OPAL_P7IOC_DIAG_TYPE_MISC:
660 pr_info("P7IOC diag-data for MISC\n\n");
661 ioda_eeh_hub_diag_common(data);
662 break;
663 case OPAL_P7IOC_DIAG_TYPE_I2C:
664 pr_info("P7IOC diag-data for I2C\n\n");
665 ioda_eeh_hub_diag_common(data);
666 break;
667 default:
668 pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n",
669 __func__, phb->hub_id, data->type);
670 }
671}
672
673static void ioda_eeh_p7ioc_phb_diag(struct pci_controller *hose,
674 struct OpalIoPhbErrorCommon *common)
675{
676 struct OpalIoP7IOCPhbErrorData *data;
677 int i;
678
679 data = (struct OpalIoP7IOCPhbErrorData *)common;
680
681 pr_info("P7IOC PHB#%x Diag-data (Version: %d)\n\n",
682 hose->global_number, common->version);
683
684 pr_info(" brdgCtl: %08x\n", data->brdgCtl);
685
686 pr_info(" portStatusReg: %08x\n", data->portStatusReg);
687 pr_info(" rootCmplxStatus: %08x\n", data->rootCmplxStatus);
688 pr_info(" busAgentStatus: %08x\n", data->busAgentStatus);
689
690 pr_info(" deviceStatus: %08x\n", data->deviceStatus);
691 pr_info(" slotStatus: %08x\n", data->slotStatus);
692 pr_info(" linkStatus: %08x\n", data->linkStatus);
693 pr_info(" devCmdStatus: %08x\n", data->devCmdStatus);
694 pr_info(" devSecStatus: %08x\n", data->devSecStatus);
695
696 pr_info(" rootErrorStatus: %08x\n", data->rootErrorStatus);
697 pr_info(" uncorrErrorStatus: %08x\n", data->uncorrErrorStatus);
698 pr_info(" corrErrorStatus: %08x\n", data->corrErrorStatus);
699 pr_info(" tlpHdr1: %08x\n", data->tlpHdr1);
700 pr_info(" tlpHdr2: %08x\n", data->tlpHdr2);
701 pr_info(" tlpHdr3: %08x\n", data->tlpHdr3);
702 pr_info(" tlpHdr4: %08x\n", data->tlpHdr4);
703 pr_info(" sourceId: %08x\n", data->sourceId);
704
705 pr_info(" errorClass: %016llx\n", data->errorClass);
706 pr_info(" correlator: %016llx\n", data->correlator);
707 pr_info(" p7iocPlssr: %016llx\n", data->p7iocPlssr);
708 pr_info(" p7iocCsr: %016llx\n", data->p7iocCsr);
709 pr_info(" lemFir: %016llx\n", data->lemFir);
710 pr_info(" lemErrorMask: %016llx\n", data->lemErrorMask);
711 pr_info(" lemWOF: %016llx\n", data->lemWOF);
712 pr_info(" phbErrorStatus: %016llx\n", data->phbErrorStatus);
713 pr_info(" phbFirstErrorStatus: %016llx\n", data->phbFirstErrorStatus);
714 pr_info(" phbErrorLog0: %016llx\n", data->phbErrorLog0);
715 pr_info(" phbErrorLog1: %016llx\n", data->phbErrorLog1);
716 pr_info(" mmioErrorStatus: %016llx\n", data->mmioErrorStatus);
717 pr_info(" mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
718 pr_info(" mmioErrorLog0: %016llx\n", data->mmioErrorLog0);
719 pr_info(" mmioErrorLog1: %016llx\n", data->mmioErrorLog1);
720 pr_info(" dma0ErrorStatus: %016llx\n", data->dma0ErrorStatus);
721 pr_info(" dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
722 pr_info(" dma0ErrorLog0: %016llx\n", data->dma0ErrorLog0);
723 pr_info(" dma0ErrorLog1: %016llx\n", data->dma0ErrorLog1);
724 pr_info(" dma1ErrorStatus: %016llx\n", data->dma1ErrorStatus);
725 pr_info(" dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
726 pr_info(" dma1ErrorLog0: %016llx\n", data->dma1ErrorLog0);
727 pr_info(" dma1ErrorLog1: %016llx\n", data->dma1ErrorLog1);
728
729 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
730 if ((data->pestA[i] >> 63) == 0 &&
731 (data->pestB[i] >> 63) == 0)
732 continue;
733
734 pr_info(" PE[%3d] PESTA: %016llx\n", i, data->pestA[i]);
735 pr_info(" PESTB: %016llx\n", data->pestB[i]);
736 }
737}
738
8c6852e0
GS		 739static void ioda_eeh_phb3_phb_diag(struct pci_controller *hose,
740 struct OpalIoPhbErrorCommon *common)
741{
742 struct OpalIoPhb3ErrorData *data;
743 int i;
744
745 data = (struct OpalIoPhb3ErrorData*)common;
746 pr_info("PHB3 PHB#%x Diag-data (Version: %d)\n\n",
747 hose->global_number, common->version);
748
749 pr_info(" brdgCtl: %08x\n", data->brdgCtl);
750
751 pr_info(" portStatusReg: %08x\n", data->portStatusReg);
752 pr_info(" rootCmplxStatus: %08x\n", data->rootCmplxStatus);
753 pr_info(" busAgentStatus: %08x\n", data->busAgentStatus);
754
755 pr_info(" deviceStatus: %08x\n", data->deviceStatus);
756 pr_info(" slotStatus: %08x\n", data->slotStatus);
757 pr_info(" linkStatus: %08x\n", data->linkStatus);
758 pr_info(" devCmdStatus: %08x\n", data->devCmdStatus);
759 pr_info(" devSecStatus: %08x\n", data->devSecStatus);
760
761 pr_info(" rootErrorStatus: %08x\n", data->rootErrorStatus);
762 pr_info(" uncorrErrorStatus: %08x\n", data->uncorrErrorStatus);
763 pr_info(" corrErrorStatus: %08x\n", data->corrErrorStatus);
764 pr_info(" tlpHdr1: %08x\n", data->tlpHdr1);
765 pr_info(" tlpHdr2: %08x\n", data->tlpHdr2);
766 pr_info(" tlpHdr3: %08x\n", data->tlpHdr3);
767 pr_info(" tlpHdr4: %08x\n", data->tlpHdr4);
768 pr_info(" sourceId: %08x\n", data->sourceId);
769 pr_info(" errorClass: %016llx\n", data->errorClass);
770 pr_info(" correlator: %016llx\n", data->correlator);
771 pr_info(" nFir: %016llx\n", data->nFir);
772 pr_info(" nFirMask: %016llx\n", data->nFirMask);
773 pr_info(" nFirWOF: %016llx\n", data->nFirWOF);
774 pr_info(" PhbPlssr: %016llx\n", data->phbPlssr);
775 pr_info(" PhbCsr: %016llx\n", data->phbCsr);
776 pr_info(" lemFir: %016llx\n", data->lemFir);
777 pr_info(" lemErrorMask: %016llx\n", data->lemErrorMask);
778 pr_info(" lemWOF: %016llx\n", data->lemWOF);
779 pr_info(" phbErrorStatus: %016llx\n", data->phbErrorStatus);
780 pr_info(" phbFirstErrorStatus: %016llx\n", data->phbFirstErrorStatus);
781 pr_info(" phbErrorLog0: %016llx\n", data->phbErrorLog0);
782 pr_info(" phbErrorLog1: %016llx\n", data->phbErrorLog1);
783 pr_info(" mmioErrorStatus: %016llx\n", data->mmioErrorStatus);
784 pr_info(" mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
785 pr_info(" mmioErrorLog0: %016llx\n", data->mmioErrorLog0);
786 pr_info(" mmioErrorLog1: %016llx\n", data->mmioErrorLog1);
787 pr_info(" dma0ErrorStatus: %016llx\n", data->dma0ErrorStatus);
788 pr_info(" dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
789 pr_info(" dma0ErrorLog0: %016llx\n", data->dma0ErrorLog0);
790 pr_info(" dma0ErrorLog1: %016llx\n", data->dma0ErrorLog1);
791 pr_info(" dma1ErrorStatus: %016llx\n", data->dma1ErrorStatus);
792 pr_info(" dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
793 pr_info(" dma1ErrorLog0: %016llx\n", data->dma1ErrorLog0);
794 pr_info(" dma1ErrorLog1: %016llx\n", data->dma1ErrorLog1);
795
796 for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) {
797 if ((data->pestA[i] >> 63) == 0 &&
798 (data->pestB[i] >> 63) == 0)
799 continue;
800
801 pr_info(" PE[%3d] PESTA: %016llx\n", i, data->pestA[i]);
802 pr_info(" PESTB: %016llx\n", data->pestB[i]);
803 }
804}
805
70f942db
GS		 806static void ioda_eeh_phb_diag(struct pci_controller *hose)
807{
808 struct pnv_phb *phb = hose->private_data;
809 struct OpalIoPhbErrorCommon *common;
810 long rc;
811
20acebdf
BH		 812 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
813 PNV_PCI_DIAG_BUF_SIZE);
70f942db
GS		 814 if (rc != OPAL_SUCCESS) {
815 pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n",
816 __func__, hose->global_number, rc);
817 return;
818 }
819
20acebdf 820 common = (struct OpalIoPhbErrorCommon *)phb->diag.blob;
70f942db
GS		 821 switch (common->ioType) {
822 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
823 ioda_eeh_p7ioc_phb_diag(hose, common);
824 break;
8c6852e0
GS		 825 case OPAL_PHB_ERROR_DATA_TYPE_PHB3:
826 ioda_eeh_phb3_phb_diag(hose, common);
827 break;
70f942db
GS		 828 default:
829 pr_warning("%s: Unrecognized I/O chip %d\n",
830 __func__, common->ioType);
831 }
832}
833
834static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
835 struct eeh_pe **pe)
836{
837 struct eeh_pe *phb_pe;
838
839 phb_pe = eeh_phb_pe_get(hose);
840 if (!phb_pe) {
841 pr_warning("%s Can't find PE for PHB#%d\n",
842 __func__, hose->global_number);
843 return -EEXIST;
844 }
845
846 *pe = phb_pe;
847 return 0;
848}
849
850static int ioda_eeh_get_pe(struct pci_controller *hose,
851 u16 pe_no, struct eeh_pe **pe)
852{
853 struct eeh_pe *phb_pe, *dev_pe;
854 struct eeh_dev dev;
855
856 /* Find the PHB PE */
857 if (ioda_eeh_get_phb_pe(hose, &phb_pe))
858 return -EEXIST;
859
860 /* Find the PE according to PE# */
861 memset(&dev, 0, sizeof(struct eeh_dev));
862 dev.phb = hose;
863 dev.pe_config_addr = pe_no;
864 dev_pe = eeh_pe_get(&dev);
865 if (!dev_pe) {
866 pr_warning("%s: Can't find PE for PHB#%x - PE#%x\n",
867 __func__, hose->global_number, pe_no);
868 return -EEXIST;
869 }
870
871 *pe = dev_pe;
872 return 0;
873}
874
875/**
876 * ioda_eeh_next_error - Retrieve next error for EEH core to handle
877 * @pe: The affected PE
878 *
879 * The function is expected to be called by EEH core while it gets
880 * special EEH event (without binding PE). The function calls to
881 * OPAL APIs for next error to handle. The informational error is
882 * handled internally by platform. However, the dead IOC, dead PHB,
883 * fenced PHB and frozen PE should be handled by EEH core eventually.
884 */
885static int ioda_eeh_next_error(struct eeh_pe **pe)
886{
887 struct pci_controller *hose, *tmp;
888 struct pnv_phb *phb;
889 u64 frozen_pe_no;
890 u16 err_type, severity;
891 long rc;
892 int ret = 1;
893
7cb9d93d
GS		 894 /*
895 * While running here, it's safe to purge the event queue.
896 * And we should keep the cached OPAL notifier event sychronized
897 * between the kernel and firmware.
898 */
70f942db 899 eeh_remove_event(NULL);
7cb9d93d 900 opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
70f942db
GS		 901
902 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
903 /*
904 * If the subordinate PCI buses of the PHB has been
905 * removed, we needn't take care of it any more.
906 */
907 phb = hose->private_data;
0b9e267d 908 if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
70f942db
GS		 909 continue;
910
911 rc = opal_pci_next_error(phb->opal_id,
912 &frozen_pe_no, &err_type, &severity);
913
914 /* If OPAL API returns error, we needn't proceed */
915 if (rc != OPAL_SUCCESS) {
20212703
MQ		 916 pr_devel("%s: Invalid return value on "
917 "PHB#%x (0x%lx) from opal_pci_next_error",
918 __func__, hose->global_number, rc);
70f942db
GS		 919 continue;
920 }
921
922 /* If the PHB doesn't have error, stop processing */
923 if (err_type == OPAL_EEH_NO_ERROR ||
924 severity == OPAL_EEH_SEV_NO_ERROR) {
20212703
MQ		 925 pr_devel("%s: No error found on PHB#%x\n",
926 __func__, hose->global_number);
70f942db
GS		 927 continue;
928 }
929
930 /*
931 * Processing the error. We're expecting the error with
932 * highest priority reported upon multiple errors on the
933 * specific PHB.
934 */
20212703
MQ		 935 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
936 __func__, err_type, severity,
937 frozen_pe_no, hose->global_number);
70f942db
GS		 938 switch (err_type) {
939 case OPAL_EEH_IOC_ERROR:
940 if (severity == OPAL_EEH_SEV_IOC_DEAD) {
941 list_for_each_entry_safe(hose, tmp,
942 &hose_list, list_node) {
943 phb = hose->private_data;
0b9e267d 944 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
70f942db
GS		 945 }
946
56ca4fde 947 pr_err("EEH: dead IOC detected\n");
70f942db
GS		 948 ret = 4;
949 goto out;
56ca4fde
GS		 950 } else if (severity == OPAL_EEH_SEV_INF) {
951 pr_info("EEH: IOC informative error "
952 "detected\n");
70f942db 953 ioda_eeh_hub_diag(hose);
56ca4fde 954 }
70f942db
GS		 955
956 break;
957 case OPAL_EEH_PHB_ERROR:
958 if (severity == OPAL_EEH_SEV_PHB_DEAD) {
959 if (ioda_eeh_get_phb_pe(hose, pe))
960 break;
961
56ca4fde
GS		 962 pr_err("EEH: dead PHB#%x detected\n",
963 hose->global_number);
0b9e267d 964 phb->eeh_state |= PNV_EEH_STATE_REMOVED;
70f942db
GS		 965 ret = 3;
966 goto out;
967 } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
968 if (ioda_eeh_get_phb_pe(hose, pe))
969 break;
970
56ca4fde
GS		 971 pr_err("EEH: fenced PHB#%x detected\n",
972 hose->global_number);
70f942db
GS		 973 ret = 2;
974 goto out;
56ca4fde
GS		 975 } else if (severity == OPAL_EEH_SEV_INF) {
976 pr_info("EEH: PHB#%x informative error "
977 "detected\n",
978 hose->global_number);
70f942db 979 ioda_eeh_phb_diag(hose);
56ca4fde 980 }
70f942db
GS		 981
982 break;
983 case OPAL_EEH_PE_ERROR:
984 if (ioda_eeh_get_pe(hose, frozen_pe_no, pe))
985 break;
986
56ca4fde
GS		 987 pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
988 (*pe)->addr, (*pe)->phb->global_number);
70f942db
GS		 989 ret = 1;
990 goto out;
991 }
992 }
993
994 ret = 0;
995out:
996 return ret;
997}
998
8747f363 999struct pnv_eeh_ops ioda_eeh_ops = {
73370c66 1000 .post_init = ioda_eeh_post_init,
eb005983 1001 .set_option = ioda_eeh_set_option,
8c41a7f3 1002 .get_state = ioda_eeh_get_state,
9d5cab00 1003 .reset = ioda_eeh_reset,
bf90dfea
GS		 1004 .get_log = ioda_eeh_get_log,
1005 .configure_bridge = ioda_eeh_configure_bridge,
70f942db 1006 .next_error = ioda_eeh_next_error
8747f363 1007};
Linux 6.x block layer and io_uring tree(s)