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[PATCH] irq-flags: PARISC: Use the new IRQF_ constants
[linux-2.6-block.git] / arch / powerpc / platforms / powermac / smp.c
CommitLineData
14cf11af
PM		 1/*
2 * SMP support for power macintosh.
3 *
4 * We support both the old "powersurge" SMP architecture
5 * and the current Core99 (G4 PowerMac) machines.
6 *
7 * Note that we don't support the very first rev. of
8 * Apple/DayStar 2 CPUs board, the one with the funky
9 * watchdog. Hopefully, none of these should be there except
10 * maybe internally to Apple. I should probably still add some
11 * code to detect this card though and disable SMP. --BenH.
12 *
13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15 *
16 * Support for DayStar quad CPU cards
17 * Copyright (C) XLR8, Inc. 1994-2000
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
14cf11af
PM		 24#include <linux/kernel.h>
25#include <linux/sched.h>
26#include <linux/smp.h>
27#include <linux/smp_lock.h>
28#include <linux/interrupt.h>
29#include <linux/kernel_stat.h>
30#include <linux/delay.h>
31#include <linux/init.h>
32#include <linux/spinlock.h>
33#include <linux/errno.h>
34#include <linux/hardirq.h>
35#include <linux/cpu.h>
54c4e6b5 36#include <linux/compiler.h>
14cf11af
PM		 37
38#include <asm/ptrace.h>
39#include <asm/atomic.h>
40#include <asm/irq.h>
41#include <asm/page.h>
42#include <asm/pgtable.h>
43#include <asm/sections.h>
44#include <asm/io.h>
45#include <asm/prom.h>
46#include <asm/smp.h>
14cf11af
PM		 47#include <asm/machdep.h>
48#include <asm/pmac_feature.h>
49#include <asm/time.h>
c0c0d996 50#include <asm/mpic.h>
14cf11af
PM		 51#include <asm/cacheflush.h>
52#include <asm/keylargo.h>
35499c01 53#include <asm/pmac_low_i2c.h>
5b9ca526 54#include <asm/pmac_pfunc.h>
35499c01 55
5b9ca526 56#define DEBUG
35499c01
PM		 57
58#ifdef DEBUG
59#define DBG(fmt...) udbg_printf(fmt)
60#else
61#define DBG(fmt...)
62#endif
63
64extern void __secondary_start_pmac_0(void);
5b9ca526 65extern int pmac_pfunc_base_install(void);
35499c01
PM		 66
67#ifdef CONFIG_PPC32
68
69/* Sync flag for HW tb sync */
70static volatile int sec_tb_reset = 0;
14cf11af
PM		 71
72/*
73 * Powersurge (old powermac SMP) support.
74 */
75
14cf11af
PM		 76/* Addresses for powersurge registers */
77#define HAMMERHEAD_BASE 0xf8000000
78#define HHEAD_CONFIG 0x90
79#define HHEAD_SEC_INTR 0xc0
80
81/* register for interrupting the primary processor on the powersurge */
82/* N.B. this is actually the ethernet ROM! */
83#define PSURGE_PRI_INTR 0xf3019000
84
85/* register for storing the start address for the secondary processor */
86/* N.B. this is the PCI config space address register for the 1st bridge */
87#define PSURGE_START 0xf2800000
88
89/* Daystar/XLR8 4-CPU card */
90#define PSURGE_QUAD_REG_ADDR 0xf8800000
91
92#define PSURGE_QUAD_IRQ_SET 0
93#define PSURGE_QUAD_IRQ_CLR 1
94#define PSURGE_QUAD_IRQ_PRIMARY 2
95#define PSURGE_QUAD_CKSTOP_CTL 3
96#define PSURGE_QUAD_PRIMARY_ARB 4
97#define PSURGE_QUAD_BOARD_ID 6
98#define PSURGE_QUAD_WHICH_CPU 7
99#define PSURGE_QUAD_CKSTOP_RDBK 8
100#define PSURGE_QUAD_RESET_CTL 11
101
102#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
103#define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
104#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
105#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
106
107/* virtual addresses for the above */
108static volatile u8 __iomem *hhead_base;
109static volatile u8 __iomem *quad_base;
110static volatile u32 __iomem *psurge_pri_intr;
111static volatile u8 __iomem *psurge_sec_intr;
112static volatile u32 __iomem *psurge_start;
113
114/* values for psurge_type */
115#define PSURGE_NONE -1
116#define PSURGE_DUAL 0
117#define PSURGE_QUAD_OKEE 1
118#define PSURGE_QUAD_COTTON 2
119#define PSURGE_QUAD_ICEGRASS 3
120
121/* what sort of powersurge board we have */
122static int psurge_type = PSURGE_NONE;
123
14cf11af
PM		 124/*
125 * Set and clear IPIs for powersurge.
126 */
127static inline void psurge_set_ipi(int cpu)
128{
129 if (psurge_type == PSURGE_NONE)
130 return;
131 if (cpu == 0)
132 in_be32(psurge_pri_intr);
133 else if (psurge_type == PSURGE_DUAL)
134 out_8(psurge_sec_intr, 0);
135 else
136 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
137}
138
139static inline void psurge_clr_ipi(int cpu)
140{
141 if (cpu > 0) {
142 switch(psurge_type) {
143 case PSURGE_DUAL:
144 out_8(psurge_sec_intr, ~0);
145 case PSURGE_NONE:
146 break;
147 default:
148 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
149 }
150 }
151}
152
153/*
154 * On powersurge (old SMP powermac architecture) we don't have
155 * separate IPIs for separate messages like openpic does. Instead
156 * we have a bitmap for each processor, where a 1 bit means that
157 * the corresponding message is pending for that processor.
158 * Ideally each cpu's entry would be in a different cache line.
159 * -- paulus.
160 */
161static unsigned long psurge_smp_message[NR_CPUS];
162
163void psurge_smp_message_recv(struct pt_regs *regs)
164{
165 int cpu = smp_processor_id();
166 int msg;
167
168 /* clear interrupt */
169 psurge_clr_ipi(cpu);
170
171 if (num_online_cpus() < 2)
172 return;
173
174 /* make sure there is a message there */
175 for (msg = 0; msg < 4; msg++)
176 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
177 smp_message_recv(msg, regs);
178}
179
180irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs)
181{
182 psurge_smp_message_recv(regs);
183 return IRQ_HANDLED;
184}
185
7ed476d1 186static void smp_psurge_message_pass(int target, int msg)
14cf11af
PM		 187{
188 int i;
189
190 if (num_online_cpus() < 2)
191 return;
192
394e3902 193 for_each_online_cpu(i) {
14cf11af
PM		 194 if (target == MSG_ALL
195 || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
196 || target == i) {
197 set_bit(msg, &psurge_smp_message[i]);
198 psurge_set_ipi(i);
199 }
200 }
201}
202
203/*
204 * Determine a quad card presence. We read the board ID register, we
205 * force the data bus to change to something else, and we read it again.
206 * It it's stable, then the register probably exist (ugh !)
207 */
208static int __init psurge_quad_probe(void)
209{
210 int type;
211 unsigned int i;
212
213 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
214 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
215 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
216 return PSURGE_DUAL;
217
218 /* looks OK, try a slightly more rigorous test */
219 /* bogus is not necessarily cacheline-aligned,
220 though I don't suppose that really matters. -- paulus */
221 for (i = 0; i < 100; i++) {
222 volatile u32 bogus[8];
223 bogus[(0+i)%8] = 0x00000000;
224 bogus[(1+i)%8] = 0x55555555;
225 bogus[(2+i)%8] = 0xFFFFFFFF;
226 bogus[(3+i)%8] = 0xAAAAAAAA;
227 bogus[(4+i)%8] = 0x33333333;
228 bogus[(5+i)%8] = 0xCCCCCCCC;
229 bogus[(6+i)%8] = 0xCCCCCCCC;
230 bogus[(7+i)%8] = 0x33333333;
231 wmb();
232 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
233 mb();
234 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
235 return PSURGE_DUAL;
236 }
237 return type;
238}
239
240static void __init psurge_quad_init(void)
241{
242 int procbits;
243
244 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
245 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
246 if (psurge_type == PSURGE_QUAD_ICEGRASS)
247 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
248 else
249 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
250 mdelay(33);
251 out_8(psurge_sec_intr, ~0);
252 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
253 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
254 if (psurge_type != PSURGE_QUAD_ICEGRASS)
255 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
256 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
257 mdelay(33);
258 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
259 mdelay(33);
260 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
261 mdelay(33);
262}
263
264static int __init smp_psurge_probe(void)
265{
266 int i, ncpus;
267
268 /* We don't do SMP on the PPC601 -- paulus */
269 if (PVR_VER(mfspr(SPRN_PVR)) == 1)
270 return 1;
271
272 /*
273 * The powersurge cpu board can be used in the generation
274 * of powermacs that have a socket for an upgradeable cpu card,
275 * including the 7500, 8500, 9500, 9600.
276 * The device tree doesn't tell you if you have 2 cpus because
277 * OF doesn't know anything about the 2nd processor.
278 * Instead we look for magic bits in magic registers,
279 * in the hammerhead memory controller in the case of the
280 * dual-cpu powersurge board. -- paulus.
281 */
282 if (find_devices("hammerhead") == NULL)
283 return 1;
284
285 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
286 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
287 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
288
289 psurge_type = psurge_quad_probe();
290 if (psurge_type != PSURGE_DUAL) {
291 psurge_quad_init();
292 /* All released cards using this HW design have 4 CPUs */
293 ncpus = 4;
294 } else {
295 iounmap(quad_base);
296 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
297 /* not a dual-cpu card */
298 iounmap(hhead_base);
299 psurge_type = PSURGE_NONE;
300 return 1;
301 }
302 ncpus = 2;
303 }
304
305 psurge_start = ioremap(PSURGE_START, 4);
306 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
307
094fe2e7
PM		 308 /*
309 * This is necessary because OF doesn't know about the
310 * secondary cpu(s), and thus there aren't nodes in the
311 * device tree for them, and smp_setup_cpu_maps hasn't
312 * set their bits in cpu_possible_map and cpu_present_map.
313 */
314 if (ncpus > NR_CPUS)
315 ncpus = NR_CPUS;
316 for (i = 1; i < ncpus ; ++i) {
317 cpu_set(i, cpu_present_map);
318 cpu_set(i, cpu_possible_map);
319 set_hard_smp_processor_id(i, i);
320 }
14cf11af
PM		 321
322 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
323
324 return ncpus;
325}
326
327static void __init smp_psurge_kick_cpu(int nr)
328{
329 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
330 unsigned long a;
331
332 /* may need to flush here if secondary bats aren't setup */
333 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
334 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
335 asm volatile("sync");
336
337 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
338
339 out_be32(psurge_start, start);
340 mb();
341
342 psurge_set_ipi(nr);
343 udelay(10);
344 psurge_clr_ipi(nr);
345
346 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
347}
348
349/*
350 * With the dual-cpu powersurge board, the decrementers and timebases
351 * of both cpus are frozen after the secondary cpu is started up,
352 * until we give the secondary cpu another interrupt. This routine
353 * uses this to get the timebases synchronized.
354 * -- paulus.
355 */
356static void __init psurge_dual_sync_tb(int cpu_nr)
357{
358 int t;
359
360 set_dec(tb_ticks_per_jiffy);
094fe2e7 361 /* XXX fixme */
14cf11af 362 set_tb(0, 0);
14cf11af
PM		 363
364 if (cpu_nr > 0) {
365 mb();
366 sec_tb_reset = 1;
367 return;
368 }
369
370 /* wait for the secondary to have reset its TB before proceeding */
371 for (t = 10000000; t > 0 && !sec_tb_reset; --t)
372 ;
373
374 /* now interrupt the secondary, starting both TBs */
375 psurge_set_ipi(1);
14cf11af
PM		 376}
377
378static struct irqaction psurge_irqaction = {
379 .handler = psurge_primary_intr,
380 .flags = SA_INTERRUPT,
381 .mask = CPU_MASK_NONE,
382 .name = "primary IPI",
383};
384
385static void __init smp_psurge_setup_cpu(int cpu_nr)
386{
387
388 if (cpu_nr == 0) {
389 /* If we failed to start the second CPU, we should still
390 * send it an IPI to start the timebase & DEC or we might
391 * have them stuck.
392 */
393 if (num_online_cpus() < 2) {
394 if (psurge_type == PSURGE_DUAL)
395 psurge_set_ipi(1);
396 return;
397 }
398 /* reset the entry point so if we get another intr we won't
399 * try to startup again */
400 out_be32(psurge_start, 0x100);
401 if (setup_irq(30, &psurge_irqaction))
402 printk(KERN_ERR "Couldn't get primary IPI interrupt");
403 }
404
405 if (psurge_type == PSURGE_DUAL)
406 psurge_dual_sync_tb(cpu_nr);
407}
408
409void __init smp_psurge_take_timebase(void)
410{
411 /* Dummy implementation */
412}
413
414void __init smp_psurge_give_timebase(void)
415{
416 /* Dummy implementation */
417}
418
35499c01
PM		 419/* PowerSurge-style Macs */
420struct smp_ops_t psurge_smp_ops = {
421 .message_pass = smp_psurge_message_pass,
422 .probe = smp_psurge_probe,
423 .kick_cpu = smp_psurge_kick_cpu,
424 .setup_cpu = smp_psurge_setup_cpu,
425 .give_timebase = smp_psurge_give_timebase,
426 .take_timebase = smp_psurge_take_timebase,
427};
428#endif /* CONFIG_PPC32 - actually powersurge support */
14cf11af 429
1beb6a7d
BH		 430/*
431 * Core 99 and later support
432 */
433
434static void (*pmac_tb_freeze)(int freeze);
0c2aca88 435static u64 timebase;
1beb6a7d
BH		 436static int tb_req;
437
438static void smp_core99_give_timebase(void)
439{
440 unsigned long flags;
441
442 local_irq_save(flags);
443
444 while(!tb_req)
445 barrier();
446 tb_req = 0;
447 (*pmac_tb_freeze)(1);
448 mb();
449 timebase = get_tb();
450 mb();
451 while (timebase)
452 barrier();
453 mb();
454 (*pmac_tb_freeze)(0);
455 mb();
456
457 local_irq_restore(flags);
458}
459
460
461static void __devinit smp_core99_take_timebase(void)
462{
463 unsigned long flags;
464
465 local_irq_save(flags);
466
467 tb_req = 1;
468 mb();
469 while (!timebase)
470 barrier();
471 mb();
472 set_tb(timebase >> 32, timebase & 0xffffffff);
473 timebase = 0;
474 mb();
475 set_dec(tb_ticks_per_jiffy/2);
476
477 local_irq_restore(flags);
478}
479
35499c01
PM		 480#ifdef CONFIG_PPC64
481/*
482 * G5s enable/disable the timebase via an i2c-connected clock chip.
483 */
730745a5 484static struct pmac_i2c_bus *pmac_tb_clock_chip_host;
35499c01 485static u8 pmac_tb_pulsar_addr;
14cf11af 486
35499c01
PM		 487static void smp_core99_cypress_tb_freeze(int freeze)
488{
489 u8 data;
490 int rc;
14cf11af 491
35499c01
PM		 492 /* Strangely, the device-tree says address is 0xd2, but darwin
493 * accesses 0xd0 ...
494 */
730745a5
BH		 495 pmac_i2c_setmode(pmac_tb_clock_chip_host,
496 pmac_i2c_mode_combined);
497 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
498 0xd0 | pmac_i2c_read,
499 1, 0x81, &data, 1);
35499c01
PM		 500 if (rc != 0)
501 goto bail;
502
503 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
504
730745a5
BH		 505 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
506 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
507 0xd0 | pmac_i2c_write,
508 1, 0x81, &data, 1);
35499c01
PM		 509
510 bail:
511 if (rc != 0) {
512 printk("Cypress Timebase %s rc: %d\n",
513 freeze ? "freeze" : "unfreeze", rc);
514 panic("Timebase freeze failed !\n");
14cf11af 515 }
14cf11af
PM		 516}
517
14cf11af 518
35499c01
PM		 519static void smp_core99_pulsar_tb_freeze(int freeze)
520{
521 u8 data;
522 int rc;
523
730745a5
BH		 524 pmac_i2c_setmode(pmac_tb_clock_chip_host,
525 pmac_i2c_mode_combined);
526 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
527 pmac_tb_pulsar_addr | pmac_i2c_read,
528 1, 0x2e, &data, 1);
35499c01
PM		 529 if (rc != 0)
530 goto bail;
531
532 data = (data & 0x88) | (freeze ? 0x11 : 0x22);
533
730745a5
BH		 534 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
535 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
536 pmac_tb_pulsar_addr | pmac_i2c_write,
537 1, 0x2e, &data, 1);
35499c01
PM		 538 bail:
539 if (rc != 0) {
540 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
541 freeze ? "freeze" : "unfreeze", rc);
542 panic("Timebase freeze failed !\n");
543 }
544}
14cf11af 545
1beb6a7d 546static void __init smp_core99_setup_i2c_hwsync(int ncpus)
14cf11af 547{
35499c01
PM		 548 struct device_node *cc = NULL;
549 struct device_node *p;
1beb6a7d 550 const char *name = NULL;
35499c01
PM		 551 u32 *reg;
552 int ok;
553
35499c01
PM		 554 /* Look for the clock chip */
555 while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) {
556 p = of_get_parent(cc);
557 ok = p && device_is_compatible(p, "uni-n-i2c");
558 of_node_put(p);
559 if (!ok)
560 continue;
14cf11af 561
730745a5
BH		 562 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
563 if (pmac_tb_clock_chip_host == NULL)
564 continue;
35499c01
PM		 565 reg = (u32 *)get_property(cc, "reg", NULL);
566 if (reg == NULL)
567 continue;
35499c01
PM		 568 switch (*reg) {
569 case 0xd2:
730745a5 570 if (device_is_compatible(cc,"pulsar-legacy-slewing")) {
35499c01
PM		 571 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
572 pmac_tb_pulsar_addr = 0xd2;
1beb6a7d 573 name = "Pulsar";
35499c01
PM		 574 } else if (device_is_compatible(cc, "cy28508")) {
575 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
1beb6a7d 576 name = "Cypress";
35499c01
PM		 577 }
578 break;
579 case 0xd4:
580 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
581 pmac_tb_pulsar_addr = 0xd4;
1beb6a7d 582 name = "Pulsar";
35499c01
PM		 583 break;
584 }
1beb6a7d 585 if (pmac_tb_freeze != NULL)
35499c01 586 break;
35499c01 587 }
1beb6a7d 588 if (pmac_tb_freeze != NULL) {
1beb6a7d 589 /* Open i2c bus for synchronous access */
730745a5
BH		 590 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) {
591 printk(KERN_ERR "Failed top open i2c bus for clock"
592 " sync, fallback to software sync !\n");
1beb6a7d
BH		 593 goto no_i2c_sync;
594 }
1beb6a7d
BH		 595 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
596 name);
597 return;
14cf11af 598 }
1beb6a7d
BH		 599 no_i2c_sync:
600 pmac_tb_freeze = NULL;
730745a5 601 pmac_tb_clock_chip_host = NULL;
14cf11af
PM		 602}
603
14cf11af 604
14cf11af 605
35499c01 606/*
5b9ca526
BH		 607 * Newer G5s uses a platform function
608 */
609
610static void smp_core99_pfunc_tb_freeze(int freeze)
611{
612 struct device_node *cpus;
613 struct pmf_args args;
614
615 cpus = of_find_node_by_path("/cpus");
616 BUG_ON(cpus == NULL);
617 args.count = 1;
618 args.u[0].v = !freeze;
619 pmf_call_function(cpus, "cpu-timebase", &args);
620 of_node_put(cpus);
621}
622
623#else /* CONFIG_PPC64 */
624
625/*
626 * SMP G4 use a GPIO to enable/disable the timebase.
35499c01 627 */
14cf11af 628
35499c01 629static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */
14cf11af 630
1beb6a7d 631static void smp_core99_gpio_tb_freeze(int freeze)
14cf11af 632{
1beb6a7d
BH		 633 if (freeze)
634 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
635 else
636 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
14cf11af 637 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
35499c01
PM		 638}
639
5b9ca526
BH		 640
641#endif /* !CONFIG_PPC64 */
642
35499c01
PM		 643/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
644volatile static long int core99_l2_cache;
645volatile static long int core99_l3_cache;
646
647static void __devinit core99_init_caches(int cpu)
14cf11af 648{
1beb6a7d 649#ifndef CONFIG_PPC64
35499c01 650 if (!cpu_has_feature(CPU_FTR_L2CR))
14cf11af 651 return;
35499c01
PM		 652
653 if (cpu == 0) {
654 core99_l2_cache = _get_L2CR();
655 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
656 } else {
657 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
658 _set_L2CR(0);
659 _set_L2CR(core99_l2_cache);
660 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
14cf11af 661 }
35499c01
PM		 662
663 if (!cpu_has_feature(CPU_FTR_L3CR))
664 return;
665
666 if (cpu == 0){
667 core99_l3_cache = _get_L3CR();
668 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
669 } else {
670 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
671 _set_L3CR(0);
672 _set_L3CR(core99_l3_cache);
673 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
14cf11af 674 }
1beb6a7d 675#endif /* !CONFIG_PPC64 */
14cf11af
PM		 676}
677
35499c01
PM		 678static void __init smp_core99_setup(int ncpus)
679{
1beb6a7d 680#ifdef CONFIG_PPC64
35499c01 681
1beb6a7d
BH		 682 /* i2c based HW sync on some G5s */
683 if (machine_is_compatible("PowerMac7,2") ||
684 machine_is_compatible("PowerMac7,3") ||
685 machine_is_compatible("RackMac3,1"))
686 smp_core99_setup_i2c_hwsync(ncpus);
687
5b9ca526 688 /* pfunc based HW sync on recent G5s */
1beb6a7d 689 if (pmac_tb_freeze == NULL) {
5b9ca526
BH		 690 struct device_node *cpus =
691 of_find_node_by_path("/cpus");
692 if (cpus &&
693 get_property(cpus, "platform-cpu-timebase", NULL)) {
694 pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
1beb6a7d 695 printk(KERN_INFO "Processor timebase sync using"
5b9ca526 696 " platform function\n");
1beb6a7d 697 }
35499c01
PM		 698 }
699
1beb6a7d
BH		 700#else /* CONFIG_PPC64 */
701
702 /* GPIO based HW sync on ppc32 Core99 */
703 if (pmac_tb_freeze == NULL && !machine_is_compatible("MacRISC4")) {
704 struct device_node *cpu;
705 u32 *tbprop = NULL;
706
707 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */
708 cpu = of_find_node_by_type(NULL, "cpu");
709 if (cpu != NULL) {
710 tbprop = (u32 *)get_property(cpu, "timebase-enable",
711 NULL);
712 if (tbprop)
713 core99_tb_gpio = *tbprop;
714 of_node_put(cpu);
715 }
716 pmac_tb_freeze = smp_core99_gpio_tb_freeze;
717 printk(KERN_INFO "Processor timebase sync using"
718 " GPIO 0x%02x\n", core99_tb_gpio);
719 }
720
721#endif /* CONFIG_PPC64 */
722
723 /* No timebase sync, fallback to software */
724 if (pmac_tb_freeze == NULL) {
725 smp_ops->give_timebase = smp_generic_give_timebase;
726 smp_ops->take_timebase = smp_generic_take_timebase;
727 printk(KERN_INFO "Processor timebase sync using software\n");
728 }
729
730#ifndef CONFIG_PPC64
731 {
732 int i;
733
734 /* XXX should get this from reg properties */
735 for (i = 1; i < ncpus; ++i)
736 smp_hw_index[i] = i;
737 }
35499c01
PM		 738#endif
739
1beb6a7d
BH		 740 /* 32 bits SMP can't NAP */
741 if (!machine_is_compatible("MacRISC4"))
742 powersave_nap = 0;
743}
744
35499c01
PM		 745static int __init smp_core99_probe(void)
746{
747 struct device_node *cpus;
748 int ncpus = 0;
749
750 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
751
752 /* Count CPUs in the device-tree */
753 for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
754 ++ncpus;
755
756 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
757
758 /* Nothing more to do if less than 2 of them */
759 if (ncpus <= 1)
760 return 1;
761
730745a5
BH		 762 /* We need to perform some early initialisations before we can start
763 * setting up SMP as we are running before initcalls
764 */
5b9ca526 765 pmac_pfunc_base_install();
730745a5
BH		 766 pmac_i2c_init();
767
768 /* Setup various bits like timebase sync method, ability to nap, ... */
35499c01 769 smp_core99_setup(ncpus);
730745a5
BH		 770
771 /* Install IPIs */
35499c01 772 mpic_request_ipis();
730745a5
BH		 773
774 /* Collect l2cr and l3cr values from CPU 0 */
35499c01
PM		 775 core99_init_caches(0);
776
777 return ncpus;
778}
779
780static void __devinit smp_core99_kick_cpu(int nr)
781{
782 unsigned int save_vector;
758438a7 783 unsigned long target, flags;
35499c01
PM		 784 volatile unsigned int *vector
785 = ((volatile unsigned int *)(KERNELBASE+0x100));
786
787 if (nr < 0 || nr > 3)
788 return;
758438a7
ME		 789
790 if (ppc_md.progress)
791 ppc_md.progress("smp_core99_kick_cpu", 0x346);
35499c01
PM		 792
793 local_irq_save(flags);
794 local_irq_disable();
795
796 /* Save reset vector */
797 save_vector = *vector;
798
758438a7 799 /* Setup fake reset vector that does
35499c01
PM		 800 * b __secondary_start_pmac_0 + nr*8 - KERNELBASE
801 */
758438a7
ME		 802 target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
803 create_branch((unsigned long)vector, target, BRANCH_SET_LINK);
35499c01
PM		 804
805 /* Put some life in our friend */
806 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
807
808 /* FIXME: We wait a bit for the CPU to take the exception, I should
809 * instead wait for the entry code to set something for me. Well,
810 * ideally, all that crap will be done in prom.c and the CPU left
811 * in a RAM-based wait loop like CHRP.
812 */
813 mdelay(1);
814
815 /* Restore our exception vector */
816 *vector = save_vector;
817 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
818
819 local_irq_restore(flags);
820 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
821}
822
823static void __devinit smp_core99_setup_cpu(int cpu_nr)
824{
825 /* Setup L2/L3 */
826 if (cpu_nr != 0)
827 core99_init_caches(cpu_nr);
828
829 /* Setup openpic */
830 mpic_setup_this_cpu();
831
832 if (cpu_nr == 0) {
1beb6a7d 833#ifdef CONFIG_PPC64
35499c01
PM		 834 extern void g5_phy_disable_cpu1(void);
835
1beb6a7d
BH		 836 /* Close i2c bus if it was used for tb sync */
837 if (pmac_tb_clock_chip_host) {
730745a5 838 pmac_i2c_close(pmac_tb_clock_chip_host);
1beb6a7d
BH		 839 pmac_tb_clock_chip_host = NULL;
840 }
841
35499c01
PM		 842 /* If we didn't start the second CPU, we must take
843 * it off the bus
844 */
845 if (machine_is_compatible("MacRISC4") &&
846 num_online_cpus() < 2)
847 g5_phy_disable_cpu1();
1beb6a7d
BH		 848#endif /* CONFIG_PPC64 */
849
850 if (ppc_md.progress)
851 ppc_md.progress("core99_setup_cpu 0 done", 0x349);
35499c01
PM		 852 }
853}
14cf11af 854
14cf11af 855
35499c01 856#if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
14cf11af 857
094fe2e7 858int smp_core99_cpu_disable(void)
14cf11af
PM		 859{
860 cpu_clear(smp_processor_id(), cpu_online_map);
861
862 /* XXX reset cpu affinity here */
c0c0d996 863 mpic_cpu_set_priority(0xf);
14cf11af
PM		 864 asm volatile("mtdec %0" : : "r" (0x7fffffff));
865 mb();
866 udelay(20);
867 asm volatile("mtdec %0" : : "r" (0x7fffffff));
868 return 0;
869}
870
35499c01 871extern void low_cpu_die(void) __attribute__((noreturn)); /* in sleep.S */
14cf11af
PM		 872static int cpu_dead[NR_CPUS];
873
874void cpu_die(void)
875{
876 local_irq_disable();
877 cpu_dead[smp_processor_id()] = 1;
878 mb();
879 low_cpu_die();
880}
881
094fe2e7 882void smp_core99_cpu_die(unsigned int cpu)
14cf11af
PM		 883{
884 int timeout;
885
886 timeout = 1000;
887 while (!cpu_dead[cpu]) {
888 if (--timeout == 0) {
889 printk("CPU %u refused to die!\n", cpu);
890 break;
891 }
892 msleep(1);
893 }
14cf11af
PM		 894 cpu_dead[cpu] = 0;
895}
896
897#endif
094fe2e7
PM		 898
899/* Core99 Macs (dual G4s and G5s) */
900struct smp_ops_t core99_smp_ops = {
901 .message_pass = smp_mpic_message_pass,
902 .probe = smp_core99_probe,
903 .kick_cpu = smp_core99_kick_cpu,
904 .setup_cpu = smp_core99_setup_cpu,
905 .give_timebase = smp_core99_give_timebase,
906 .take_timebase = smp_core99_take_timebase,
907#if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)
908 .cpu_disable = smp_core99_cpu_disable,
909 .cpu_die = smp_core99_cpu_die,
910#endif
911};
Linux 6.x block layer and io_uring tree(s)