Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
14cf11af PM |
2 | /* |
3 | * Support for the interrupt controllers found on Power Macintosh, | |
4 | * currently Apple's "Grand Central" interrupt controller in all | |
0ddbbb89 | 5 | * its incarnations. OpenPIC support used on newer machines is |
14cf11af PM |
6 | * in a separate file |
7 | * | |
8 | * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) | |
cc5d0189 BH |
9 | * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org) |
10 | * IBM, Corp. | |
14cf11af PM |
11 | */ |
12 | ||
14cf11af PM |
13 | #include <linux/stddef.h> |
14 | #include <linux/init.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/signal.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/interrupt.h> | |
f5a592f7 | 19 | #include <linux/syscore_ops.h> |
14cf11af | 20 | #include <linux/adb.h> |
a605b39e | 21 | #include <linux/minmax.h> |
14cf11af | 22 | #include <linux/pmu.h> |
e6f6390a CL |
23 | #include <linux/irqdomain.h> |
24 | #include <linux/of_address.h> | |
25 | #include <linux/of_irq.h> | |
14cf11af PM |
26 | |
27 | #include <asm/sections.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/smp.h> | |
14cf11af PM |
30 | #include <asm/pci-bridge.h> |
31 | #include <asm/time.h> | |
14cf11af PM |
32 | #include <asm/pmac_feature.h> |
33 | #include <asm/mpic.h> | |
af3b74df | 34 | #include <asm/xmon.h> |
14cf11af | 35 | |
3c3f42d6 | 36 | #include "pmac.h" |
14cf11af | 37 | |
3c3f42d6 | 38 | #ifdef CONFIG_PPC32 |
14cf11af PM |
39 | struct pmac_irq_hw { |
40 | unsigned int event; | |
41 | unsigned int enable; | |
42 | unsigned int ack; | |
43 | unsigned int level; | |
44 | }; | |
45 | ||
b83da291 GL |
46 | /* Workaround flags for 32bit powermac machines */ |
47 | unsigned int of_irq_workarounds; | |
48 | struct device_node *of_irq_dflt_pic; | |
49 | ||
14cf11af | 50 | /* Default addresses */ |
cc5d0189 | 51 | static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4]; |
14cf11af | 52 | |
14cf11af PM |
53 | static int max_irqs; |
54 | static int max_real_irqs; | |
14cf11af | 55 | |
d0eab3eb | 56 | static DEFINE_RAW_SPINLOCK(pmac_pic_lock); |
14cf11af | 57 | |
4013369f GL |
58 | /* The max irq number this driver deals with is 128; see max_irqs */ |
59 | static DECLARE_BITMAP(ppc_lost_interrupts, 128); | |
60 | static DECLARE_BITMAP(ppc_cached_irq_mask, 128); | |
b9e5b4e6 | 61 | static int pmac_irq_cascade = -1; |
bae1d8f1 | 62 | static struct irq_domain *pmac_pic_host; |
756e7104 | 63 | |
b9e5b4e6 | 64 | static void __pmac_retrigger(unsigned int irq_nr) |
14cf11af | 65 | { |
b9e5b4e6 BH |
66 | if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) { |
67 | __set_bit(irq_nr, ppc_lost_interrupts); | |
68 | irq_nr = pmac_irq_cascade; | |
69 | mb(); | |
70 | } | |
71 | if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) { | |
14cf11af | 72 | atomic_inc(&ppc_n_lost_interrupts); |
b9e5b4e6 | 73 | set_dec(1); |
14cf11af PM |
74 | } |
75 | } | |
76 | ||
d8c94aca | 77 | static void pmac_mask_and_ack_irq(struct irq_data *d) |
14cf11af | 78 | { |
476eb491 | 79 | unsigned int src = irqd_to_hwirq(d); |
ca72945d BH |
80 | unsigned long bit = 1UL << (src & 0x1f); |
81 | int i = src >> 5; | |
14cf11af PM |
82 | unsigned long flags; |
83 | ||
d0eab3eb | 84 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 BH |
85 | __clear_bit(src, ppc_cached_irq_mask); |
86 | if (__test_and_clear_bit(src, ppc_lost_interrupts)) | |
b9e5b4e6 | 87 | atomic_dec(&ppc_n_lost_interrupts); |
14cf11af PM |
88 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); |
89 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
90 | do { | |
91 | /* make sure ack gets to controller before we enable | |
92 | interrupts */ | |
93 | mb(); | |
94 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
95 | != (ppc_cached_irq_mask[i] & bit)); | |
d0eab3eb | 96 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
97 | } |
98 | ||
d8c94aca | 99 | static void pmac_ack_irq(struct irq_data *d) |
14cf11af | 100 | { |
476eb491 | 101 | unsigned int src = irqd_to_hwirq(d); |
0ebfff14 BH |
102 | unsigned long bit = 1UL << (src & 0x1f); |
103 | int i = src >> 5; | |
14cf11af PM |
104 | unsigned long flags; |
105 | ||
d0eab3eb | 106 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 | 107 | if (__test_and_clear_bit(src, ppc_lost_interrupts)) |
b9e5b4e6 BH |
108 | atomic_dec(&ppc_n_lost_interrupts); |
109 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
110 | (void)in_le32(&pmac_irq_hw[i]->ack); | |
d0eab3eb | 111 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 BH |
112 | } |
113 | ||
114 | static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) | |
115 | { | |
116 | unsigned long bit = 1UL << (irq_nr & 0x1f); | |
117 | int i = irq_nr >> 5; | |
118 | ||
119 | if ((unsigned)irq_nr >= max_irqs) | |
120 | return; | |
121 | ||
14cf11af PM |
122 | /* enable unmasked interrupts */ |
123 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); | |
124 | ||
125 | do { | |
126 | /* make sure mask gets to controller before we | |
127 | return to user */ | |
128 | mb(); | |
129 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
130 | != (ppc_cached_irq_mask[i] & bit)); | |
131 | ||
132 | /* | |
133 | * Unfortunately, setting the bit in the enable register | |
134 | * when the device interrupt is already on *doesn't* set | |
135 | * the bit in the flag register or request another interrupt. | |
136 | */ | |
137 | if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level)) | |
b9e5b4e6 | 138 | __pmac_retrigger(irq_nr); |
14cf11af PM |
139 | } |
140 | ||
141 | /* When an irq gets requested for the first client, if it's an | |
142 | * edge interrupt, we clear any previous one on the controller | |
143 | */ | |
d8c94aca | 144 | static unsigned int pmac_startup_irq(struct irq_data *d) |
14cf11af | 145 | { |
b9e5b4e6 | 146 | unsigned long flags; |
476eb491 | 147 | unsigned int src = irqd_to_hwirq(d); |
0ebfff14 BH |
148 | unsigned long bit = 1UL << (src & 0x1f); |
149 | int i = src >> 5; | |
14cf11af | 150 | |
d0eab3eb | 151 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
8c99f561 | 152 | if (!irqd_is_level_type(d)) |
14cf11af | 153 | out_le32(&pmac_irq_hw[i]->ack, bit); |
0ebfff14 BH |
154 | __set_bit(src, ppc_cached_irq_mask); |
155 | __pmac_set_irq_mask(src, 0); | |
d0eab3eb | 156 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
157 | |
158 | return 0; | |
159 | } | |
160 | ||
d8c94aca | 161 | static void pmac_mask_irq(struct irq_data *d) |
14cf11af | 162 | { |
b9e5b4e6 | 163 | unsigned long flags; |
476eb491 | 164 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 165 | |
d0eab3eb | 166 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 | 167 | __clear_bit(src, ppc_cached_irq_mask); |
ca72945d | 168 | __pmac_set_irq_mask(src, 1); |
d0eab3eb | 169 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
170 | } |
171 | ||
d8c94aca | 172 | static void pmac_unmask_irq(struct irq_data *d) |
14cf11af | 173 | { |
b9e5b4e6 | 174 | unsigned long flags; |
476eb491 | 175 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 176 | |
d0eab3eb | 177 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 BH |
178 | __set_bit(src, ppc_cached_irq_mask); |
179 | __pmac_set_irq_mask(src, 0); | |
d0eab3eb | 180 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
181 | } |
182 | ||
d8c94aca | 183 | static int pmac_retrigger(struct irq_data *d) |
14cf11af | 184 | { |
b9e5b4e6 | 185 | unsigned long flags; |
14cf11af | 186 | |
d0eab3eb | 187 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
476eb491 | 188 | __pmac_retrigger(irqd_to_hwirq(d)); |
d0eab3eb | 189 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 BH |
190 | return 1; |
191 | } | |
14cf11af | 192 | |
b9e5b4e6 | 193 | static struct irq_chip pmac_pic = { |
fc380c0c | 194 | .name = "PMAC-PIC", |
d8c94aca LB |
195 | .irq_startup = pmac_startup_irq, |
196 | .irq_mask = pmac_mask_irq, | |
197 | .irq_ack = pmac_ack_irq, | |
198 | .irq_mask_ack = pmac_mask_and_ack_irq, | |
199 | .irq_unmask = pmac_unmask_irq, | |
200 | .irq_retrigger = pmac_retrigger, | |
14cf11af PM |
201 | }; |
202 | ||
35a84c2f | 203 | static irqreturn_t gatwick_action(int cpl, void *dev_id) |
14cf11af | 204 | { |
b9e5b4e6 | 205 | unsigned long flags; |
14cf11af | 206 | int irq, bits; |
b9e5b4e6 | 207 | int rc = IRQ_NONE; |
14cf11af | 208 | |
d0eab3eb | 209 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
14cf11af PM |
210 | for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) { |
211 | int i = irq >> 5; | |
212 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
8e609d5e | 213 | bits |= in_le32(&pmac_irq_hw[i]->level); |
14cf11af PM |
214 | bits &= ppc_cached_irq_mask[i]; |
215 | if (bits == 0) | |
216 | continue; | |
217 | irq += __ilog2(bits); | |
d0eab3eb | 218 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
f11f76d4 | 219 | generic_handle_irq(irq); |
d0eab3eb | 220 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
b9e5b4e6 | 221 | rc = IRQ_HANDLED; |
14cf11af | 222 | } |
d0eab3eb | 223 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 | 224 | return rc; |
14cf11af PM |
225 | } |
226 | ||
35a84c2f | 227 | static unsigned int pmac_pic_get_irq(void) |
14cf11af PM |
228 | { |
229 | int irq; | |
230 | unsigned long bits = 0; | |
b9e5b4e6 | 231 | unsigned long flags; |
14cf11af | 232 | |
1ece355b | 233 | #ifdef CONFIG_PPC_PMAC32_PSURGE |
23f73a5f MM |
234 | /* IPI's are a hack on the powersurge -- Cort */ |
235 | if (smp_processor_id() != 0) { | |
236 | return psurge_secondary_virq; | |
14cf11af | 237 | } |
1ece355b | 238 | #endif /* CONFIG_PPC_PMAC32_PSURGE */ |
d0eab3eb | 239 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
14cf11af PM |
240 | for (irq = max_real_irqs; (irq -= 32) >= 0; ) { |
241 | int i = irq >> 5; | |
242 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
8e609d5e | 243 | bits |= in_le32(&pmac_irq_hw[i]->level); |
14cf11af PM |
244 | bits &= ppc_cached_irq_mask[i]; |
245 | if (bits == 0) | |
246 | continue; | |
247 | irq += __ilog2(bits); | |
248 | break; | |
249 | } | |
d0eab3eb | 250 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
0ebfff14 | 251 | if (unlikely(irq < 0)) |
ef24ba70 | 252 | return 0; |
0ebfff14 | 253 | return irq_linear_revmap(pmac_pic_host, irq); |
14cf11af PM |
254 | } |
255 | ||
ad3aedfb MZ |
256 | static int pmac_pic_host_match(struct irq_domain *h, struct device_node *node, |
257 | enum irq_domain_bus_token bus_token) | |
0ebfff14 BH |
258 | { |
259 | /* We match all, we don't always have a node anyway */ | |
260 | return 1; | |
261 | } | |
262 | ||
bae1d8f1 | 263 | static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq, |
6e99e458 | 264 | irq_hw_number_t hw) |
0ebfff14 | 265 | { |
0ebfff14 BH |
266 | if (hw >= max_irqs) |
267 | return -EINVAL; | |
268 | ||
269 | /* Mark level interrupts, set delayed disable for edge ones and set | |
270 | * handlers | |
271 | */ | |
8e609d5e BH |
272 | irq_set_status_flags(virq, IRQ_LEVEL); |
273 | irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq); | |
0ebfff14 BH |
274 | return 0; |
275 | } | |
276 | ||
9f70b8eb | 277 | static const struct irq_domain_ops pmac_pic_host_ops = { |
0ebfff14 BH |
278 | .match = pmac_pic_host_match, |
279 | .map = pmac_pic_host_map, | |
ff8c3ab8 | 280 | .xlate = irq_domain_xlate_onecell, |
0ebfff14 BH |
281 | }; |
282 | ||
cc5d0189 | 283 | static void __init pmac_pic_probe_oldstyle(void) |
3c3f42d6 | 284 | { |
3c3f42d6 | 285 | int i; |
cc5d0189 BH |
286 | struct device_node *master = NULL; |
287 | struct device_node *slave = NULL; | |
288 | u8 __iomem *addr; | |
289 | struct resource r; | |
14cf11af | 290 | |
cc5d0189 | 291 | /* Set our get_irq function */ |
0ebfff14 | 292 | ppc_md.get_irq = pmac_pic_get_irq; |
14cf11af | 293 | |
cc5d0189 BH |
294 | /* |
295 | * Find the interrupt controller type & node | |
14cf11af | 296 | */ |
cc5d0189 BH |
297 | |
298 | if ((master = of_find_node_by_name(NULL, "gc")) != NULL) { | |
299 | max_irqs = max_real_irqs = 32; | |
cc5d0189 BH |
300 | } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) { |
301 | max_irqs = max_real_irqs = 32; | |
14cf11af | 302 | /* We might have a second cascaded ohare */ |
cc5d0189 | 303 | slave = of_find_node_by_name(NULL, "pci106b,7"); |
8e609d5e | 304 | if (slave) |
cc5d0189 | 305 | max_irqs = 64; |
cc5d0189 BH |
306 | } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) { |
307 | max_irqs = max_real_irqs = 64; | |
cc5d0189 | 308 | |
14cf11af | 309 | /* We might have a second cascaded heathrow */ |
8f910fd0 GU |
310 | |
311 | /* Compensate for of_node_put() in of_find_node_by_name() */ | |
312 | of_node_get(master); | |
cc5d0189 BH |
313 | slave = of_find_node_by_name(master, "mac-io"); |
314 | ||
315 | /* Check ordering of master & slave */ | |
55b61fec | 316 | if (of_device_is_compatible(master, "gatwick")) { |
cc5d0189 | 317 | BUG_ON(slave == NULL); |
a605b39e | 318 | swap(master, slave); |
cc5d0189 | 319 | } |
14cf11af | 320 | |
cc5d0189 | 321 | /* We found a slave */ |
8e609d5e | 322 | if (slave) |
14cf11af | 323 | max_irqs = 128; |
14cf11af | 324 | } |
cc5d0189 BH |
325 | BUG_ON(master == NULL); |
326 | ||
0ebfff14 BH |
327 | /* |
328 | * Allocate an irq host | |
329 | */ | |
a8db8cf0 GL |
330 | pmac_pic_host = irq_domain_add_linear(master, max_irqs, |
331 | &pmac_pic_host_ops, NULL); | |
0ebfff14 BH |
332 | BUG_ON(pmac_pic_host == NULL); |
333 | irq_set_default_host(pmac_pic_host); | |
14cf11af | 334 | |
cc5d0189 BH |
335 | /* Get addresses of first controller if we have a node for it */ |
336 | BUG_ON(of_address_to_resource(master, 0, &r)); | |
337 | ||
338 | /* Map interrupts of primary controller */ | |
339 | addr = (u8 __iomem *) ioremap(r.start, 0x40); | |
340 | i = 0; | |
341 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
342 | (addr + 0x20); | |
343 | if (max_real_irqs > 32) | |
344 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
345 | (addr + 0x10); | |
346 | of_node_put(master); | |
347 | ||
b7c670d6 RH |
348 | printk(KERN_INFO "irq: Found primary Apple PIC %pOF for %d irqs\n", |
349 | master, max_real_irqs); | |
cc5d0189 BH |
350 | |
351 | /* Map interrupts of cascaded controller */ | |
352 | if (slave && !of_address_to_resource(slave, 0, &r)) { | |
353 | addr = (u8 __iomem *)ioremap(r.start, 0x40); | |
354 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
355 | (addr + 0x20); | |
356 | if (max_irqs > 64) | |
357 | pmac_irq_hw[i++] = | |
358 | (volatile struct pmac_irq_hw __iomem *) | |
359 | (addr + 0x10); | |
0ebfff14 | 360 | pmac_irq_cascade = irq_of_parse_and_map(slave, 0); |
cc5d0189 | 361 | |
b7c670d6 RH |
362 | printk(KERN_INFO "irq: Found slave Apple PIC %pOF for %d irqs" |
363 | " cascade: %d\n", slave, | |
b9e5b4e6 | 364 | max_irqs - max_real_irqs, pmac_irq_cascade); |
14cf11af | 365 | } |
cc5d0189 | 366 | of_node_put(slave); |
14cf11af | 367 | |
b9e5b4e6 | 368 | /* Disable all interrupts in all controllers */ |
14cf11af PM |
369 | for (i = 0; i * 32 < max_irqs; ++i) |
370 | out_le32(&pmac_irq_hw[i]->enable, 0); | |
cc5d0189 | 371 | |
b9e5b4e6 | 372 | /* Hookup cascade irq */ |
b4f00d5b | 373 | if (slave && pmac_irq_cascade) { |
374 | if (request_irq(pmac_irq_cascade, gatwick_action, | |
375 | IRQF_NO_THREAD, "cascade", NULL)) | |
376 | pr_err("Failed to register cascade interrupt\n"); | |
377 | } | |
14cf11af | 378 | |
cc5d0189 | 379 | printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs); |
14cf11af | 380 | #ifdef CONFIG_XMON |
b4f00d5b | 381 | i = irq_create_mapping(NULL, 20); |
382 | if (request_irq(i, xmon_irq, IRQF_NO_THREAD, "NMI - XMON", NULL)) | |
383 | pr_err("Failed to register NMI-XMON interrupt\n"); | |
cc5d0189 BH |
384 | #endif |
385 | } | |
b83da291 | 386 | |
bb12dd42 | 387 | int of_irq_parse_oldworld(const struct device_node *device, int index, |
530210c7 | 388 | struct of_phandle_args *out_irq) |
b83da291 GL |
389 | { |
390 | const u32 *ints = NULL; | |
391 | int intlen; | |
392 | ||
393 | /* | |
394 | * Old machines just have a list of interrupt numbers | |
395 | * and no interrupt-controller nodes. We also have dodgy | |
396 | * cases where the APPL,interrupts property is completely | |
397 | * missing behind pci-pci bridges and we have to get it | |
398 | * from the parent (the bridge itself, as apple just wired | |
399 | * everything together on these) | |
400 | */ | |
401 | while (device) { | |
402 | ints = of_get_property(device, "AAPL,interrupts", &intlen); | |
403 | if (ints != NULL) | |
404 | break; | |
405 | device = device->parent; | |
e5480bdc | 406 | if (!of_node_is_type(device, "pci")) |
b83da291 GL |
407 | break; |
408 | } | |
409 | if (ints == NULL) | |
410 | return -EINVAL; | |
411 | intlen /= sizeof(u32); | |
412 | ||
413 | if (index >= intlen) | |
414 | return -EINVAL; | |
415 | ||
530210c7 GL |
416 | out_irq->np = NULL; |
417 | out_irq->args[0] = ints[index]; | |
418 | out_irq->args_count = 1; | |
b83da291 GL |
419 | |
420 | return 0; | |
421 | } | |
cc5d0189 BH |
422 | #endif /* CONFIG_PPC32 */ |
423 | ||
cc5d0189 BH |
424 | static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) |
425 | { | |
426 | #if defined(CONFIG_XMON) && defined(CONFIG_PPC32) | |
427 | struct device_node* pswitch; | |
428 | int nmi_irq; | |
429 | ||
430 | pswitch = of_find_node_by_name(NULL, "programmer-switch"); | |
0ebfff14 BH |
431 | if (pswitch) { |
432 | nmi_irq = irq_of_parse_and_map(pswitch, 0); | |
ef24ba70 | 433 | if (nmi_irq) { |
0ebfff14 | 434 | mpic_irq_set_priority(nmi_irq, 9); |
b4f00d5b | 435 | if (request_irq(nmi_irq, xmon_irq, IRQF_NO_THREAD, |
436 | "NMI - XMON", NULL)) | |
437 | pr_err("Failed to register NMI-XMON interrupt\n"); | |
0ebfff14 BH |
438 | } |
439 | of_node_put(pswitch); | |
cc5d0189 | 440 | } |
cc5d0189 BH |
441 | #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */ |
442 | } | |
443 | ||
1beb6a7d BH |
444 | static struct mpic * __init pmac_setup_one_mpic(struct device_node *np, |
445 | int master) | |
446 | { | |
1beb6a7d | 447 | const char *name = master ? " MPIC 1 " : " MPIC 2 "; |
1beb6a7d | 448 | struct mpic *mpic; |
be8bec56 | 449 | unsigned int flags = master ? 0 : MPIC_SECONDARY; |
1beb6a7d BH |
450 | |
451 | pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0); | |
452 | ||
4d57e351 | 453 | if (of_property_read_bool(np, "big-endian")) |
1beb6a7d BH |
454 | flags |= MPIC_BIG_ENDIAN; |
455 | ||
456 | /* Primary Big Endian means HT interrupts. This is quite dodgy | |
457 | * but works until I find a better way | |
458 | */ | |
459 | if (master && (flags & MPIC_BIG_ENDIAN)) | |
6cfef5b2 | 460 | flags |= MPIC_U3_HT_IRQS; |
1beb6a7d | 461 | |
8bf41568 | 462 | mpic = mpic_alloc(np, 0, flags, 0, 0, name); |
1beb6a7d BH |
463 | if (mpic == NULL) |
464 | return NULL; | |
465 | ||
466 | mpic_init(mpic); | |
467 | ||
468 | return mpic; | |
469 | } | |
470 | ||
cc5d0189 BH |
471 | static int __init pmac_pic_probe_mpic(void) |
472 | { | |
473 | struct mpic *mpic1, *mpic2; | |
474 | struct device_node *np, *master = NULL, *slave = NULL; | |
cc5d0189 BH |
475 | |
476 | /* We can have up to 2 MPICs cascaded */ | |
9625e69a | 477 | for_each_node_by_type(np, "open-pic") { |
857d423c | 478 | if (master == NULL && !of_property_present(np, "interrupts")) |
cc5d0189 BH |
479 | master = of_node_get(np); |
480 | else if (slave == NULL) | |
481 | slave = of_node_get(np); | |
9625e69a DT |
482 | if (master && slave) { |
483 | of_node_put(np); | |
cc5d0189 | 484 | break; |
9625e69a | 485 | } |
cc5d0189 BH |
486 | } |
487 | ||
488 | /* Check for bogus setups */ | |
489 | if (master == NULL && slave != NULL) { | |
490 | master = slave; | |
491 | slave = NULL; | |
492 | } | |
493 | ||
494 | /* Not found, default to good old pmac pic */ | |
495 | if (master == NULL) | |
496 | return -ENODEV; | |
497 | ||
498 | /* Set master handler */ | |
499 | ppc_md.get_irq = mpic_get_irq; | |
500 | ||
501 | /* Setup master */ | |
1beb6a7d | 502 | mpic1 = pmac_setup_one_mpic(master, 1); |
cc5d0189 | 503 | BUG_ON(mpic1 == NULL); |
cc5d0189 BH |
504 | |
505 | /* Install NMI if any */ | |
506 | pmac_pic_setup_mpic_nmi(mpic1); | |
507 | ||
508 | of_node_put(master); | |
509 | ||
09dc34a9 KM |
510 | /* Set up a cascaded controller, if present */ |
511 | if (slave) { | |
512 | mpic2 = pmac_setup_one_mpic(slave, 0); | |
513 | if (mpic2 == NULL) | |
514 | printk(KERN_ERR "Failed to setup slave MPIC\n"); | |
1beb6a7d | 515 | of_node_put(slave); |
cc5d0189 | 516 | } |
cc5d0189 | 517 | |
cc5d0189 BH |
518 | return 0; |
519 | } | |
520 | ||
521 | ||
522 | void __init pmac_pic_init(void) | |
523 | { | |
0ebfff14 | 524 | /* We configure the OF parsing based on our oldworld vs. newworld |
48fc7f7e | 525 | * platform type and whether we were booted by BootX. |
0ebfff14 BH |
526 | */ |
527 | #ifdef CONFIG_PPC32 | |
528 | if (!pmac_newworld) | |
b83da291 | 529 | of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC; |
4d57e351 | 530 | if (of_property_read_bool(of_chosen, "linux,bootx")) |
b83da291 | 531 | of_irq_workarounds |= OF_IMAP_NO_PHANDLE; |
0ebfff14 | 532 | |
b83da291 GL |
533 | /* If we don't have phandles on a newworld, then try to locate a |
534 | * default interrupt controller (happens when booting with BootX). | |
535 | * We do a first match here, hopefully, that only ever happens on | |
536 | * machines with one controller. | |
537 | */ | |
538 | if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) { | |
539 | struct device_node *np; | |
540 | ||
541 | for_each_node_with_property(np, "interrupt-controller") { | |
542 | /* Skip /chosen/interrupt-controller */ | |
2c8e65b5 | 543 | if (of_node_name_eq(np, "chosen")) |
b83da291 GL |
544 | continue; |
545 | /* It seems like at least one person wants | |
546 | * to use BootX on a machine with an AppleKiwi | |
547 | * controller which happens to pretend to be an | |
548 | * interrupt controller too. */ | |
2c8e65b5 | 549 | if (of_node_name_eq(np, "AppleKiwi")) |
b83da291 GL |
550 | continue; |
551 | /* I think we found one ! */ | |
552 | of_irq_dflt_pic = np; | |
553 | break; | |
554 | } | |
555 | } | |
556 | #endif /* CONFIG_PPC32 */ | |
6e99e458 | 557 | |
cc5d0189 BH |
558 | /* We first try to detect Apple's new Core99 chipset, since mac-io |
559 | * is quite different on those machines and contains an IBM MPIC2. | |
560 | */ | |
561 | if (pmac_pic_probe_mpic() == 0) | |
562 | return; | |
563 | ||
564 | #ifdef CONFIG_PPC32 | |
565 | pmac_pic_probe_oldstyle(); | |
566 | #endif | |
14cf11af PM |
567 | } |
568 | ||
a0005034 | 569 | #if defined(CONFIG_PM) && defined(CONFIG_PPC32) |
14cf11af PM |
570 | /* |
571 | * These procedures are used in implementing sleep on the powerbooks. | |
572 | * sleep_save_intrs() saves the states of all interrupt enables | |
573 | * and disables all interrupts except for the nominated one. | |
574 | * sleep_restore_intrs() restores the states of all interrupt enables. | |
575 | */ | |
576 | unsigned long sleep_save_mask[2]; | |
577 | ||
578 | /* This used to be passed by the PMU driver but that link got | |
579 | * broken with the new driver model. We use this tweak for now... | |
0ebfff14 | 580 | * We really want to do things differently though... |
14cf11af PM |
581 | */ |
582 | static int pmacpic_find_viaint(void) | |
583 | { | |
584 | int viaint = -1; | |
585 | ||
586 | #ifdef CONFIG_ADB_PMU | |
587 | struct device_node *np; | |
588 | ||
589 | if (pmu_get_model() != PMU_OHARE_BASED) | |
590 | goto not_found; | |
591 | np = of_find_node_by_name(NULL, "via-pmu"); | |
592 | if (np == NULL) | |
593 | goto not_found; | |
d258e64e | 594 | viaint = irq_of_parse_and_map(np, 0); |
2aaf0a19 | 595 | of_node_put(np); |
14cf11af PM |
596 | |
597 | not_found: | |
98cddbfb | 598 | #endif /* CONFIG_ADB_PMU */ |
14cf11af PM |
599 | return viaint; |
600 | } | |
601 | ||
f5a592f7 | 602 | static int pmacpic_suspend(void) |
14cf11af PM |
603 | { |
604 | int viaint = pmacpic_find_viaint(); | |
605 | ||
606 | sleep_save_mask[0] = ppc_cached_irq_mask[0]; | |
607 | sleep_save_mask[1] = ppc_cached_irq_mask[1]; | |
608 | ppc_cached_irq_mask[0] = 0; | |
609 | ppc_cached_irq_mask[1] = 0; | |
610 | if (viaint > 0) | |
611 | set_bit(viaint, ppc_cached_irq_mask); | |
612 | out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]); | |
613 | if (max_real_irqs > 32) | |
614 | out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]); | |
615 | (void)in_le32(&pmac_irq_hw[0]->event); | |
616 | /* make sure mask gets to controller before we return to caller */ | |
617 | mb(); | |
618 | (void)in_le32(&pmac_irq_hw[0]->enable); | |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
f5a592f7 | 623 | static void pmacpic_resume(void) |
14cf11af PM |
624 | { |
625 | int i; | |
626 | ||
627 | out_le32(&pmac_irq_hw[0]->enable, 0); | |
628 | if (max_real_irqs > 32) | |
629 | out_le32(&pmac_irq_hw[1]->enable, 0); | |
630 | mb(); | |
631 | for (i = 0; i < max_real_irqs; ++i) | |
632 | if (test_bit(i, sleep_save_mask)) | |
d8c94aca | 633 | pmac_unmask_irq(irq_get_irq_data(i)); |
14cf11af PM |
634 | } |
635 | ||
f5a592f7 RW |
636 | static struct syscore_ops pmacpic_syscore_ops = { |
637 | .suspend = pmacpic_suspend, | |
638 | .resume = pmacpic_resume, | |
14cf11af PM |
639 | }; |
640 | ||
f5a592f7 | 641 | static int __init init_pmacpic_syscore(void) |
14cf11af | 642 | { |
339dedf7 BH |
643 | if (pmac_irq_hw[0]) |
644 | register_syscore_ops(&pmacpic_syscore_ops); | |
14cf11af PM |
645 | return 0; |
646 | } | |
14cf11af | 647 | |
f5a592f7 RW |
648 | machine_subsys_initcall(powermac, init_pmacpic_syscore); |
649 | ||
650 | #endif /* CONFIG_PM && CONFIG_PPC32 */ |