Commit | Line | Data |
---|---|---|
14cf11af PM |
1 | /* |
2 | * Support for the interrupt controllers found on Power Macintosh, | |
3 | * currently Apple's "Grand Central" interrupt controller in all | |
4 | * it's incarnations. OpenPIC support used on newer machines is | |
5 | * in a separate file | |
6 | * | |
7 | * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) | |
cc5d0189 BH |
8 | * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org) |
9 | * IBM, Corp. | |
14cf11af PM |
10 | * |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/stddef.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/signal.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/interrupt.h> | |
f5a592f7 | 24 | #include <linux/syscore_ops.h> |
14cf11af PM |
25 | #include <linux/adb.h> |
26 | #include <linux/pmu.h> | |
27 | ||
28 | #include <asm/sections.h> | |
29 | #include <asm/io.h> | |
30 | #include <asm/smp.h> | |
31 | #include <asm/prom.h> | |
32 | #include <asm/pci-bridge.h> | |
33 | #include <asm/time.h> | |
14cf11af PM |
34 | #include <asm/pmac_feature.h> |
35 | #include <asm/mpic.h> | |
af3b74df | 36 | #include <asm/xmon.h> |
14cf11af | 37 | |
3c3f42d6 | 38 | #include "pmac.h" |
14cf11af | 39 | |
3c3f42d6 | 40 | #ifdef CONFIG_PPC32 |
14cf11af PM |
41 | struct pmac_irq_hw { |
42 | unsigned int event; | |
43 | unsigned int enable; | |
44 | unsigned int ack; | |
45 | unsigned int level; | |
46 | }; | |
47 | ||
b83da291 GL |
48 | /* Workaround flags for 32bit powermac machines */ |
49 | unsigned int of_irq_workarounds; | |
50 | struct device_node *of_irq_dflt_pic; | |
51 | ||
14cf11af | 52 | /* Default addresses */ |
cc5d0189 | 53 | static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4]; |
14cf11af | 54 | |
14cf11af PM |
55 | static int max_irqs; |
56 | static int max_real_irqs; | |
14cf11af | 57 | |
d0eab3eb | 58 | static DEFINE_RAW_SPINLOCK(pmac_pic_lock); |
14cf11af | 59 | |
4013369f GL |
60 | /* The max irq number this driver deals with is 128; see max_irqs */ |
61 | static DECLARE_BITMAP(ppc_lost_interrupts, 128); | |
62 | static DECLARE_BITMAP(ppc_cached_irq_mask, 128); | |
b9e5b4e6 | 63 | static int pmac_irq_cascade = -1; |
bae1d8f1 | 64 | static struct irq_domain *pmac_pic_host; |
756e7104 | 65 | |
b9e5b4e6 | 66 | static void __pmac_retrigger(unsigned int irq_nr) |
14cf11af | 67 | { |
b9e5b4e6 BH |
68 | if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) { |
69 | __set_bit(irq_nr, ppc_lost_interrupts); | |
70 | irq_nr = pmac_irq_cascade; | |
71 | mb(); | |
72 | } | |
73 | if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) { | |
14cf11af | 74 | atomic_inc(&ppc_n_lost_interrupts); |
b9e5b4e6 | 75 | set_dec(1); |
14cf11af PM |
76 | } |
77 | } | |
78 | ||
d8c94aca | 79 | static void pmac_mask_and_ack_irq(struct irq_data *d) |
14cf11af | 80 | { |
476eb491 | 81 | unsigned int src = irqd_to_hwirq(d); |
ca72945d BH |
82 | unsigned long bit = 1UL << (src & 0x1f); |
83 | int i = src >> 5; | |
14cf11af PM |
84 | unsigned long flags; |
85 | ||
d0eab3eb | 86 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 BH |
87 | __clear_bit(src, ppc_cached_irq_mask); |
88 | if (__test_and_clear_bit(src, ppc_lost_interrupts)) | |
b9e5b4e6 | 89 | atomic_dec(&ppc_n_lost_interrupts); |
14cf11af PM |
90 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); |
91 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
92 | do { | |
93 | /* make sure ack gets to controller before we enable | |
94 | interrupts */ | |
95 | mb(); | |
96 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
97 | != (ppc_cached_irq_mask[i] & bit)); | |
d0eab3eb | 98 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
99 | } |
100 | ||
d8c94aca | 101 | static void pmac_ack_irq(struct irq_data *d) |
14cf11af | 102 | { |
476eb491 | 103 | unsigned int src = irqd_to_hwirq(d); |
0ebfff14 BH |
104 | unsigned long bit = 1UL << (src & 0x1f); |
105 | int i = src >> 5; | |
14cf11af PM |
106 | unsigned long flags; |
107 | ||
d0eab3eb | 108 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 | 109 | if (__test_and_clear_bit(src, ppc_lost_interrupts)) |
b9e5b4e6 BH |
110 | atomic_dec(&ppc_n_lost_interrupts); |
111 | out_le32(&pmac_irq_hw[i]->ack, bit); | |
112 | (void)in_le32(&pmac_irq_hw[i]->ack); | |
d0eab3eb | 113 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 BH |
114 | } |
115 | ||
116 | static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) | |
117 | { | |
118 | unsigned long bit = 1UL << (irq_nr & 0x1f); | |
119 | int i = irq_nr >> 5; | |
120 | ||
121 | if ((unsigned)irq_nr >= max_irqs) | |
122 | return; | |
123 | ||
14cf11af PM |
124 | /* enable unmasked interrupts */ |
125 | out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); | |
126 | ||
127 | do { | |
128 | /* make sure mask gets to controller before we | |
129 | return to user */ | |
130 | mb(); | |
131 | } while((in_le32(&pmac_irq_hw[i]->enable) & bit) | |
132 | != (ppc_cached_irq_mask[i] & bit)); | |
133 | ||
134 | /* | |
135 | * Unfortunately, setting the bit in the enable register | |
136 | * when the device interrupt is already on *doesn't* set | |
137 | * the bit in the flag register or request another interrupt. | |
138 | */ | |
139 | if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level)) | |
b9e5b4e6 | 140 | __pmac_retrigger(irq_nr); |
14cf11af PM |
141 | } |
142 | ||
143 | /* When an irq gets requested for the first client, if it's an | |
144 | * edge interrupt, we clear any previous one on the controller | |
145 | */ | |
d8c94aca | 146 | static unsigned int pmac_startup_irq(struct irq_data *d) |
14cf11af | 147 | { |
b9e5b4e6 | 148 | unsigned long flags; |
476eb491 | 149 | unsigned int src = irqd_to_hwirq(d); |
0ebfff14 BH |
150 | unsigned long bit = 1UL << (src & 0x1f); |
151 | int i = src >> 5; | |
14cf11af | 152 | |
d0eab3eb | 153 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
8c99f561 | 154 | if (!irqd_is_level_type(d)) |
14cf11af | 155 | out_le32(&pmac_irq_hw[i]->ack, bit); |
0ebfff14 BH |
156 | __set_bit(src, ppc_cached_irq_mask); |
157 | __pmac_set_irq_mask(src, 0); | |
d0eab3eb | 158 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
159 | |
160 | return 0; | |
161 | } | |
162 | ||
d8c94aca | 163 | static void pmac_mask_irq(struct irq_data *d) |
14cf11af | 164 | { |
b9e5b4e6 | 165 | unsigned long flags; |
476eb491 | 166 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 167 | |
d0eab3eb | 168 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 | 169 | __clear_bit(src, ppc_cached_irq_mask); |
ca72945d | 170 | __pmac_set_irq_mask(src, 1); |
d0eab3eb | 171 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
172 | } |
173 | ||
d8c94aca | 174 | static void pmac_unmask_irq(struct irq_data *d) |
14cf11af | 175 | { |
b9e5b4e6 | 176 | unsigned long flags; |
476eb491 | 177 | unsigned int src = irqd_to_hwirq(d); |
b9e5b4e6 | 178 | |
d0eab3eb | 179 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
0ebfff14 BH |
180 | __set_bit(src, ppc_cached_irq_mask); |
181 | __pmac_set_irq_mask(src, 0); | |
d0eab3eb | 182 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
14cf11af PM |
183 | } |
184 | ||
d8c94aca | 185 | static int pmac_retrigger(struct irq_data *d) |
14cf11af | 186 | { |
b9e5b4e6 | 187 | unsigned long flags; |
14cf11af | 188 | |
d0eab3eb | 189 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
476eb491 | 190 | __pmac_retrigger(irqd_to_hwirq(d)); |
d0eab3eb | 191 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 BH |
192 | return 1; |
193 | } | |
14cf11af | 194 | |
b9e5b4e6 | 195 | static struct irq_chip pmac_pic = { |
fc380c0c | 196 | .name = "PMAC-PIC", |
d8c94aca LB |
197 | .irq_startup = pmac_startup_irq, |
198 | .irq_mask = pmac_mask_irq, | |
199 | .irq_ack = pmac_ack_irq, | |
200 | .irq_mask_ack = pmac_mask_and_ack_irq, | |
201 | .irq_unmask = pmac_unmask_irq, | |
202 | .irq_retrigger = pmac_retrigger, | |
14cf11af PM |
203 | }; |
204 | ||
35a84c2f | 205 | static irqreturn_t gatwick_action(int cpl, void *dev_id) |
14cf11af | 206 | { |
b9e5b4e6 | 207 | unsigned long flags; |
14cf11af | 208 | int irq, bits; |
b9e5b4e6 | 209 | int rc = IRQ_NONE; |
14cf11af | 210 | |
d0eab3eb | 211 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
14cf11af PM |
212 | for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) { |
213 | int i = irq >> 5; | |
214 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
8e609d5e | 215 | bits |= in_le32(&pmac_irq_hw[i]->level); |
14cf11af PM |
216 | bits &= ppc_cached_irq_mask[i]; |
217 | if (bits == 0) | |
218 | continue; | |
219 | irq += __ilog2(bits); | |
d0eab3eb | 220 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
f11f76d4 | 221 | generic_handle_irq(irq); |
d0eab3eb | 222 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
b9e5b4e6 | 223 | rc = IRQ_HANDLED; |
14cf11af | 224 | } |
d0eab3eb | 225 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
b9e5b4e6 | 226 | return rc; |
14cf11af PM |
227 | } |
228 | ||
35a84c2f | 229 | static unsigned int pmac_pic_get_irq(void) |
14cf11af PM |
230 | { |
231 | int irq; | |
232 | unsigned long bits = 0; | |
b9e5b4e6 | 233 | unsigned long flags; |
14cf11af | 234 | |
1ece355b | 235 | #ifdef CONFIG_PPC_PMAC32_PSURGE |
23f73a5f MM |
236 | /* IPI's are a hack on the powersurge -- Cort */ |
237 | if (smp_processor_id() != 0) { | |
238 | return psurge_secondary_virq; | |
14cf11af | 239 | } |
1ece355b | 240 | #endif /* CONFIG_PPC_PMAC32_PSURGE */ |
d0eab3eb | 241 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
14cf11af PM |
242 | for (irq = max_real_irqs; (irq -= 32) >= 0; ) { |
243 | int i = irq >> 5; | |
244 | bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; | |
8e609d5e | 245 | bits |= in_le32(&pmac_irq_hw[i]->level); |
14cf11af PM |
246 | bits &= ppc_cached_irq_mask[i]; |
247 | if (bits == 0) | |
248 | continue; | |
249 | irq += __ilog2(bits); | |
250 | break; | |
251 | } | |
d0eab3eb | 252 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
0ebfff14 | 253 | if (unlikely(irq < 0)) |
ef24ba70 | 254 | return 0; |
0ebfff14 | 255 | return irq_linear_revmap(pmac_pic_host, irq); |
14cf11af PM |
256 | } |
257 | ||
14cf11af PM |
258 | #ifdef CONFIG_XMON |
259 | static struct irqaction xmon_action = { | |
260 | .handler = xmon_irq, | |
57f88947 | 261 | .flags = IRQF_NO_THREAD, |
14cf11af PM |
262 | .name = "NMI - XMON" |
263 | }; | |
264 | #endif | |
265 | ||
266 | static struct irqaction gatwick_cascade_action = { | |
267 | .handler = gatwick_action, | |
57f88947 | 268 | .flags = IRQF_NO_THREAD, |
14cf11af PM |
269 | .name = "cascade", |
270 | }; | |
3c3f42d6 | 271 | |
ad3aedfb MZ |
272 | static int pmac_pic_host_match(struct irq_domain *h, struct device_node *node, |
273 | enum irq_domain_bus_token bus_token) | |
0ebfff14 BH |
274 | { |
275 | /* We match all, we don't always have a node anyway */ | |
276 | return 1; | |
277 | } | |
278 | ||
bae1d8f1 | 279 | static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq, |
6e99e458 | 280 | irq_hw_number_t hw) |
0ebfff14 | 281 | { |
0ebfff14 BH |
282 | if (hw >= max_irqs) |
283 | return -EINVAL; | |
284 | ||
285 | /* Mark level interrupts, set delayed disable for edge ones and set | |
286 | * handlers | |
287 | */ | |
8e609d5e BH |
288 | irq_set_status_flags(virq, IRQ_LEVEL); |
289 | irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq); | |
0ebfff14 BH |
290 | return 0; |
291 | } | |
292 | ||
9f70b8eb | 293 | static const struct irq_domain_ops pmac_pic_host_ops = { |
0ebfff14 BH |
294 | .match = pmac_pic_host_match, |
295 | .map = pmac_pic_host_map, | |
ff8c3ab8 | 296 | .xlate = irq_domain_xlate_onecell, |
0ebfff14 BH |
297 | }; |
298 | ||
cc5d0189 | 299 | static void __init pmac_pic_probe_oldstyle(void) |
3c3f42d6 | 300 | { |
3c3f42d6 | 301 | int i; |
cc5d0189 BH |
302 | struct device_node *master = NULL; |
303 | struct device_node *slave = NULL; | |
304 | u8 __iomem *addr; | |
305 | struct resource r; | |
14cf11af | 306 | |
cc5d0189 | 307 | /* Set our get_irq function */ |
0ebfff14 | 308 | ppc_md.get_irq = pmac_pic_get_irq; |
14cf11af | 309 | |
cc5d0189 BH |
310 | /* |
311 | * Find the interrupt controller type & node | |
14cf11af | 312 | */ |
cc5d0189 BH |
313 | |
314 | if ((master = of_find_node_by_name(NULL, "gc")) != NULL) { | |
315 | max_irqs = max_real_irqs = 32; | |
cc5d0189 BH |
316 | } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) { |
317 | max_irqs = max_real_irqs = 32; | |
14cf11af | 318 | /* We might have a second cascaded ohare */ |
cc5d0189 | 319 | slave = of_find_node_by_name(NULL, "pci106b,7"); |
8e609d5e | 320 | if (slave) |
cc5d0189 | 321 | max_irqs = 64; |
cc5d0189 BH |
322 | } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) { |
323 | max_irqs = max_real_irqs = 64; | |
cc5d0189 | 324 | |
14cf11af | 325 | /* We might have a second cascaded heathrow */ |
8f910fd0 GU |
326 | |
327 | /* Compensate for of_node_put() in of_find_node_by_name() */ | |
328 | of_node_get(master); | |
cc5d0189 BH |
329 | slave = of_find_node_by_name(master, "mac-io"); |
330 | ||
331 | /* Check ordering of master & slave */ | |
55b61fec | 332 | if (of_device_is_compatible(master, "gatwick")) { |
cc5d0189 BH |
333 | struct device_node *tmp; |
334 | BUG_ON(slave == NULL); | |
335 | tmp = master; | |
336 | master = slave; | |
337 | slave = tmp; | |
338 | } | |
14cf11af | 339 | |
cc5d0189 | 340 | /* We found a slave */ |
8e609d5e | 341 | if (slave) |
14cf11af | 342 | max_irqs = 128; |
14cf11af | 343 | } |
cc5d0189 BH |
344 | BUG_ON(master == NULL); |
345 | ||
0ebfff14 BH |
346 | /* |
347 | * Allocate an irq host | |
348 | */ | |
a8db8cf0 GL |
349 | pmac_pic_host = irq_domain_add_linear(master, max_irqs, |
350 | &pmac_pic_host_ops, NULL); | |
0ebfff14 BH |
351 | BUG_ON(pmac_pic_host == NULL); |
352 | irq_set_default_host(pmac_pic_host); | |
14cf11af | 353 | |
cc5d0189 BH |
354 | /* Get addresses of first controller if we have a node for it */ |
355 | BUG_ON(of_address_to_resource(master, 0, &r)); | |
356 | ||
357 | /* Map interrupts of primary controller */ | |
358 | addr = (u8 __iomem *) ioremap(r.start, 0x40); | |
359 | i = 0; | |
360 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
361 | (addr + 0x20); | |
362 | if (max_real_irqs > 32) | |
363 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
364 | (addr + 0x10); | |
365 | of_node_put(master); | |
366 | ||
b7c670d6 RH |
367 | printk(KERN_INFO "irq: Found primary Apple PIC %pOF for %d irqs\n", |
368 | master, max_real_irqs); | |
cc5d0189 BH |
369 | |
370 | /* Map interrupts of cascaded controller */ | |
371 | if (slave && !of_address_to_resource(slave, 0, &r)) { | |
372 | addr = (u8 __iomem *)ioremap(r.start, 0x40); | |
373 | pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) | |
374 | (addr + 0x20); | |
375 | if (max_irqs > 64) | |
376 | pmac_irq_hw[i++] = | |
377 | (volatile struct pmac_irq_hw __iomem *) | |
378 | (addr + 0x10); | |
0ebfff14 | 379 | pmac_irq_cascade = irq_of_parse_and_map(slave, 0); |
cc5d0189 | 380 | |
b7c670d6 RH |
381 | printk(KERN_INFO "irq: Found slave Apple PIC %pOF for %d irqs" |
382 | " cascade: %d\n", slave, | |
b9e5b4e6 | 383 | max_irqs - max_real_irqs, pmac_irq_cascade); |
14cf11af | 384 | } |
cc5d0189 | 385 | of_node_put(slave); |
14cf11af | 386 | |
b9e5b4e6 | 387 | /* Disable all interrupts in all controllers */ |
14cf11af PM |
388 | for (i = 0; i * 32 < max_irqs; ++i) |
389 | out_le32(&pmac_irq_hw[i]->enable, 0); | |
cc5d0189 | 390 | |
b9e5b4e6 | 391 | /* Hookup cascade irq */ |
ef24ba70 | 392 | if (slave && pmac_irq_cascade) |
b9e5b4e6 | 393 | setup_irq(pmac_irq_cascade, &gatwick_cascade_action); |
14cf11af | 394 | |
cc5d0189 | 395 | printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs); |
14cf11af | 396 | #ifdef CONFIG_XMON |
6e99e458 | 397 | setup_irq(irq_create_mapping(NULL, 20), &xmon_action); |
cc5d0189 BH |
398 | #endif |
399 | } | |
b83da291 | 400 | |
0c02c800 | 401 | int of_irq_parse_oldworld(struct device_node *device, int index, |
530210c7 | 402 | struct of_phandle_args *out_irq) |
b83da291 GL |
403 | { |
404 | const u32 *ints = NULL; | |
405 | int intlen; | |
406 | ||
407 | /* | |
408 | * Old machines just have a list of interrupt numbers | |
409 | * and no interrupt-controller nodes. We also have dodgy | |
410 | * cases where the APPL,interrupts property is completely | |
411 | * missing behind pci-pci bridges and we have to get it | |
412 | * from the parent (the bridge itself, as apple just wired | |
413 | * everything together on these) | |
414 | */ | |
415 | while (device) { | |
416 | ints = of_get_property(device, "AAPL,interrupts", &intlen); | |
417 | if (ints != NULL) | |
418 | break; | |
419 | device = device->parent; | |
e5480bdc | 420 | if (!of_node_is_type(device, "pci")) |
b83da291 GL |
421 | break; |
422 | } | |
423 | if (ints == NULL) | |
424 | return -EINVAL; | |
425 | intlen /= sizeof(u32); | |
426 | ||
427 | if (index >= intlen) | |
428 | return -EINVAL; | |
429 | ||
530210c7 GL |
430 | out_irq->np = NULL; |
431 | out_irq->args[0] = ints[index]; | |
432 | out_irq->args_count = 1; | |
b83da291 GL |
433 | |
434 | return 0; | |
435 | } | |
cc5d0189 BH |
436 | #endif /* CONFIG_PPC32 */ |
437 | ||
cc5d0189 BH |
438 | static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) |
439 | { | |
440 | #if defined(CONFIG_XMON) && defined(CONFIG_PPC32) | |
441 | struct device_node* pswitch; | |
442 | int nmi_irq; | |
443 | ||
444 | pswitch = of_find_node_by_name(NULL, "programmer-switch"); | |
0ebfff14 BH |
445 | if (pswitch) { |
446 | nmi_irq = irq_of_parse_and_map(pswitch, 0); | |
ef24ba70 | 447 | if (nmi_irq) { |
0ebfff14 BH |
448 | mpic_irq_set_priority(nmi_irq, 9); |
449 | setup_irq(nmi_irq, &xmon_action); | |
450 | } | |
451 | of_node_put(pswitch); | |
cc5d0189 | 452 | } |
cc5d0189 BH |
453 | #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */ |
454 | } | |
455 | ||
1beb6a7d BH |
456 | static struct mpic * __init pmac_setup_one_mpic(struct device_node *np, |
457 | int master) | |
458 | { | |
1beb6a7d | 459 | const char *name = master ? " MPIC 1 " : " MPIC 2 "; |
1beb6a7d | 460 | struct mpic *mpic; |
be8bec56 | 461 | unsigned int flags = master ? 0 : MPIC_SECONDARY; |
1beb6a7d BH |
462 | |
463 | pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0); | |
464 | ||
e2eb6392 | 465 | if (of_get_property(np, "big-endian", NULL)) |
1beb6a7d BH |
466 | flags |= MPIC_BIG_ENDIAN; |
467 | ||
468 | /* Primary Big Endian means HT interrupts. This is quite dodgy | |
469 | * but works until I find a better way | |
470 | */ | |
471 | if (master && (flags & MPIC_BIG_ENDIAN)) | |
6cfef5b2 | 472 | flags |= MPIC_U3_HT_IRQS; |
1beb6a7d | 473 | |
8bf41568 | 474 | mpic = mpic_alloc(np, 0, flags, 0, 0, name); |
1beb6a7d BH |
475 | if (mpic == NULL) |
476 | return NULL; | |
477 | ||
478 | mpic_init(mpic); | |
479 | ||
480 | return mpic; | |
481 | } | |
482 | ||
cc5d0189 BH |
483 | static int __init pmac_pic_probe_mpic(void) |
484 | { | |
485 | struct mpic *mpic1, *mpic2; | |
486 | struct device_node *np, *master = NULL, *slave = NULL; | |
cc5d0189 BH |
487 | |
488 | /* We can have up to 2 MPICs cascaded */ | |
9625e69a | 489 | for_each_node_by_type(np, "open-pic") { |
cc5d0189 | 490 | if (master == NULL && |
e2eb6392 | 491 | of_get_property(np, "interrupts", NULL) == NULL) |
cc5d0189 BH |
492 | master = of_node_get(np); |
493 | else if (slave == NULL) | |
494 | slave = of_node_get(np); | |
9625e69a DT |
495 | if (master && slave) { |
496 | of_node_put(np); | |
cc5d0189 | 497 | break; |
9625e69a | 498 | } |
cc5d0189 BH |
499 | } |
500 | ||
501 | /* Check for bogus setups */ | |
502 | if (master == NULL && slave != NULL) { | |
503 | master = slave; | |
504 | slave = NULL; | |
505 | } | |
506 | ||
507 | /* Not found, default to good old pmac pic */ | |
508 | if (master == NULL) | |
509 | return -ENODEV; | |
510 | ||
511 | /* Set master handler */ | |
512 | ppc_md.get_irq = mpic_get_irq; | |
513 | ||
514 | /* Setup master */ | |
1beb6a7d | 515 | mpic1 = pmac_setup_one_mpic(master, 1); |
cc5d0189 | 516 | BUG_ON(mpic1 == NULL); |
cc5d0189 BH |
517 | |
518 | /* Install NMI if any */ | |
519 | pmac_pic_setup_mpic_nmi(mpic1); | |
520 | ||
521 | of_node_put(master); | |
522 | ||
09dc34a9 KM |
523 | /* Set up a cascaded controller, if present */ |
524 | if (slave) { | |
525 | mpic2 = pmac_setup_one_mpic(slave, 0); | |
526 | if (mpic2 == NULL) | |
527 | printk(KERN_ERR "Failed to setup slave MPIC\n"); | |
1beb6a7d | 528 | of_node_put(slave); |
cc5d0189 | 529 | } |
cc5d0189 | 530 | |
cc5d0189 BH |
531 | return 0; |
532 | } | |
533 | ||
534 | ||
535 | void __init pmac_pic_init(void) | |
536 | { | |
0ebfff14 | 537 | /* We configure the OF parsing based on our oldworld vs. newworld |
48fc7f7e | 538 | * platform type and whether we were booted by BootX. |
0ebfff14 BH |
539 | */ |
540 | #ifdef CONFIG_PPC32 | |
541 | if (!pmac_newworld) | |
b83da291 | 542 | of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC; |
e2eb6392 | 543 | if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL) |
b83da291 | 544 | of_irq_workarounds |= OF_IMAP_NO_PHANDLE; |
0ebfff14 | 545 | |
b83da291 GL |
546 | /* If we don't have phandles on a newworld, then try to locate a |
547 | * default interrupt controller (happens when booting with BootX). | |
548 | * We do a first match here, hopefully, that only ever happens on | |
549 | * machines with one controller. | |
550 | */ | |
551 | if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) { | |
552 | struct device_node *np; | |
553 | ||
554 | for_each_node_with_property(np, "interrupt-controller") { | |
555 | /* Skip /chosen/interrupt-controller */ | |
2c8e65b5 | 556 | if (of_node_name_eq(np, "chosen")) |
b83da291 GL |
557 | continue; |
558 | /* It seems like at least one person wants | |
559 | * to use BootX on a machine with an AppleKiwi | |
560 | * controller which happens to pretend to be an | |
561 | * interrupt controller too. */ | |
2c8e65b5 | 562 | if (of_node_name_eq(np, "AppleKiwi")) |
b83da291 GL |
563 | continue; |
564 | /* I think we found one ! */ | |
565 | of_irq_dflt_pic = np; | |
566 | break; | |
567 | } | |
568 | } | |
569 | #endif /* CONFIG_PPC32 */ | |
6e99e458 | 570 | |
cc5d0189 BH |
571 | /* We first try to detect Apple's new Core99 chipset, since mac-io |
572 | * is quite different on those machines and contains an IBM MPIC2. | |
573 | */ | |
574 | if (pmac_pic_probe_mpic() == 0) | |
575 | return; | |
576 | ||
577 | #ifdef CONFIG_PPC32 | |
578 | pmac_pic_probe_oldstyle(); | |
579 | #endif | |
14cf11af PM |
580 | } |
581 | ||
a0005034 | 582 | #if defined(CONFIG_PM) && defined(CONFIG_PPC32) |
14cf11af PM |
583 | /* |
584 | * These procedures are used in implementing sleep on the powerbooks. | |
585 | * sleep_save_intrs() saves the states of all interrupt enables | |
586 | * and disables all interrupts except for the nominated one. | |
587 | * sleep_restore_intrs() restores the states of all interrupt enables. | |
588 | */ | |
589 | unsigned long sleep_save_mask[2]; | |
590 | ||
591 | /* This used to be passed by the PMU driver but that link got | |
592 | * broken with the new driver model. We use this tweak for now... | |
0ebfff14 | 593 | * We really want to do things differently though... |
14cf11af PM |
594 | */ |
595 | static int pmacpic_find_viaint(void) | |
596 | { | |
597 | int viaint = -1; | |
598 | ||
599 | #ifdef CONFIG_ADB_PMU | |
600 | struct device_node *np; | |
601 | ||
602 | if (pmu_get_model() != PMU_OHARE_BASED) | |
603 | goto not_found; | |
604 | np = of_find_node_by_name(NULL, "via-pmu"); | |
605 | if (np == NULL) | |
606 | goto not_found; | |
d258e64e | 607 | viaint = irq_of_parse_and_map(np, 0); |
2aaf0a19 | 608 | of_node_put(np); |
14cf11af PM |
609 | |
610 | not_found: | |
98cddbfb | 611 | #endif /* CONFIG_ADB_PMU */ |
14cf11af PM |
612 | return viaint; |
613 | } | |
614 | ||
f5a592f7 | 615 | static int pmacpic_suspend(void) |
14cf11af PM |
616 | { |
617 | int viaint = pmacpic_find_viaint(); | |
618 | ||
619 | sleep_save_mask[0] = ppc_cached_irq_mask[0]; | |
620 | sleep_save_mask[1] = ppc_cached_irq_mask[1]; | |
621 | ppc_cached_irq_mask[0] = 0; | |
622 | ppc_cached_irq_mask[1] = 0; | |
623 | if (viaint > 0) | |
624 | set_bit(viaint, ppc_cached_irq_mask); | |
625 | out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]); | |
626 | if (max_real_irqs > 32) | |
627 | out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]); | |
628 | (void)in_le32(&pmac_irq_hw[0]->event); | |
629 | /* make sure mask gets to controller before we return to caller */ | |
630 | mb(); | |
631 | (void)in_le32(&pmac_irq_hw[0]->enable); | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
f5a592f7 | 636 | static void pmacpic_resume(void) |
14cf11af PM |
637 | { |
638 | int i; | |
639 | ||
640 | out_le32(&pmac_irq_hw[0]->enable, 0); | |
641 | if (max_real_irqs > 32) | |
642 | out_le32(&pmac_irq_hw[1]->enable, 0); | |
643 | mb(); | |
644 | for (i = 0; i < max_real_irqs; ++i) | |
645 | if (test_bit(i, sleep_save_mask)) | |
d8c94aca | 646 | pmac_unmask_irq(irq_get_irq_data(i)); |
14cf11af PM |
647 | } |
648 | ||
f5a592f7 RW |
649 | static struct syscore_ops pmacpic_syscore_ops = { |
650 | .suspend = pmacpic_suspend, | |
651 | .resume = pmacpic_resume, | |
14cf11af PM |
652 | }; |
653 | ||
f5a592f7 | 654 | static int __init init_pmacpic_syscore(void) |
14cf11af | 655 | { |
339dedf7 BH |
656 | if (pmac_irq_hw[0]) |
657 | register_syscore_ops(&pmacpic_syscore_ops); | |
14cf11af PM |
658 | return 0; |
659 | } | |
14cf11af | 660 | |
f5a592f7 RW |
661 | machine_subsys_initcall(powermac, init_pmacpic_syscore); |
662 | ||
663 | #endif /* CONFIG_PM && CONFIG_PPC32 */ |