Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
14cf11af PM |
2 | /* |
3 | * Support for PCI bridges found on Power Macintoshes. | |
14cf11af | 4 | * |
1beb6a7d | 5 | * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org) |
14cf11af | 6 | * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) |
14cf11af PM |
7 | */ |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/pci.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/string.h> | |
13 | #include <linux/init.h> | |
6e99e458 | 14 | #include <linux/irq.h> |
98d9f30c | 15 | #include <linux/of_pci.h> |
14cf11af PM |
16 | |
17 | #include <asm/sections.h> | |
18 | #include <asm/io.h> | |
19 | #include <asm/prom.h> | |
20 | #include <asm/pci-bridge.h> | |
21 | #include <asm/machdep.h> | |
22 | #include <asm/pmac_feature.h> | |
830825d6 | 23 | #include <asm/grackle.h> |
3c3f42d6 | 24 | #include <asm/ppc-pci.h> |
14cf11af | 25 | |
e63f26d3 DA |
26 | #include "pmac.h" |
27 | ||
14cf11af PM |
28 | #undef DEBUG |
29 | ||
30 | #ifdef DEBUG | |
31 | #define DBG(x...) printk(x) | |
32 | #else | |
33 | #define DBG(x...) | |
34 | #endif | |
35 | ||
14cf11af PM |
36 | /* XXX Could be per-controller, but I don't think we risk anything by |
37 | * assuming we won't have both UniNorth and Bandit */ | |
38 | static int has_uninorth; | |
35499c01 | 39 | #ifdef CONFIG_PPC64 |
14cf11af | 40 | static struct pci_controller *u3_agp; |
0ebfff14 BH |
41 | #else |
42 | static int has_second_ohare; | |
35499c01 | 43 | #endif /* CONFIG_PPC64 */ |
14cf11af | 44 | |
14cf11af PM |
45 | extern int pcibios_assign_bus_offset; |
46 | ||
47 | struct device_node *k2_skiplist[2]; | |
48 | ||
49 | /* | |
50 | * Magic constants for enabling cache coherency in the bandit/PSX bridge. | |
51 | */ | |
52 | #define BANDIT_DEVID_2 8 | |
53 | #define BANDIT_REVID 3 | |
54 | ||
55 | #define BANDIT_DEVNUM 11 | |
56 | #define BANDIT_MAGIC 0x50 | |
57 | #define BANDIT_COHERENT 0x40 | |
58 | ||
59 | static int __init fixup_one_level_bus_range(struct device_node *node, int higher) | |
60 | { | |
d8731527 | 61 | for (; node; node = node->sibling) { |
018a3d1d JK |
62 | const int * bus_range; |
63 | const unsigned int *class_code; | |
14cf11af PM |
64 | int len; |
65 | ||
66 | /* For PCI<->PCI bridges or CardBus bridges, we go down */ | |
e2eb6392 | 67 | class_code = of_get_property(node, "class-code", NULL); |
14cf11af PM |
68 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && |
69 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) | |
70 | continue; | |
e2eb6392 | 71 | bus_range = of_get_property(node, "bus-range", &len); |
14cf11af PM |
72 | if (bus_range != NULL && len > 2 * sizeof(int)) { |
73 | if (bus_range[1] > higher) | |
74 | higher = bus_range[1]; | |
75 | } | |
76 | higher = fixup_one_level_bus_range(node->child, higher); | |
77 | } | |
78 | return higher; | |
79 | } | |
80 | ||
81 | /* This routine fixes the "bus-range" property of all bridges in the | |
82 | * system since they tend to have their "last" member wrong on macs | |
83 | * | |
84 | * Note that the bus numbers manipulated here are OF bus numbers, they | |
85 | * are not Linux bus numbers. | |
86 | */ | |
87 | static void __init fixup_bus_range(struct device_node *bridge) | |
88 | { | |
018a3d1d JK |
89 | int *bus_range, len; |
90 | struct property *prop; | |
14cf11af PM |
91 | |
92 | /* Lookup the "bus-range" property for the hose */ | |
018a3d1d JK |
93 | prop = of_find_property(bridge, "bus-range", &len); |
94 | if (prop == NULL || prop->length < 2 * sizeof(int)) | |
14cf11af | 95 | return; |
018a3d1d | 96 | |
1a38147e | 97 | bus_range = prop->value; |
14cf11af PM |
98 | bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); |
99 | } | |
100 | ||
101 | /* | |
102 | * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. | |
103 | * | |
104 | * The "Bandit" version is present in all early PCI PowerMacs, | |
105 | * and up to the first ones using Grackle. Some machines may | |
106 | * have 2 bandit controllers (2 PCI busses). | |
107 | * | |
108 | * "Chaos" is used in some "Bandit"-type machines as a bridge | |
109 | * for the separate display bus. It is accessed the same | |
110 | * way as bandit, but cannot be probed for devices. It therefore | |
111 | * has its own config access functions. | |
112 | * | |
113 | * The "UniNorth" version is present in all Core99 machines | |
114 | * (iBook, G4, new IMacs, and all the recent Apple machines). | |
115 | * It contains 3 controllers in one ASIC. | |
116 | * | |
117 | * The U3 is the bridge used on G5 machines. It contains an | |
118 | * AGP bus which is dealt with the old UniNorth access routines | |
119 | * and a HyperTransport bus which uses its own set of access | |
120 | * functions. | |
121 | */ | |
122 | ||
123 | #define MACRISC_CFA0(devfn, off) \ | |
1beb6a7d BH |
124 | ((1 << (unsigned int)PCI_SLOT(dev_fn)) \ |
125 | | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ | |
126 | | (((unsigned int)(off)) & 0xFCUL)) | |
14cf11af PM |
127 | |
128 | #define MACRISC_CFA1(bus, devfn, off) \ | |
1beb6a7d BH |
129 | ((((unsigned int)(bus)) << 16) \ |
130 | |(((unsigned int)(devfn)) << 8) \ | |
131 | |(((unsigned int)(off)) & 0xFCUL) \ | |
14cf11af PM |
132 | |1UL) |
133 | ||
b98fa508 RH |
134 | static void __iomem *macrisc_cfg_map_bus(struct pci_bus *bus, |
135 | unsigned int dev_fn, | |
136 | int offset) | |
14cf11af PM |
137 | { |
138 | unsigned int caddr; | |
b98fa508 | 139 | struct pci_controller *hose; |
14cf11af | 140 | |
b98fa508 RH |
141 | hose = pci_bus_to_host(bus); |
142 | if (hose == NULL) | |
143 | return NULL; | |
144 | ||
145 | if (bus->number == hose->first_busno) { | |
14cf11af | 146 | if (dev_fn < (11 << 3)) |
de125bf3 | 147 | return NULL; |
14cf11af PM |
148 | caddr = MACRISC_CFA0(dev_fn, offset); |
149 | } else | |
b98fa508 | 150 | caddr = MACRISC_CFA1(bus->number, dev_fn, offset); |
14cf11af PM |
151 | |
152 | /* Uninorth will return garbage if we don't read back the value ! */ | |
153 | do { | |
154 | out_le32(hose->cfg_addr, caddr); | |
155 | } while (in_le32(hose->cfg_addr) != caddr); | |
156 | ||
157 | offset &= has_uninorth ? 0x07 : 0x03; | |
de125bf3 | 158 | return hose->cfg_data + offset; |
14cf11af PM |
159 | } |
160 | ||
14cf11af PM |
161 | static struct pci_ops macrisc_pci_ops = |
162 | { | |
b98fa508 RH |
163 | .map_bus = macrisc_cfg_map_bus, |
164 | .read = pci_generic_config_read, | |
165 | .write = pci_generic_config_write, | |
14cf11af PM |
166 | }; |
167 | ||
35499c01 | 168 | #ifdef CONFIG_PPC32 |
14cf11af | 169 | /* |
3c3f42d6 | 170 | * Verify that a specific (bus, dev_fn) exists on chaos |
14cf11af | 171 | */ |
b98fa508 RH |
172 | static void __iomem *chaos_map_bus(struct pci_bus *bus, unsigned int devfn, |
173 | int offset) | |
14cf11af PM |
174 | { |
175 | struct device_node *np; | |
018a3d1d | 176 | const u32 *vendor, *device; |
14cf11af | 177 | |
1beb6a7d | 178 | if (offset >= 0x100) |
b98fa508 | 179 | return NULL; |
98d9f30c | 180 | np = of_pci_find_child_device(bus->dev.of_node, devfn); |
14cf11af | 181 | if (np == NULL) |
b98fa508 | 182 | return NULL; |
14cf11af | 183 | |
e2eb6392 SR |
184 | vendor = of_get_property(np, "vendor-id", NULL); |
185 | device = of_get_property(np, "device-id", NULL); | |
14cf11af | 186 | if (vendor == NULL || device == NULL) |
b98fa508 | 187 | return NULL; |
14cf11af PM |
188 | |
189 | if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) | |
190 | && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) | |
b98fa508 | 191 | return NULL; |
14cf11af | 192 | |
b98fa508 | 193 | return macrisc_cfg_map_bus(bus, devfn, offset); |
14cf11af PM |
194 | } |
195 | ||
196 | static struct pci_ops chaos_pci_ops = | |
197 | { | |
b98fa508 RH |
198 | .map_bus = chaos_map_bus, |
199 | .read = pci_generic_config_read, | |
200 | .write = pci_generic_config_write, | |
14cf11af PM |
201 | }; |
202 | ||
35499c01 | 203 | static void __init setup_chaos(struct pci_controller *hose, |
cc5d0189 | 204 | struct resource *addr) |
35499c01 PM |
205 | { |
206 | /* assume a `chaos' bridge */ | |
207 | hose->ops = &chaos_pci_ops; | |
cc5d0189 BH |
208 | hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); |
209 | hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); | |
35499c01 | 210 | } |
35499c01 PM |
211 | #endif /* CONFIG_PPC32 */ |
212 | ||
213 | #ifdef CONFIG_PPC64 | |
14cf11af PM |
214 | /* |
215 | * These versions of U3 HyperTransport config space access ops do not | |
216 | * implement self-view of the HT host yet | |
217 | */ | |
218 | ||
219 | /* | |
220 | * This function deals with some "special cases" devices. | |
221 | * | |
222 | * 0 -> No special case | |
25985edc | 223 | * 1 -> Skip the device but act as if the access was successful |
14cf11af PM |
224 | * (return 0xff's on reads, eventually, cache config space |
225 | * accesses in a later version) | |
af901ca1 | 226 | * -1 -> Hide the device (unsuccessful access) |
14cf11af PM |
227 | */ |
228 | static int u3_ht_skip_device(struct pci_controller *hose, | |
229 | struct pci_bus *bus, unsigned int devfn) | |
230 | { | |
231 | struct device_node *busdn, *dn; | |
232 | int i; | |
233 | ||
234 | /* We only allow config cycles to devices that are in OF device-tree | |
235 | * as we are apparently having some weird things going on with some | |
444532d4 BH |
236 | * revs of K2 on recent G5s, except for the host bridge itself, which |
237 | * is missing from the tree but we know we can probe. | |
14cf11af PM |
238 | */ |
239 | if (bus->self) | |
240 | busdn = pci_device_to_OF_node(bus->self); | |
444532d4 BH |
241 | else if (devfn == 0) |
242 | return 0; | |
14cf11af | 243 | else |
44ef3390 | 244 | busdn = hose->dn; |
14cf11af | 245 | for (dn = busdn->child; dn; dn = dn->sibling) |
e07102db | 246 | if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn) |
14cf11af PM |
247 | break; |
248 | if (dn == NULL) | |
249 | return -1; | |
250 | ||
251 | /* | |
252 | * When a device in K2 is powered down, we die on config | |
253 | * cycle accesses. Fix that here. | |
254 | */ | |
255 | for (i=0; i<2; i++) | |
256 | if (k2_skiplist[i] == dn) | |
257 | return 1; | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
262 | #define U3_HT_CFA0(devfn, off) \ | |
1beb6a7d | 263 | ((((unsigned int)devfn) << 8) | offset) |
14cf11af PM |
264 | #define U3_HT_CFA1(bus, devfn, off) \ |
265 | (U3_HT_CFA0(devfn, off) \ | |
1beb6a7d | 266 | + (((unsigned int)bus) << 16) \ |
14cf11af PM |
267 | + 0x01000000UL) |
268 | ||
444532d4 BH |
269 | static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus, |
270 | u8 devfn, u8 offset, int *swap) | |
14cf11af | 271 | { |
444532d4 | 272 | *swap = 1; |
14cf11af | 273 | if (bus == hose->first_busno) { |
444532d4 BH |
274 | if (devfn != 0) |
275 | return hose->cfg_data + U3_HT_CFA0(devfn, offset); | |
276 | *swap = 0; | |
277 | return ((void __iomem *)hose->cfg_addr) + (offset << 2); | |
14cf11af | 278 | } else |
de125bf3 | 279 | return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); |
14cf11af PM |
280 | } |
281 | ||
282 | static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, | |
283 | int offset, int len, u32 *val) | |
284 | { | |
3c3f42d6 | 285 | struct pci_controller *hose; |
444532d4 BH |
286 | void __iomem *addr; |
287 | int swap; | |
14cf11af | 288 | |
3c3f42d6 PM |
289 | hose = pci_bus_to_host(bus); |
290 | if (hose == NULL) | |
14cf11af | 291 | return PCIBIOS_DEVICE_NOT_FOUND; |
1beb6a7d BH |
292 | if (offset >= 0x100) |
293 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
444532d4 | 294 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); |
14cf11af PM |
295 | if (!addr) |
296 | return PCIBIOS_DEVICE_NOT_FOUND; | |
297 | ||
298 | switch (u3_ht_skip_device(hose, bus, devfn)) { | |
299 | case 0: | |
300 | break; | |
301 | case 1: | |
3c3f42d6 PM |
302 | switch (len) { |
303 | case 1: | |
304 | *val = 0xff; break; | |
305 | case 2: | |
306 | *val = 0xffff; break; | |
307 | default: | |
308 | *val = 0xfffffffful; break; | |
309 | } | |
310 | return PCIBIOS_SUCCESSFUL; | |
14cf11af PM |
311 | default: |
312 | return PCIBIOS_DEVICE_NOT_FOUND; | |
3c3f42d6 PM |
313 | } |
314 | ||
14cf11af PM |
315 | /* |
316 | * Note: the caller has already checked that offset is | |
317 | * suitably aligned and that len is 1, 2 or 4. | |
318 | */ | |
319 | switch (len) { | |
320 | case 1: | |
de125bf3 | 321 | *val = in_8(addr); |
14cf11af PM |
322 | break; |
323 | case 2: | |
444532d4 | 324 | *val = swap ? in_le16(addr) : in_be16(addr); |
14cf11af PM |
325 | break; |
326 | default: | |
444532d4 | 327 | *val = swap ? in_le32(addr) : in_be32(addr); |
14cf11af PM |
328 | break; |
329 | } | |
330 | return PCIBIOS_SUCCESSFUL; | |
331 | } | |
332 | ||
333 | static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, | |
334 | int offset, int len, u32 val) | |
335 | { | |
3c3f42d6 | 336 | struct pci_controller *hose; |
444532d4 BH |
337 | void __iomem *addr; |
338 | int swap; | |
14cf11af | 339 | |
3c3f42d6 PM |
340 | hose = pci_bus_to_host(bus); |
341 | if (hose == NULL) | |
14cf11af | 342 | return PCIBIOS_DEVICE_NOT_FOUND; |
1beb6a7d BH |
343 | if (offset >= 0x100) |
344 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
444532d4 | 345 | addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); |
14cf11af PM |
346 | if (!addr) |
347 | return PCIBIOS_DEVICE_NOT_FOUND; | |
348 | ||
349 | switch (u3_ht_skip_device(hose, bus, devfn)) { | |
350 | case 0: | |
351 | break; | |
352 | case 1: | |
353 | return PCIBIOS_SUCCESSFUL; | |
354 | default: | |
355 | return PCIBIOS_DEVICE_NOT_FOUND; | |
356 | } | |
357 | ||
358 | /* | |
359 | * Note: the caller has already checked that offset is | |
360 | * suitably aligned and that len is 1, 2 or 4. | |
361 | */ | |
362 | switch (len) { | |
363 | case 1: | |
de125bf3 | 364 | out_8(addr, val); |
14cf11af PM |
365 | break; |
366 | case 2: | |
444532d4 | 367 | swap ? out_le16(addr, val) : out_be16(addr, val); |
14cf11af PM |
368 | break; |
369 | default: | |
444532d4 | 370 | swap ? out_le32(addr, val) : out_be32(addr, val); |
14cf11af PM |
371 | break; |
372 | } | |
373 | return PCIBIOS_SUCCESSFUL; | |
374 | } | |
375 | ||
376 | static struct pci_ops u3_ht_pci_ops = | |
377 | { | |
3fac10e7 NL |
378 | .read = u3_ht_read_config, |
379 | .write = u3_ht_write_config, | |
14cf11af | 380 | }; |
1beb6a7d BH |
381 | |
382 | #define U4_PCIE_CFA0(devfn, off) \ | |
383 | ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \ | |
384 | | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ | |
385 | | ((((unsigned int)(off)) >> 8) << 28) \ | |
386 | | (((unsigned int)(off)) & 0xfcU)) | |
387 | ||
388 | #define U4_PCIE_CFA1(bus, devfn, off) \ | |
389 | ((((unsigned int)(bus)) << 16) \ | |
390 | |(((unsigned int)(devfn)) << 8) \ | |
391 | | ((((unsigned int)(off)) >> 8) << 28) \ | |
392 | |(((unsigned int)(off)) & 0xfcU) \ | |
393 | |1UL) | |
394 | ||
b98fa508 RH |
395 | static void __iomem *u4_pcie_cfg_map_bus(struct pci_bus *bus, |
396 | unsigned int dev_fn, | |
397 | int offset) | |
1beb6a7d | 398 | { |
b98fa508 | 399 | struct pci_controller *hose; |
1beb6a7d BH |
400 | unsigned int caddr; |
401 | ||
b98fa508 RH |
402 | if (offset >= 0x1000) |
403 | return NULL; | |
404 | ||
405 | hose = pci_bus_to_host(bus); | |
406 | if (!hose) | |
407 | return NULL; | |
408 | ||
409 | if (bus->number == hose->first_busno) { | |
1beb6a7d BH |
410 | caddr = U4_PCIE_CFA0(dev_fn, offset); |
411 | } else | |
b98fa508 | 412 | caddr = U4_PCIE_CFA1(bus->number, dev_fn, offset); |
1beb6a7d BH |
413 | |
414 | /* Uninorth will return garbage if we don't read back the value ! */ | |
415 | do { | |
416 | out_le32(hose->cfg_addr, caddr); | |
417 | } while (in_le32(hose->cfg_addr) != caddr); | |
418 | ||
419 | offset &= 0x03; | |
de125bf3 | 420 | return hose->cfg_data + offset; |
1beb6a7d BH |
421 | } |
422 | ||
1beb6a7d BH |
423 | static struct pci_ops u4_pcie_pci_ops = |
424 | { | |
b98fa508 RH |
425 | .map_bus = u4_pcie_cfg_map_bus, |
426 | .read = pci_generic_config_read, | |
427 | .write = pci_generic_config_write, | |
1beb6a7d BH |
428 | }; |
429 | ||
cad5cef6 | 430 | static void pmac_pci_fixup_u4_of_node(struct pci_dev *dev) |
16fa42af BH |
431 | { |
432 | /* Apple's device-tree "hides" the root complex virtual P2P bridge | |
433 | * on U4. However, Linux sees it, causing the PCI <-> OF matching | |
434 | * code to fail to properly match devices below it. This works around | |
435 | * it by setting the node of the bridge to point to the PHB node, | |
436 | * which is not entirely correct but fixes the matching code and | |
437 | * doesn't break anything else. It's also the simplest possible fix. | |
438 | */ | |
439 | if (dev->dev.of_node == NULL) | |
440 | dev->dev.of_node = pcibios_get_phb_of_node(dev->bus); | |
441 | } | |
442 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node); | |
443 | ||
35499c01 | 444 | #endif /* CONFIG_PPC64 */ |
14cf11af | 445 | |
35499c01 | 446 | #ifdef CONFIG_PPC32 |
14cf11af PM |
447 | /* |
448 | * For a bandit bridge, turn on cache coherency if necessary. | |
449 | * N.B. we could clean this up using the hose ops directly. | |
450 | */ | |
3c3f42d6 | 451 | static void __init init_bandit(struct pci_controller *bp) |
14cf11af PM |
452 | { |
453 | unsigned int vendev, magic; | |
454 | int rev; | |
455 | ||
456 | /* read the word at offset 0 in config space for device 11 */ | |
457 | out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); | |
458 | udelay(2); | |
459 | vendev = in_le32(bp->cfg_data); | |
460 | if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + | |
461 | PCI_VENDOR_ID_APPLE) { | |
462 | /* read the revision id */ | |
463 | out_le32(bp->cfg_addr, | |
464 | (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); | |
465 | udelay(2); | |
466 | rev = in_8(bp->cfg_data); | |
467 | if (rev != BANDIT_REVID) | |
468 | printk(KERN_WARNING | |
469 | "Unknown revision %d for bandit\n", rev); | |
470 | } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { | |
471 | printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); | |
472 | return; | |
473 | } | |
474 | ||
475 | /* read the word at offset 0x50 */ | |
476 | out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); | |
477 | udelay(2); | |
478 | magic = in_le32(bp->cfg_data); | |
479 | if ((magic & BANDIT_COHERENT) != 0) | |
480 | return; | |
481 | magic |= BANDIT_COHERENT; | |
482 | udelay(2); | |
483 | out_le32(bp->cfg_data, magic); | |
484 | printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); | |
485 | } | |
486 | ||
14cf11af PM |
487 | /* |
488 | * Tweak the PCI-PCI bridge chip on the blue & white G3s. | |
489 | */ | |
3c3f42d6 | 490 | static void __init init_p2pbridge(void) |
14cf11af PM |
491 | { |
492 | struct device_node *p2pbridge; | |
493 | struct pci_controller* hose; | |
494 | u8 bus, devfn; | |
495 | u16 val; | |
496 | ||
497 | /* XXX it would be better here to identify the specific | |
498 | PCI-PCI bridge chip we have. */ | |
30686ba6 | 499 | p2pbridge = of_find_node_by_name(NULL, "pci-bridge"); |
2c8e65b5 | 500 | if (p2pbridge == NULL || !of_node_name_eq(p2pbridge->parent, "pci")) |
30686ba6 | 501 | goto done; |
14cf11af PM |
502 | if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { |
503 | DBG("Can't find PCI infos for PCI<->PCI bridge\n"); | |
30686ba6 | 504 | goto done; |
14cf11af PM |
505 | } |
506 | /* Warning: At this point, we have not yet renumbered all busses. | |
507 | * So we must use OF walking to find out hose | |
508 | */ | |
509 | hose = pci_find_hose_for_OF_device(p2pbridge); | |
510 | if (!hose) { | |
511 | DBG("Can't find hose for PCI<->PCI bridge\n"); | |
30686ba6 | 512 | goto done; |
14cf11af PM |
513 | } |
514 | if (early_read_config_word(hose, bus, devfn, | |
515 | PCI_BRIDGE_CONTROL, &val) < 0) { | |
cc5d0189 BH |
516 | printk(KERN_ERR "init_p2pbridge: couldn't read bridge" |
517 | " control\n"); | |
30686ba6 | 518 | goto done; |
14cf11af PM |
519 | } |
520 | val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; | |
521 | early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); | |
30686ba6 SR |
522 | done: |
523 | of_node_put(p2pbridge); | |
14cf11af PM |
524 | } |
525 | ||
0ebfff14 BH |
526 | static void __init init_second_ohare(void) |
527 | { | |
528 | struct device_node *np = of_find_node_by_name(NULL, "pci106b,7"); | |
529 | unsigned char bus, devfn; | |
530 | unsigned short cmd; | |
531 | ||
532 | if (np == NULL) | |
533 | return; | |
534 | ||
535 | /* This must run before we initialize the PICs since the second | |
536 | * ohare hosts a PIC that will be accessed there. | |
537 | */ | |
538 | if (pci_device_from_OF_node(np, &bus, &devfn) == 0) { | |
539 | struct pci_controller* hose = | |
540 | pci_find_hose_for_OF_device(np); | |
541 | if (!hose) { | |
542 | printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); | |
afcb0654 | 543 | of_node_put(np); |
0ebfff14 BH |
544 | return; |
545 | } | |
546 | early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); | |
547 | cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; | |
548 | cmd &= ~PCI_COMMAND_IO; | |
549 | early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); | |
550 | } | |
551 | has_second_ohare = 1; | |
afcb0654 | 552 | of_node_put(np); |
0ebfff14 BH |
553 | } |
554 | ||
14cf11af PM |
555 | /* |
556 | * Some Apple desktop machines have a NEC PD720100A USB2 controller | |
557 | * on the motherboard. Open Firmware, on these, will disable the | |
558 | * EHCI part of it so it behaves like a pair of OHCI's. This fixup | |
559 | * code re-enables it ;) | |
560 | */ | |
3c3f42d6 | 561 | static void __init fixup_nec_usb2(void) |
14cf11af PM |
562 | { |
563 | struct device_node *nec; | |
564 | ||
ccdb8ed3 | 565 | for_each_node_by_name(nec, "usb") { |
14cf11af | 566 | struct pci_controller *hose; |
018a3d1d JK |
567 | u32 data; |
568 | const u32 *prop; | |
14cf11af | 569 | u8 bus, devfn; |
35499c01 | 570 | |
e2eb6392 | 571 | prop = of_get_property(nec, "vendor-id", NULL); |
14cf11af PM |
572 | if (prop == NULL) |
573 | continue; | |
574 | if (0x1033 != *prop) | |
575 | continue; | |
e2eb6392 | 576 | prop = of_get_property(nec, "device-id", NULL); |
14cf11af PM |
577 | if (prop == NULL) |
578 | continue; | |
579 | if (0x0035 != *prop) | |
580 | continue; | |
e2eb6392 | 581 | prop = of_get_property(nec, "reg", NULL); |
14cf11af PM |
582 | if (prop == NULL) |
583 | continue; | |
584 | devfn = (prop[0] >> 8) & 0xff; | |
585 | bus = (prop[0] >> 16) & 0xff; | |
586 | if (PCI_FUNC(devfn) != 0) | |
587 | continue; | |
588 | hose = pci_find_hose_for_OF_device(nec); | |
589 | if (!hose) | |
590 | continue; | |
591 | early_read_config_dword(hose, bus, devfn, 0xe4, &data); | |
592 | if (data & 1UL) { | |
cc5d0189 BH |
593 | printk("Found NEC PD720100A USB2 chip with disabled" |
594 | " EHCI, fixing up...\n"); | |
14cf11af PM |
595 | data &= ~1UL; |
596 | early_write_config_dword(hose, bus, devfn, 0xe4, data); | |
14cf11af PM |
597 | } |
598 | } | |
599 | } | |
600 | ||
35499c01 | 601 | static void __init setup_bandit(struct pci_controller *hose, |
cc5d0189 | 602 | struct resource *addr) |
14cf11af PM |
603 | { |
604 | hose->ops = ¯isc_pci_ops; | |
cc5d0189 BH |
605 | hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); |
606 | hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); | |
14cf11af PM |
607 | init_bandit(hose); |
608 | } | |
609 | ||
35499c01 | 610 | static int __init setup_uninorth(struct pci_controller *hose, |
cc5d0189 | 611 | struct resource *addr) |
14cf11af | 612 | { |
0e47ff1c | 613 | pci_add_flags(PCI_REASSIGN_ALL_BUS); |
35499c01 PM |
614 | has_uninorth = 1; |
615 | hose->ops = ¯isc_pci_ops; | |
cc5d0189 BH |
616 | hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); |
617 | hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); | |
35499c01 | 618 | /* We "know" that the bridge at f2000000 has the PCI slots. */ |
cc5d0189 | 619 | return addr->start == 0xf2000000; |
14cf11af | 620 | } |
cc5d0189 | 621 | #endif /* CONFIG_PPC32 */ |
14cf11af | 622 | |
35499c01 | 623 | #ifdef CONFIG_PPC64 |
14cf11af PM |
624 | static void __init setup_u3_agp(struct pci_controller* hose) |
625 | { | |
626 | /* On G5, we move AGP up to high bus number so we don't need | |
627 | * to reassign bus numbers for HT. If we ever have P2P bridges | |
35499c01 | 628 | * on AGP, we'll have to move pci_assign_all_busses to the |
14cf11af PM |
629 | * pci_controller structure so we enable it for AGP and not for |
630 | * HT childs. | |
631 | * We hard code the address because of the different size of | |
632 | * the reg address cell, we shall fix that by killing struct | |
633 | * reg_property and using some accessor functions instead | |
634 | */ | |
3c3f42d6 | 635 | hose->first_busno = 0xf0; |
14cf11af PM |
636 | hose->last_busno = 0xff; |
637 | has_uninorth = 1; | |
638 | hose->ops = ¯isc_pci_ops; | |
639 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); | |
640 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); | |
14cf11af PM |
641 | u3_agp = hose; |
642 | } | |
643 | ||
1beb6a7d BH |
644 | static void __init setup_u4_pcie(struct pci_controller* hose) |
645 | { | |
646 | /* We currently only implement the "non-atomic" config space, to | |
647 | * be optimised later. | |
648 | */ | |
649 | hose->ops = &u4_pcie_pci_ops; | |
650 | hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); | |
651 | hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); | |
652 | ||
653 | /* The bus contains a bridge from root -> device, we need to | |
654 | * make it visible on bus 0 so that we pick the right type | |
655 | * of config cycles. If we didn't, we would have to force all | |
656 | * config cycles to be type 1. So we override the "bus-range" | |
657 | * property here | |
658 | */ | |
659 | hose->first_busno = 0x00; | |
660 | hose->last_busno = 0xff; | |
d0264ce7 BH |
661 | } |
662 | ||
663 | static void __init parse_region_decode(struct pci_controller *hose, | |
664 | u32 decode) | |
665 | { | |
666 | unsigned long base, end, next = -1; | |
667 | int i, cur = -1; | |
668 | ||
669 | /* Iterate through all bits. We ignore the last bit as this region is | |
670 | * reserved for the ROM among other niceties | |
671 | */ | |
672 | for (i = 0; i < 31; i++) { | |
673 | if ((decode & (0x80000000 >> i)) == 0) | |
674 | continue; | |
675 | if (i < 16) { | |
676 | base = 0xf0000000 | (((u32)i) << 24); | |
677 | end = base + 0x00ffffff; | |
678 | } else { | |
679 | base = ((u32)i-16) << 28; | |
680 | end = base + 0x0fffffff; | |
681 | } | |
682 | if (base != next) { | |
683 | if (++cur >= 3) { | |
684 | printk(KERN_WARNING "PCI: Too many ranges !\n"); | |
685 | break; | |
686 | } | |
687 | hose->mem_resources[cur].flags = IORESOURCE_MEM; | |
688 | hose->mem_resources[cur].name = hose->dn->full_name; | |
689 | hose->mem_resources[cur].start = base; | |
690 | hose->mem_resources[cur].end = end; | |
3fd47f06 | 691 | hose->mem_offset[cur] = 0; |
d0264ce7 BH |
692 | DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end); |
693 | } else { | |
694 | DBG(" : -0x%08lx\n", end); | |
695 | hose->mem_resources[cur].end = end; | |
696 | } | |
697 | next = end + 1; | |
698 | } | |
1beb6a7d BH |
699 | } |
700 | ||
14cf11af PM |
701 | static void __init setup_u3_ht(struct pci_controller* hose) |
702 | { | |
44ef3390 | 703 | struct device_node *np = hose->dn; |
444532d4 | 704 | struct resource cfg_res, self_res; |
d0264ce7 | 705 | u32 decode; |
1beb6a7d | 706 | |
14cf11af PM |
707 | hose->ops = &u3_ht_pci_ops; |
708 | ||
444532d4 BH |
709 | /* Get base addresses from OF tree |
710 | */ | |
711 | if (of_address_to_resource(np, 0, &cfg_res) || | |
712 | of_address_to_resource(np, 1, &self_res)) { | |
713 | printk(KERN_ERR "PCI: Failed to get U3/U4 HT resources !\n"); | |
714 | return; | |
715 | } | |
716 | ||
717 | /* Map external cfg space access into cfg_data and self registers | |
718 | * into cfg_addr | |
14cf11af | 719 | */ |
444532d4 | 720 | hose->cfg_data = ioremap(cfg_res.start, 0x02000000); |
28f65c11 | 721 | hose->cfg_addr = ioremap(self_res.start, resource_size(&self_res)); |
14cf11af PM |
722 | |
723 | /* | |
d0264ce7 BH |
724 | * /ht node doesn't expose a "ranges" property, we read the register |
725 | * that controls the decoding logic and use that for memory regions. | |
726 | * The IO region is hard coded since it is fixed in HW as well. | |
14cf11af PM |
727 | */ |
728 | hose->io_base_phys = 0xf4000000; | |
35499c01 | 729 | hose->pci_io_size = 0x00400000; |
14cf11af PM |
730 | hose->io_resource.name = np->full_name; |
731 | hose->io_resource.start = 0; | |
732 | hose->io_resource.end = 0x003fffff; | |
733 | hose->io_resource.flags = IORESOURCE_IO; | |
14cf11af PM |
734 | hose->first_busno = 0; |
735 | hose->last_busno = 0xef; | |
14cf11af | 736 | |
d0264ce7 BH |
737 | /* Note: fix offset when cfg_addr becomes a void * */ |
738 | decode = in_be32(hose->cfg_addr + 0x80); | |
739 | ||
740 | DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode); | |
741 | ||
742 | /* NOTE: The decode register setup is a bit weird... region | |
743 | * 0xf8000000 for example is marked as enabled in there while it's | |
744 | & actually the memory controller registers. | |
745 | * That means that we are incorrectly attributing it to HT. | |
746 | * | |
747 | * In a similar vein, region 0xf4000000 is actually the HT IO space but | |
748 | * also marked as enabled in here and 0xf9000000 is used by some other | |
749 | * internal bits of the northbridge. | |
750 | * | |
751 | * Unfortunately, we can't just mask out those bit as we would end | |
752 | * up with more regions than we can cope (linux can only cope with | |
753 | * 3 memory regions for a PHB at this stage). | |
754 | * | |
755 | * So for now, we just do a little hack. We happen to -know- that | |
756 | * Apple firmware doesn't assign things below 0xfa000000 for that | |
757 | * bridge anyway so we mask out all bits we don't want. | |
14cf11af | 758 | */ |
d0264ce7 BH |
759 | decode &= 0x003fffff; |
760 | ||
761 | /* Now parse the resulting bits and build resources */ | |
762 | parse_region_decode(hose, decode); | |
14cf11af | 763 | } |
cc5d0189 | 764 | #endif /* CONFIG_PPC64 */ |
14cf11af PM |
765 | |
766 | /* | |
767 | * We assume that if we have a G3 powermac, we have one bridge called | |
768 | * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, | |
769 | * if we have one or more bandit or chaos bridges, we don't have a MPC106. | |
770 | */ | |
09b55f76 | 771 | static int __init pmac_add_bridge(struct device_node *dev) |
14cf11af PM |
772 | { |
773 | int len; | |
774 | struct pci_controller *hose; | |
cc5d0189 | 775 | struct resource rsrc; |
35499c01 | 776 | char *disp_name; |
018a3d1d | 777 | const int *bus_range; |
618a89d7 | 778 | int primary = 1; |
14cf11af | 779 | |
b7c670d6 | 780 | DBG("Adding PCI host bridge %pOF\n", dev); |
14cf11af | 781 | |
cc5d0189 | 782 | /* Fetch host bridge registers address */ |
618a89d7 | 783 | of_address_to_resource(dev, 0, &rsrc); |
cc5d0189 BH |
784 | |
785 | /* Get bus range if any */ | |
e2eb6392 | 786 | bus_range = of_get_property(dev, "bus-range", &len); |
35499c01 | 787 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
b7c670d6 RH |
788 | printk(KERN_WARNING "Can't get bus-range for %pOF, assume" |
789 | " bus 0\n", dev); | |
35499c01 PM |
790 | } |
791 | ||
b5166cc2 | 792 | hose = pcibios_alloc_controller(dev); |
35499c01 PM |
793 | if (!hose) |
794 | return -ENOMEM; | |
35499c01 PM |
795 | hose->first_busno = bus_range ? bus_range[0] : 0; |
796 | hose->last_busno = bus_range ? bus_range[1] : 0xff; | |
e63f26d3 | 797 | hose->controller_ops = pmac_pci_controller_ops; |
14cf11af PM |
798 | |
799 | disp_name = NULL; | |
cc5d0189 BH |
800 | |
801 | /* 64 bits only bridges */ | |
b5166cc2 | 802 | #ifdef CONFIG_PPC64 |
55b61fec | 803 | if (of_device_is_compatible(dev, "u3-agp")) { |
35499c01 PM |
804 | setup_u3_agp(hose); |
805 | disp_name = "U3-AGP"; | |
806 | primary = 0; | |
55b61fec | 807 | } else if (of_device_is_compatible(dev, "u3-ht")) { |
35499c01 PM |
808 | setup_u3_ht(hose); |
809 | disp_name = "U3-HT"; | |
810 | primary = 1; | |
55b61fec | 811 | } else if (of_device_is_compatible(dev, "u4-pcie")) { |
1beb6a7d BH |
812 | setup_u4_pcie(hose); |
813 | disp_name = "U4-PCIE"; | |
814 | primary = 0; | |
35499c01 | 815 | } |
1beb6a7d BH |
816 | printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:" |
817 | " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); | |
cc5d0189 BH |
818 | #endif /* CONFIG_PPC64 */ |
819 | ||
820 | /* 32 bits only bridges */ | |
821 | #ifdef CONFIG_PPC32 | |
55b61fec | 822 | if (of_device_is_compatible(dev, "uni-north")) { |
cc5d0189 | 823 | primary = setup_uninorth(hose, &rsrc); |
35499c01 | 824 | disp_name = "UniNorth"; |
2c8e65b5 | 825 | } else if (of_node_name_eq(dev, "pci")) { |
35499c01 PM |
826 | /* XXX assume this is a mpc106 (grackle) */ |
827 | setup_grackle(hose); | |
828 | disp_name = "Grackle (MPC106)"; | |
2c8e65b5 | 829 | } else if (of_node_name_eq(dev, "bandit")) { |
cc5d0189 | 830 | setup_bandit(hose, &rsrc); |
35499c01 | 831 | disp_name = "Bandit"; |
2c8e65b5 | 832 | } else if (of_node_name_eq(dev, "chaos")) { |
cc5d0189 | 833 | setup_chaos(hose, &rsrc); |
35499c01 PM |
834 | disp_name = "Chaos"; |
835 | primary = 0; | |
836 | } | |
685143ac | 837 | printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. " |
cc5d0189 | 838 | "Firmware bus number: %d->%d\n", |
685143ac GKH |
839 | disp_name, (unsigned long long)rsrc.start, hose->first_busno, |
840 | hose->last_busno); | |
cc5d0189 BH |
841 | #endif /* CONFIG_PPC32 */ |
842 | ||
35499c01 PM |
843 | DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", |
844 | hose, hose->cfg_addr, hose->cfg_data); | |
845 | ||
846 | /* Interpret the "ranges" property */ | |
847 | /* This also maps the I/O region and sets isa_io/mem_base */ | |
848 | pci_process_bridge_OF_ranges(hose, dev, primary); | |
849 | ||
850 | /* Fixup "bus-range" OF property */ | |
851 | fixup_bus_range(dev); | |
14cf11af PM |
852 | |
853 | return 0; | |
854 | } | |
855 | ||
cad5cef6 | 856 | void pmac_pci_irq_fixup(struct pci_dev *dev) |
14cf11af | 857 | { |
6e99e458 | 858 | #ifdef CONFIG_PPC32 |
f90bb153 BH |
859 | /* Fixup interrupt for the modem/ethernet combo controller. |
860 | * on machines with a second ohare chip. | |
861 | * The number in the device tree (27) is bogus (correct for | |
862 | * the ethernet-only board but not the combo ethernet/modem | |
863 | * board). The real interrupt is 28 on the second controller | |
864 | * -> 28+32 = 60. | |
865 | */ | |
866 | if (has_second_ohare && | |
867 | dev->vendor == PCI_VENDOR_ID_DEC && | |
868 | dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { | |
869 | dev->irq = irq_create_mapping(NULL, 60); | |
ec775d0e | 870 | irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); |
14cf11af | 871 | } |
f90bb153 | 872 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
873 | } |
874 | ||
8cc7581c GS |
875 | #ifdef CONFIG_PPC64 |
876 | static int pmac_pci_root_bridge_prepare(struct pci_host_bridge *bridge) | |
877 | { | |
878 | struct pci_controller *hose = pci_bus_to_host(bridge->bus); | |
879 | struct device_node *np, *child; | |
880 | ||
881 | if (hose != u3_agp) | |
882 | return 0; | |
883 | ||
884 | /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We | |
885 | * assume there is no P2P bridge on the AGP bus, which should be a | |
886 | * safe assumptions for now. We should do something better in the | |
887 | * future though | |
888 | */ | |
889 | np = hose->dn; | |
890 | PCI_DN(np)->busno = 0xf0; | |
891 | for_each_child_of_node(np, child) | |
892 | PCI_DN(child)->busno = 0xf0; | |
893 | ||
894 | return 0; | |
895 | } | |
896 | #endif /* CONFIG_PPC64 */ | |
897 | ||
35499c01 | 898 | void __init pmac_pci_init(void) |
3c3f42d6 PM |
899 | { |
900 | struct device_node *np, *root; | |
618a89d7 | 901 | struct device_node *ht __maybe_unused = NULL; |
3c3f42d6 | 902 | |
0e47ff1c | 903 | pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN); |
3fd94c6b | 904 | |
3c3f42d6 PM |
905 | root = of_find_node_by_path("/"); |
906 | if (root == NULL) { | |
35499c01 PM |
907 | printk(KERN_CRIT "pmac_pci_init: can't find root " |
908 | "of device tree\n"); | |
3c3f42d6 PM |
909 | return; |
910 | } | |
2c8e65b5 RH |
911 | for_each_child_of_node(root, np) { |
912 | if (of_node_name_eq(np, "bandit") | |
913 | || of_node_name_eq(np, "chaos") | |
914 | || of_node_name_eq(np, "pci")) { | |
09b55f76 | 915 | if (pmac_add_bridge(np) == 0) |
3c3f42d6 PM |
916 | of_node_get(np); |
917 | } | |
2c8e65b5 | 918 | if (of_node_name_eq(np, "ht")) { |
3c3f42d6 PM |
919 | of_node_get(np); |
920 | ht = np; | |
921 | } | |
922 | } | |
923 | of_node_put(root); | |
924 | ||
35499c01 | 925 | #ifdef CONFIG_PPC64 |
3c3f42d6 PM |
926 | /* Probe HT last as it relies on the agp resources to be already |
927 | * setup | |
928 | */ | |
09b55f76 | 929 | if (ht && pmac_add_bridge(ht) != 0) |
3c3f42d6 PM |
930 | of_node_put(ht); |
931 | ||
8cc7581c | 932 | ppc_md.pcibios_root_bridge_prepare = pmac_pci_root_bridge_prepare; |
35499c01 PM |
933 | /* pmac_check_ht_link(); */ |
934 | ||
35499c01 | 935 | #else /* CONFIG_PPC64 */ |
3c3f42d6 | 936 | init_p2pbridge(); |
0ebfff14 | 937 | init_second_ohare(); |
3c3f42d6 | 938 | fixup_nec_usb2(); |
35499c01 | 939 | |
3c3f42d6 PM |
940 | /* We are still having some issues with the Xserve G4, enabling |
941 | * some offset between bus number and domains for now when we | |
942 | * assign all busses should help for now | |
943 | */ | |
0e47ff1c | 944 | if (pci_has_flag(PCI_REASSIGN_ALL_BUS)) |
3c3f42d6 | 945 | pcibios_assign_bus_offset = 0x10; |
35499c01 | 946 | #endif |
3c3f42d6 PM |
947 | } |
948 | ||
bc0826cf | 949 | #ifdef CONFIG_PPC32 |
e63f26d3 | 950 | static bool pmac_pci_enable_device_hook(struct pci_dev *dev) |
14cf11af PM |
951 | { |
952 | struct device_node* node; | |
953 | int updatecfg = 0; | |
954 | int uninorth_child; | |
955 | ||
956 | node = pci_device_to_OF_node(dev); | |
957 | ||
958 | /* We don't want to enable USB controllers absent from the OF tree | |
959 | * (iBook second controller) | |
960 | */ | |
961 | if (dev->vendor == PCI_VENDOR_ID_APPLE | |
c67808ee | 962 | && dev->class == PCI_CLASS_SERIAL_USB_OHCI |
14cf11af PM |
963 | && !node) { |
964 | printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", | |
965 | pci_name(dev)); | |
c88c2a18 | 966 | return false; |
14cf11af PM |
967 | } |
968 | ||
969 | if (!node) | |
c88c2a18 | 970 | return true; |
14cf11af PM |
971 | |
972 | uninorth_child = node->parent && | |
55b61fec | 973 | of_device_is_compatible(node->parent, "uni-north"); |
35499c01 | 974 | |
14cf11af PM |
975 | /* Firewire & GMAC were disabled after PCI probe, the driver is |
976 | * claiming them, we must re-enable them now. | |
977 | */ | |
2c8e65b5 | 978 | if (uninorth_child && of_node_name_eq(node, "firewire") && |
55b61fec SR |
979 | (of_device_is_compatible(node, "pci106b,18") || |
980 | of_device_is_compatible(node, "pci106b,30") || | |
981 | of_device_is_compatible(node, "pci11c1,5811"))) { | |
14cf11af PM |
982 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); |
983 | pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); | |
984 | updatecfg = 1; | |
985 | } | |
2c8e65b5 | 986 | if (uninorth_child && of_node_name_eq(node, "ethernet") && |
55b61fec | 987 | of_device_is_compatible(node, "gmac")) { |
14cf11af PM |
988 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); |
989 | updatecfg = 1; | |
990 | } | |
991 | ||
549beb9b BH |
992 | /* |
993 | * Fixup various header fields on 32 bits. We don't do that on | |
994 | * 64 bits as some of these have strange values behind the HT | |
995 | * bridge and we must not, for example, enable MWI or set the | |
996 | * cache line size on them. | |
997 | */ | |
14cf11af PM |
998 | if (updatecfg) { |
999 | u16 cmd; | |
35499c01 | 1000 | |
14cf11af | 1001 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
35499c01 PM |
1002 | cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
1003 | | PCI_COMMAND_INVALIDATE; | |
1004 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1005 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); | |
549beb9b | 1006 | |
35499c01 PM |
1007 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, |
1008 | L1_CACHE_BYTES >> 2); | |
14cf11af PM |
1009 | } |
1010 | ||
c88c2a18 | 1011 | return true; |
14cf11af PM |
1012 | } |
1013 | ||
618a89d7 | 1014 | static void pmac_pci_fixup_ohci(struct pci_dev *dev) |
bc0826cf BH |
1015 | { |
1016 | struct device_node *node = pci_device_to_OF_node(dev); | |
1017 | ||
1018 | /* We don't want to assign resources to USB controllers | |
1019 | * absent from the OF tree (iBook second controller) | |
1020 | */ | |
1021 | if (dev->class == PCI_CLASS_SERIAL_USB_OHCI && !node) | |
1022 | dev->resource[0].flags = 0; | |
1023 | } | |
1024 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_ANY_ID, pmac_pci_fixup_ohci); | |
1025 | ||
14cf11af PM |
1026 | /* We power down some devices after they have been probed. They'll |
1027 | * be powered back on later on | |
1028 | */ | |
35499c01 | 1029 | void __init pmac_pcibios_after_init(void) |
14cf11af PM |
1030 | { |
1031 | struct device_node* nd; | |
1032 | ||
30686ba6 | 1033 | for_each_node_by_name(nd, "firewire") { |
55b61fec SR |
1034 | if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") || |
1035 | of_device_is_compatible(nd, "pci106b,30") || | |
1036 | of_device_is_compatible(nd, "pci11c1,5811")) | |
1037 | && of_device_is_compatible(nd->parent, "uni-north")) { | |
14cf11af PM |
1038 | pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); |
1039 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); | |
1040 | } | |
14cf11af | 1041 | } |
30686ba6 | 1042 | for_each_node_by_name(nd, "ethernet") { |
55b61fec SR |
1043 | if (nd->parent && of_device_is_compatible(nd, "gmac") |
1044 | && of_device_is_compatible(nd->parent, "uni-north")) | |
14cf11af | 1045 | pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); |
14cf11af PM |
1046 | } |
1047 | } | |
1048 | ||
618a89d7 | 1049 | static void pmac_pci_fixup_cardbus(struct pci_dev *dev) |
14cf11af | 1050 | { |
e8222502 | 1051 | if (!machine_is(powermac)) |
14cf11af PM |
1052 | return; |
1053 | /* | |
1054 | * Fix the interrupt routing on the various cardbus bridges | |
1055 | * used on powerbooks | |
1056 | */ | |
1057 | if (dev->vendor != PCI_VENDOR_ID_TI) | |
1058 | return; | |
1059 | if (dev->device == PCI_DEVICE_ID_TI_1130 || | |
1060 | dev->device == PCI_DEVICE_ID_TI_1131) { | |
1061 | u8 val; | |
35499c01 | 1062 | /* Enable PCI interrupt */ |
14cf11af PM |
1063 | if (pci_read_config_byte(dev, 0x91, &val) == 0) |
1064 | pci_write_config_byte(dev, 0x91, val | 0x30); | |
1065 | /* Disable ISA interrupt mode */ | |
1066 | if (pci_read_config_byte(dev, 0x92, &val) == 0) | |
1067 | pci_write_config_byte(dev, 0x92, val & ~0x06); | |
1068 | } | |
1069 | if (dev->device == PCI_DEVICE_ID_TI_1210 || | |
1070 | dev->device == PCI_DEVICE_ID_TI_1211 || | |
1071 | dev->device == PCI_DEVICE_ID_TI_1410 || | |
1072 | dev->device == PCI_DEVICE_ID_TI_1510) { | |
1073 | u8 val; | |
1074 | /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA | |
1075 | signal out the MFUNC0 pin */ | |
1076 | if (pci_read_config_byte(dev, 0x8c, &val) == 0) | |
1077 | pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); | |
1078 | /* Disable ISA interrupt mode */ | |
1079 | if (pci_read_config_byte(dev, 0x92, &val) == 0) | |
1080 | pci_write_config_byte(dev, 0x92, val & ~0x06); | |
1081 | } | |
1082 | } | |
1083 | ||
1084 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); | |
1085 | ||
618a89d7 | 1086 | static void pmac_pci_fixup_pciata(struct pci_dev *dev) |
14cf11af PM |
1087 | { |
1088 | u8 progif = 0; | |
1089 | ||
1090 | /* | |
1091 | * On PowerMacs, we try to switch any PCI ATA controller to | |
1092 | * fully native mode | |
1093 | */ | |
e8222502 | 1094 | if (!machine_is(powermac)) |
14cf11af | 1095 | return; |
e8222502 | 1096 | |
14cf11af PM |
1097 | /* Some controllers don't have the class IDE */ |
1098 | if (dev->vendor == PCI_VENDOR_ID_PROMISE) | |
1099 | switch(dev->device) { | |
1100 | case PCI_DEVICE_ID_PROMISE_20246: | |
1101 | case PCI_DEVICE_ID_PROMISE_20262: | |
1102 | case PCI_DEVICE_ID_PROMISE_20263: | |
1103 | case PCI_DEVICE_ID_PROMISE_20265: | |
1104 | case PCI_DEVICE_ID_PROMISE_20267: | |
1105 | case PCI_DEVICE_ID_PROMISE_20268: | |
1106 | case PCI_DEVICE_ID_PROMISE_20269: | |
1107 | case PCI_DEVICE_ID_PROMISE_20270: | |
1108 | case PCI_DEVICE_ID_PROMISE_20271: | |
1109 | case PCI_DEVICE_ID_PROMISE_20275: | |
1110 | case PCI_DEVICE_ID_PROMISE_20276: | |
1111 | case PCI_DEVICE_ID_PROMISE_20277: | |
1112 | goto good; | |
1113 | } | |
1114 | /* Others, check PCI class */ | |
1115 | if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) | |
1116 | return; | |
1117 | good: | |
1118 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
1119 | if ((progif & 5) != 5) { | |
6d98bda7 | 1120 | printk(KERN_INFO "PCI: %s Forcing PCI IDE into native mode\n", |
1beb6a7d | 1121 | pci_name(dev)); |
14cf11af PM |
1122 | (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); |
1123 | if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || | |
1124 | (progif & 5) != 5) | |
1125 | printk(KERN_ERR "Rewrite of PROGIF failed !\n"); | |
6d98bda7 BH |
1126 | else { |
1127 | /* Clear IO BARs, they will be reassigned */ | |
1128 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0); | |
1129 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); | |
1130 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0); | |
1131 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0); | |
1132 | } | |
14cf11af PM |
1133 | } |
1134 | } | |
6d98bda7 | 1135 | DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); |
bc0826cf | 1136 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
1137 | |
1138 | /* | |
1139 | * Disable second function on K2-SATA, it's broken | |
1140 | * and disable IO BARs on first one | |
1141 | */ | |
1142 | static void fixup_k2_sata(struct pci_dev* dev) | |
1143 | { | |
1144 | int i; | |
1145 | u16 cmd; | |
1146 | ||
1147 | if (PCI_FUNC(dev->devfn) > 0) { | |
1148 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1149 | cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); | |
1150 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1151 | for (i = 0; i < 6; i++) { | |
1152 | dev->resource[i].start = dev->resource[i].end = 0; | |
1153 | dev->resource[i].flags = 0; | |
1beb6a7d BH |
1154 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, |
1155 | 0); | |
14cf11af PM |
1156 | } |
1157 | } else { | |
1158 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1159 | cmd &= ~PCI_COMMAND_IO; | |
1160 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1161 | for (i = 0; i < 5; i++) { | |
1162 | dev->resource[i].start = dev->resource[i].end = 0; | |
1163 | dev->resource[i].flags = 0; | |
1beb6a7d BH |
1164 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, |
1165 | 0); | |
14cf11af PM |
1166 | } |
1167 | } | |
1168 | } | |
1169 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); | |
1170 | ||
cede3930 BH |
1171 | /* |
1172 | * On U4 (aka CPC945) the PCIe root complex "P2P" bridge resource ranges aren't | |
1173 | * configured by the firmware. The bridge itself seems to ignore them but it | |
1174 | * causes problems with Linux which then re-assigns devices below the bridge, | |
1175 | * thus changing addresses of those devices from what was in the device-tree, | |
1176 | * which sucks when those are video cards using offb | |
1177 | * | |
1178 | * We could just mark it transparent but I prefer fixing up the resources to | |
1179 | * properly show what's going on here, as I have some doubts about having them | |
1180 | * badly configured potentially being an issue for DMA. | |
1181 | * | |
1182 | * We leave PIO alone, it seems to be fine | |
1183 | * | |
1184 | * Oh and there's another funny bug. The OF properties advertize the region | |
1185 | * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's | |
1186 | * actually not true, this region is the memory mapped config space. So we | |
1187 | * also need to filter it out or we'll map things in the wrong place. | |
1188 | */ | |
1189 | static void fixup_u4_pcie(struct pci_dev* dev) | |
1190 | { | |
1191 | struct pci_controller *host = pci_bus_to_host(dev->bus); | |
1192 | struct resource *region = NULL; | |
1193 | u32 reg; | |
1194 | int i; | |
1195 | ||
1196 | /* Only do that on PowerMac */ | |
1197 | if (!machine_is(powermac)) | |
1198 | return; | |
1199 | ||
1200 | /* Find the largest MMIO region */ | |
1201 | for (i = 0; i < 3; i++) { | |
1202 | struct resource *r = &host->mem_resources[i]; | |
1203 | if (!(r->flags & IORESOURCE_MEM)) | |
1204 | continue; | |
1205 | /* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they | |
1206 | * are reserved by HW for other things | |
1207 | */ | |
1208 | if (r->start >= 0xf0000000 && r->start < 0xf3000000) | |
1209 | continue; | |
28f65c11 | 1210 | if (!region || resource_size(r) > resource_size(region)) |
cede3930 BH |
1211 | region = r; |
1212 | } | |
1213 | /* Nothing found, bail */ | |
d8731527 | 1214 | if (!region) |
cede3930 BH |
1215 | return; |
1216 | ||
1217 | /* Print things out */ | |
1218 | printk(KERN_INFO "PCI: Fixup U4 PCIe bridge range: %pR\n", region); | |
1219 | ||
1220 | /* Fixup bridge config space. We know it's a Mac, resource aren't | |
1221 | * offset so let's just blast them as-is. We also know that they | |
1222 | * fit in 32 bits | |
1223 | */ | |
1224 | reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000); | |
1225 | pci_write_config_dword(dev, PCI_MEMORY_BASE, reg); | |
1226 | pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0); | |
1227 | pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); | |
1228 | pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0); | |
1229 | } | |
1230 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie); | |
ba9c8f22 DA |
1231 | |
1232 | #ifdef CONFIG_PPC64 | |
e63f26d3 | 1233 | static int pmac_pci_probe_mode(struct pci_bus *bus) |
ba9c8f22 DA |
1234 | { |
1235 | struct device_node *node = pci_bus_to_OF_node(bus); | |
1236 | ||
1237 | /* We need to use normal PCI probing for the AGP bus, | |
1238 | * since the device for the AGP bridge isn't in the tree. | |
1239 | * Same for the PCIe host on U4 and the HT host bridge. | |
1240 | */ | |
1241 | if (bus->self == NULL && (of_device_is_compatible(node, "u3-agp") || | |
1242 | of_device_is_compatible(node, "u4-pcie") || | |
1243 | of_device_is_compatible(node, "u3-ht"))) | |
1244 | return PCI_PROBE_NORMAL; | |
1245 | return PCI_PROBE_DEVTREE; | |
1246 | } | |
1247 | #endif /* CONFIG_PPC64 */ | |
e63f26d3 DA |
1248 | |
1249 | struct pci_controller_ops pmac_pci_controller_ops = { | |
1250 | #ifdef CONFIG_PPC64 | |
1251 | .probe_mode = pmac_pci_probe_mode, | |
1252 | #endif | |
1253 | #ifdef CONFIG_PPC32 | |
1254 | .enable_device_hook = pmac_pci_enable_device_hook, | |
1255 | #endif | |
1256 | }; |