[linux-2.6-block.git] / arch / powerpc / platforms / powermac / nvram.c

/*
 *  Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 *  Todo: - add support for the OF persistent properties
 */
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/stddef.h>
#include <linux/string.h>
#include <linux/nvram.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/adb.h>
#include <linux/pmu.h>
#include <linux/memblock.h>
#include <linux/completion.h>
#include <linux/spinlock.h>
#include <asm/sections.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/nvram.h>

#include "pmac.h"

#define DEBUG

#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

#define NVRAM_SIZE		0x2000	/* 8kB of non-volatile RAM */

#define CORE99_SIGNATURE	0x5a
#define CORE99_ADLER_START	0x14

/* On Core99, nvram is either a sharp, a micron or an AMD flash */
#define SM_FLASH_STATUS_DONE	0x80
#define SM_FLASH_STATUS_ERR	0x38

#define SM_FLASH_CMD_ERASE_CONFIRM	0xd0
#define SM_FLASH_CMD_ERASE_SETUP	0x20
#define SM_FLASH_CMD_RESET		0xff
#define SM_FLASH_CMD_WRITE_SETUP	0x40
#define SM_FLASH_CMD_CLEAR_STATUS	0x50
#define SM_FLASH_CMD_READ_STATUS	0x70

/* CHRP NVRAM header */
struct chrp_header {
  u8		signature;
  u8		cksum;
  u16		len;
  char          name[12];
  u8		data[0];
};

struct core99_header {
  struct chrp_header	hdr;
  u32			adler;
  u32			generation;
  u32			reserved[2];
};

/*
 * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
 */
static int nvram_naddrs;
static volatile unsigned char __iomem *nvram_data;
static int is_core_99;
static int core99_bank = 0;
static int nvram_partitions[3];
// XXX Turn that into a sem
static DEFINE_RAW_SPINLOCK(nv_lock);

static int (*core99_write_bank)(int bank, u8* datas);
static int (*core99_erase_bank)(int bank);

static char *nvram_image;


static unsigned char core99_nvram_read_byte(int addr)
{
	if (nvram_image == NULL)
		return 0xff;
	return nvram_image[addr];
}

static void core99_nvram_write_byte(int addr, unsigned char val)
{
	if (nvram_image == NULL)
		return;
	nvram_image[addr] = val;
}

static ssize_t core99_nvram_read(char *buf, size_t count, loff_t *index)
{
	int i;

	if (nvram_image == NULL)
		return -ENODEV;
	if (*index > NVRAM_SIZE)
		return 0;

	i = *index;
	if (i + count > NVRAM_SIZE)
		count = NVRAM_SIZE - i;

	memcpy(buf, &nvram_image[i], count);
	*index = i + count;
	return count;
}

static ssize_t core99_nvram_write(char *buf, size_t count, loff_t *index)
{
	int i;

	if (nvram_image == NULL)
		return -ENODEV;
	if (*index > NVRAM_SIZE)
		return 0;

	i = *index;
	if (i + count > NVRAM_SIZE)
		count = NVRAM_SIZE - i;

	memcpy(&nvram_image[i], buf, count);
	*index = i + count;
	return count;
}

static ssize_t core99_nvram_size(void)
{
	if (nvram_image == NULL)
		return -ENODEV;
	return NVRAM_SIZE;
}

#ifdef CONFIG_PPC32
static volatile unsigned char __iomem *nvram_addr;
static int nvram_mult;

static unsigned char direct_nvram_read_byte(int addr)
{
	return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
}

static void direct_nvram_write_byte(int addr, unsigned char val)
{
	out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
}


static unsigned char indirect_nvram_read_byte(int addr)
{
	unsigned char val;
	unsigned long flags;

	raw_spin_lock_irqsave(&nv_lock, flags);
	out_8(nvram_addr, addr >> 5);
	val = in_8(&nvram_data[(addr & 0x1f) << 4]);
	raw_spin_unlock_irqrestore(&nv_lock, flags);

	return val;
}

static void indirect_nvram_write_byte(int addr, unsigned char val)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&nv_lock, flags);
	out_8(nvram_addr, addr >> 5);
	out_8(&nvram_data[(addr & 0x1f) << 4], val);
	raw_spin_unlock_irqrestore(&nv_lock, flags);
}


#ifdef CONFIG_ADB_PMU

static void pmu_nvram_complete(struct adb_request *req)
{
	if (req->arg)
		complete((struct completion *)req->arg);
}

static unsigned char pmu_nvram_read_byte(int addr)
{
	struct adb_request req;
	DECLARE_COMPLETION_ONSTACK(req_complete);
	
	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
	if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
			(addr >> 8) & 0xff, addr & 0xff))
		return 0xff;
	if (system_state == SYSTEM_RUNNING)
		wait_for_completion(&req_complete);
	while (!req.complete)
		pmu_poll();
	return req.reply[0];
}

static void pmu_nvram_write_byte(int addr, unsigned char val)
{
	struct adb_request req;
	DECLARE_COMPLETION_ONSTACK(req_complete);
	
	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
	if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
			(addr >> 8) & 0xff, addr & 0xff, val))
		return;
	if (system_state == SYSTEM_RUNNING)
		wait_for_completion(&req_complete);
	while (!req.complete)
		pmu_poll();
}

#endif /* CONFIG_ADB_PMU */
#endif /* CONFIG_PPC32 */

static u8 chrp_checksum(struct chrp_header* hdr)
{
	u8 *ptr;
	u16 sum = hdr->signature;
	for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
		sum += *ptr;
	while (sum > 0xFF)
		sum = (sum & 0xFF) + (sum>>8);
	return sum;
}

static u32 core99_calc_adler(u8 *buffer)
{
	int cnt;
	u32 low, high;

   	buffer += CORE99_ADLER_START;
	low = 1;
	high = 0;
	for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
		if ((cnt % 5000) == 0) {
			high  %= 65521UL;
			high %= 65521UL;
		}
		low += buffer[cnt];
		high += low;
	}
	low  %= 65521UL;
	high %= 65521UL;

	return (high << 16) | low;
}

static u32 core99_check(u8* datas)
{
	struct core99_header* hdr99 = (struct core99_header*)datas;

	if (hdr99->hdr.signature != CORE99_SIGNATURE) {
		DBG("Invalid signature\n");
		return 0;
	}
	if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
		DBG("Invalid checksum\n");
		return 0;
	}
	if (hdr99->adler != core99_calc_adler(datas)) {
		DBG("Invalid adler\n");
		return 0;
	}
	return hdr99->generation;
}

static int sm_erase_bank(int bank)
{
	int stat;
	unsigned long timeout;

	u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);

	out_8(base, SM_FLASH_CMD_ERASE_SETUP);
	out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
	timeout = 0;
	do {
		if (++timeout > 1000000) {
			printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n");
			break;
		}
		out_8(base, SM_FLASH_CMD_READ_STATUS);
		stat = in_8(base);
	} while (!(stat & SM_FLASH_STATUS_DONE));

	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	out_8(base, SM_FLASH_CMD_RESET);

	if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
		printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
		return -ENXIO;
	}
	return 0;
}

static int sm_write_bank(int bank, u8* datas)
{
	int i, stat = 0;
	unsigned long timeout;

	u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);

	for (i=0; i<NVRAM_SIZE; i++) {
		out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
		udelay(1);
		out_8(base+i, datas[i]);
		timeout = 0;
		do {
			if (++timeout > 1000000) {
				printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
				break;
			}
			out_8(base, SM_FLASH_CMD_READ_STATUS);
			stat = in_8(base);
		} while (!(stat & SM_FLASH_STATUS_DONE));
		if (!(stat & SM_FLASH_STATUS_DONE))
			break;
	}
	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	out_8(base, SM_FLASH_CMD_RESET);
	if (memcmp(base, datas, NVRAM_SIZE)) {
		printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
		return -ENXIO;
	}
	return 0;
}

static int amd_erase_bank(int bank)
{
	int stat = 0;
	unsigned long timeout;

	u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: AMD Erasing bank %d...\n", bank);

	/* Unlock 1 */
	out_8(base+0x555, 0xaa);
	udelay(1);
	/* Unlock 2 */
	out_8(base+0x2aa, 0x55);
	udelay(1);

	/* Sector-Erase */
	out_8(base+0x555, 0x80);
	udelay(1);
	out_8(base+0x555, 0xaa);
	udelay(1);
	out_8(base+0x2aa, 0x55);
	udelay(1);
	out_8(base, 0x30);
	udelay(1);

	timeout = 0;
	do {
		if (++timeout > 1000000) {
			printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
			break;
		}
		stat = in_8(base) ^ in_8(base);
	} while (stat != 0);
	
	/* Reset */
	out_8(base, 0xf0);
	udelay(1);

	if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
		printk(KERN_ERR "nvram: AMD flash erase failed !\n");
		return -ENXIO;
	}
	return 0;
}

static int amd_write_bank(int bank, u8* datas)
{
	int i, stat = 0;
	unsigned long timeout;

	u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;

       	DBG("nvram: AMD Writing bank %d...\n", bank);

	for (i=0; i<NVRAM_SIZE; i++) {
		/* Unlock 1 */
		out_8(base+0x555, 0xaa);
		udelay(1);
		/* Unlock 2 */
		out_8(base+0x2aa, 0x55);
		udelay(1);

		/* Write single word */
		out_8(base+0x555, 0xa0);
		udelay(1);
		out_8(base+i, datas[i]);
		
		timeout = 0;
		do {
			if (++timeout > 1000000) {
				printk(KERN_ERR "nvram: AMD flash write timeout !\n");
				break;
			}
			stat = in_8(base) ^ in_8(base);
		} while (stat != 0);
		if (stat != 0)
			break;
	}

	/* Reset */
	out_8(base, 0xf0);
	udelay(1);

	if (memcmp(base, datas, NVRAM_SIZE)) {
		printk(KERN_ERR "nvram: AMD flash write failed !\n");
		return -ENXIO;
	}
	return 0;
}

static void __init lookup_partitions(void)
{
	u8 buffer[17];
	int i, offset;
	struct chrp_header* hdr;

	if (pmac_newworld) {
		nvram_partitions[pmac_nvram_OF] = -1;
		nvram_partitions[pmac_nvram_XPRAM] = -1;
		nvram_partitions[pmac_nvram_NR] = -1;
		hdr = (struct chrp_header *)buffer;

		offset = 0;
		buffer[16] = 0;
		do {
			for (i=0;i<16;i++)
				buffer[i] = ppc_md.nvram_read_val(offset+i);
			if (!strcmp(hdr->name, "common"))
				nvram_partitions[pmac_nvram_OF] = offset + 0x10;
			if (!strcmp(hdr->name, "APL,MacOS75")) {
				nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
				nvram_partitions[pmac_nvram_NR] = offset + 0x110;
			}
			offset += (hdr->len * 0x10);
		} while(offset < NVRAM_SIZE);
	} else {
		nvram_partitions[pmac_nvram_OF] = 0x1800;
		nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
		nvram_partitions[pmac_nvram_NR] = 0x1400;
	}
	DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
	DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
	DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
}

static void core99_nvram_sync(void)
{
	struct core99_header* hdr99;
	unsigned long flags;

	if (!is_core_99 || !nvram_data || !nvram_image)
		return;

	raw_spin_lock_irqsave(&nv_lock, flags);
	if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
		NVRAM_SIZE))
		goto bail;

	DBG("Updating nvram...\n");

	hdr99 = (struct core99_header*)nvram_image;
	hdr99->generation++;
	hdr99->hdr.signature = CORE99_SIGNATURE;
	hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
	hdr99->adler = core99_calc_adler(nvram_image);
	core99_bank = core99_bank ? 0 : 1;
	if (core99_erase_bank)
		if (core99_erase_bank(core99_bank)) {
			printk("nvram: Error erasing bank %d\n", core99_bank);
			goto bail;
		}
	if (core99_write_bank)
		if (core99_write_bank(core99_bank, nvram_image))
			printk("nvram: Error writing bank %d\n", core99_bank);
 bail:
	raw_spin_unlock_irqrestore(&nv_lock, flags);

#ifdef DEBUG
       	mdelay(2000);
#endif
}

static int __init core99_nvram_setup(struct device_node *dp, unsigned long addr)
{
	int i;
	u32 gen_bank0, gen_bank1;

	if (nvram_naddrs < 1) {
		printk(KERN_ERR "nvram: no address\n");
		return -EINVAL;
	}
	nvram_image = memblock_alloc(NVRAM_SIZE, SMP_CACHE_BYTES);
	nvram_data = ioremap(addr, NVRAM_SIZE*2);
	nvram_naddrs = 1; /* Make sure we get the correct case */

	DBG("nvram: Checking bank 0...\n");

	gen_bank0 = core99_check((u8 *)nvram_data);
	gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
	core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;

	DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
	DBG("nvram: Active bank is: %d\n", core99_bank);

	for (i=0; i<NVRAM_SIZE; i++)
		nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];

	ppc_md.nvram_read_val	= core99_nvram_read_byte;
	ppc_md.nvram_write_val	= core99_nvram_write_byte;
	ppc_md.nvram_read	= core99_nvram_read;
	ppc_md.nvram_write	= core99_nvram_write;
	ppc_md.nvram_size	= core99_nvram_size;
	ppc_md.nvram_sync	= core99_nvram_sync;
	ppc_md.machine_shutdown	= core99_nvram_sync;
	/* 
	 * Maybe we could be smarter here though making an exclusive list
	 * of known flash chips is a bit nasty as older OF didn't provide us
	 * with a useful "compatible" entry. A solution would be to really
	 * identify the chip using flash id commands and base ourselves on
	 * a list of known chips IDs
	 */
	if (of_device_is_compatible(dp, "amd-0137")) {
		core99_erase_bank = amd_erase_bank;
		core99_write_bank = amd_write_bank;
	} else {
		core99_erase_bank = sm_erase_bank;
		core99_write_bank = sm_write_bank;
	}
	return 0;
}

int __init pmac_nvram_init(void)
{
	struct device_node *dp;
	struct resource r1, r2;
	unsigned int s1 = 0, s2 = 0;
	int err = 0;

	nvram_naddrs = 0;

	dp = of_find_node_by_name(NULL, "nvram");
	if (dp == NULL) {
		printk(KERN_ERR "Can't find NVRAM device\n");
		return -ENODEV;
	}

	/* Try to obtain an address */
	if (of_address_to_resource(dp, 0, &r1) == 0) {
		nvram_naddrs = 1;
		s1 = resource_size(&r1);
		if (of_address_to_resource(dp, 1, &r2) == 0) {
			nvram_naddrs = 2;
			s2 = resource_size(&r2);
		}
	}

	is_core_99 = of_device_is_compatible(dp, "nvram,flash");
	if (is_core_99) {
		err = core99_nvram_setup(dp, r1.start);
		goto bail;
	}

#ifdef CONFIG_PPC32
	if (machine_is(chrp) && nvram_naddrs == 1) {
		nvram_data = ioremap(r1.start, s1);
		nvram_mult = 1;
		ppc_md.nvram_read_val	= direct_nvram_read_byte;
		ppc_md.nvram_write_val	= direct_nvram_write_byte;
	} else if (nvram_naddrs == 1) {
		nvram_data = ioremap(r1.start, s1);
		nvram_mult = (s1 + NVRAM_SIZE - 1) / NVRAM_SIZE;
		ppc_md.nvram_read_val	= direct_nvram_read_byte;
		ppc_md.nvram_write_val	= direct_nvram_write_byte;
	} else if (nvram_naddrs == 2) {
		nvram_addr = ioremap(r1.start, s1);
		nvram_data = ioremap(r2.start, s2);
		ppc_md.nvram_read_val	= indirect_nvram_read_byte;
		ppc_md.nvram_write_val	= indirect_nvram_write_byte;
	} else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
#ifdef CONFIG_ADB_PMU
		nvram_naddrs = -1;
		ppc_md.nvram_read_val	= pmu_nvram_read_byte;
		ppc_md.nvram_write_val	= pmu_nvram_write_byte;
#endif /* CONFIG_ADB_PMU */
	} else {
		printk(KERN_ERR "Incompatible type of NVRAM\n");
		err = -ENXIO;
	}
#endif /* CONFIG_PPC32 */
bail:
	of_node_put(dp);
	if (err == 0)
		lookup_partitions();
	return err;
}

int pmac_get_partition(int partition)
{
	return nvram_partitions[partition];
}

u8 pmac_xpram_read(int xpaddr)
{
	int offset = pmac_get_partition(pmac_nvram_XPRAM);

	if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
		return 0xff;

	return ppc_md.nvram_read_val(xpaddr + offset);
}

void pmac_xpram_write(int xpaddr, u8 data)
{
	int offset = pmac_get_partition(pmac_nvram_XPRAM);

	if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
		return;

	ppc_md.nvram_write_val(xpaddr + offset, data);
}

EXPORT_SYMBOL(pmac_get_partition);
EXPORT_SYMBOL(pmac_xpram_read);
EXPORT_SYMBOL(pmac_xpram_write);
Commit	Line	Data
14cf11af	1	/*
14cf11af PM	2	* Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*
	9	* Todo: - add support for the OF persistent properties
	10	*/
4b16f8e2	11	#include <linux/export.h>
14cf11af PM	12	#include <linux/kernel.h>
	13	#include <linux/stddef.h>
	14	#include <linux/string.h>
	15	#include <linux/nvram.h>
	16	#include <linux/init.h>
14cf11af PM	17	#include <linux/delay.h>
	18	#include <linux/errno.h>
	19	#include <linux/adb.h>
	20	#include <linux/pmu.h>
57c8a661	21	#include <linux/memblock.h>
14cf11af PM	22	#include <linux/completion.h>
	23	#include <linux/spinlock.h>
	24	#include <asm/sections.h>
	25	#include <asm/io.h>
14cf11af PM	26	#include <asm/prom.h>
	27	#include <asm/machdep.h>
	28	#include <asm/nvram.h>
	29
0ebfff14 BH	30	#include "pmac.h"
0ebfff14 BH	31
14cf11af PM	32	#define DEBUG
	33
	34	#ifdef DEBUG
	35	#define DBG(x...) printk(x)
	36	#else
	37	#define DBG(x...)
	38	#endif
	39
	40	#define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */
	41
	42	#define CORE99_SIGNATURE 0x5a
	43	#define CORE99_ADLER_START 0x14
	44
	45	/* On Core99, nvram is either a sharp, a micron or an AMD flash */
	46	#define SM_FLASH_STATUS_DONE 0x80
35499c01 PM	47	#define SM_FLASH_STATUS_ERR 0x38
35499c01 PM	48
14cf11af PM	49	#define SM_FLASH_CMD_ERASE_CONFIRM 0xd0
	50	#define SM_FLASH_CMD_ERASE_SETUP 0x20
	51	#define SM_FLASH_CMD_RESET 0xff
	52	#define SM_FLASH_CMD_WRITE_SETUP 0x40
	53	#define SM_FLASH_CMD_CLEAR_STATUS 0x50
	54	#define SM_FLASH_CMD_READ_STATUS 0x70
	55
	56	/* CHRP NVRAM header */
	57	struct chrp_header {
	58	u8 signature;
	59	u8 cksum;
	60	u16 len;
	61	char name[12];
	62	u8 data[0];
	63	};
	64
	65	struct core99_header {
	66	struct chrp_header hdr;
	67	u32 adler;
	68	u32 generation;
	69	u32 reserved[2];
	70	};
	71
	72	/*
	73	* Read and write the non-volatile RAM on PowerMacs and CHRP machines.
	74	*/
	75	static int nvram_naddrs;
af308377	76	static volatile unsigned char __iomem *nvram_data;
35499c01	77	static int is_core_99;
14cf11af PM	78	static int core99_bank = 0;
14cf11af PM	79	static int nvram_partitions[3];
35499c01	80	// XXX Turn that into a sem
7d725bdc	81	static DEFINE_RAW_SPINLOCK(nv_lock);
14cf11af	82
14cf11af PM	83	static int (core99_write_bank)(int bank, u8 datas);
	84	static int (*core99_erase_bank)(int bank);
	85
	86	static char *nvram_image;
	87
	88
	89	static unsigned char core99_nvram_read_byte(int addr)
	90	{
	91	if (nvram_image == NULL)
	92	return 0xff;
	93	return nvram_image[addr];
	94	}
	95
	96	static void core99_nvram_write_byte(int addr, unsigned char val)
	97	{
	98	if (nvram_image == NULL)
	99	return;
	100	nvram_image[addr] = val;
	101	}
	102
35499c01 PM	103	static ssize_t core99_nvram_read(char buf, size_t count, loff_t index)
	104	{
	105	int i;
	106
	107	if (nvram_image == NULL)
	108	return -ENODEV;
	109	if (*index > NVRAM_SIZE)
	110	return 0;
	111
	112	i = *index;
	113	if (i + count > NVRAM_SIZE)
	114	count = NVRAM_SIZE - i;
	115
	116	memcpy(buf, &nvram_image[i], count);
	117	*index = i + count;
	118	return count;
	119	}
	120
	121	static ssize_t core99_nvram_write(char buf, size_t count, loff_t index)
	122	{
	123	int i;
	124
	125	if (nvram_image == NULL)
	126	return -ENODEV;
	127	if (*index > NVRAM_SIZE)
	128	return 0;
	129
	130	i = *index;
	131	if (i + count > NVRAM_SIZE)
	132	count = NVRAM_SIZE - i;
	133
	134	memcpy(&nvram_image[i], buf, count);
	135	*index = i + count;
	136	return count;
	137	}
	138
	139	static ssize_t core99_nvram_size(void)
	140	{
	141	if (nvram_image == NULL)
	142	return -ENODEV;
	143	return NVRAM_SIZE;
	144	}
	145
	146	#ifdef CONFIG_PPC32
af308377	147	static volatile unsigned char __iomem *nvram_addr;
35499c01	148	static int nvram_mult;
14cf11af PM	149
	150	static unsigned char direct_nvram_read_byte(int addr)
	151	{
	152	return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
	153	}
	154
	155	static void direct_nvram_write_byte(int addr, unsigned char val)
	156	{
	157	out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
	158	}
	159
	160
	161	static unsigned char indirect_nvram_read_byte(int addr)
	162	{
	163	unsigned char val;
	164	unsigned long flags;
	165
7d725bdc	166	raw_spin_lock_irqsave(&nv_lock, flags);
14cf11af PM	167	out_8(nvram_addr, addr >> 5);
14cf11af PM	168	val = in_8(&nvram_data[(addr & 0x1f) << 4]);
7d725bdc	169	raw_spin_unlock_irqrestore(&nv_lock, flags);
14cf11af PM	170
	171	return val;
	172	}
	173
	174	static void indirect_nvram_write_byte(int addr, unsigned char val)
	175	{
	176	unsigned long flags;
	177
7d725bdc	178	raw_spin_lock_irqsave(&nv_lock, flags);
14cf11af PM	179	out_8(nvram_addr, addr >> 5);
14cf11af PM	180	out_8(&nvram_data[(addr & 0x1f) << 4], val);
7d725bdc	181	raw_spin_unlock_irqrestore(&nv_lock, flags);
14cf11af PM	182	}
	183
	184
	185	#ifdef CONFIG_ADB_PMU
	186
	187	static void pmu_nvram_complete(struct adb_request *req)
	188	{
	189	if (req->arg)
	190	complete((struct completion *)req->arg);
	191	}
	192
	193	static unsigned char pmu_nvram_read_byte(int addr)
	194	{
	195	struct adb_request req;
6e9a4738	196	DECLARE_COMPLETION_ONSTACK(req_complete);
14cf11af PM	197
	198	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
	199	if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
	200	(addr >> 8) & 0xff, addr & 0xff))
	201	return 0xff;
	202	if (system_state == SYSTEM_RUNNING)
	203	wait_for_completion(&req_complete);
	204	while (!req.complete)
	205	pmu_poll();
	206	return req.reply[0];
	207	}
	208
	209	static void pmu_nvram_write_byte(int addr, unsigned char val)
	210	{
	211	struct adb_request req;
6e9a4738	212	DECLARE_COMPLETION_ONSTACK(req_complete);
14cf11af PM	213
	214	req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
	215	if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
	216	(addr >> 8) & 0xff, addr & 0xff, val))
	217	return;
	218	if (system_state == SYSTEM_RUNNING)
	219	wait_for_completion(&req_complete);
	220	while (!req.complete)
	221	pmu_poll();
	222	}
	223
	224	#endif /* CONFIG_ADB_PMU */
35499c01	225	#endif /* CONFIG_PPC32 */
14cf11af PM	226
	227	static u8 chrp_checksum(struct chrp_header* hdr)
	228	{
	229	u8 *ptr;
	230	u16 sum = hdr->signature;
	231	for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
	232	sum += *ptr;
	233	while (sum > 0xFF)
	234	sum = (sum & 0xFF) + (sum>>8);
	235	return sum;
	236	}
	237
	238	static u32 core99_calc_adler(u8 *buffer)
	239	{
	240	int cnt;
	241	u32 low, high;
	242
	243	buffer += CORE99_ADLER_START;
	244	low = 1;
	245	high = 0;
	246	for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
	247	if ((cnt % 5000) == 0) {
	248	high %= 65521UL;
	249	high %= 65521UL;
	250	}
	251	low += buffer[cnt];
	252	high += low;
	253	}
	254	low %= 65521UL;
	255	high %= 65521UL;
	256
	257	return (high << 16) \| low;
	258	}
	259
	260	static u32 core99_check(u8* datas)
	261	{
	262	struct core99_header* hdr99 = (struct core99_header*)datas;
	263
	264	if (hdr99->hdr.signature != CORE99_SIGNATURE) {
	265	DBG("Invalid signature\n");
	266	return 0;
	267	}
	268	if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
	269	DBG("Invalid checksum\n");
	270	return 0;
	271	}
	272	if (hdr99->adler != core99_calc_adler(datas)) {
	273	DBG("Invalid adler\n");
	274	return 0;
	275	}
	276	return hdr99->generation;
	277	}
	278
	279	static int sm_erase_bank(int bank)
	280	{
2d4b9712	281	int stat;
14cf11af PM	282	unsigned long timeout;
14cf11af PM	283
af308377	284	u8 __iomem base = (u8 __iomem )nvram_data + core99_bank*NVRAM_SIZE;
14cf11af PM	285
	286	DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
	287
	288	out_8(base, SM_FLASH_CMD_ERASE_SETUP);
	289	out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
	290	timeout = 0;
	291	do {
	292	if (++timeout > 1000000) {
35499c01	293	printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n");
14cf11af PM	294	break;
	295	}
	296	out_8(base, SM_FLASH_CMD_READ_STATUS);
	297	stat = in_8(base);
	298	} while (!(stat & SM_FLASH_STATUS_DONE));
	299
	300	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	301	out_8(base, SM_FLASH_CMD_RESET);
	302
2d4b9712 AM	303	if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
	304	printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
	305	return -ENXIO;
	306	}
14cf11af PM	307	return 0;
	308	}
	309
	310	static int sm_write_bank(int bank, u8* datas)
	311	{
	312	int i, stat = 0;
	313	unsigned long timeout;
	314
af308377	315	u8 __iomem base = (u8 __iomem )nvram_data + core99_bank*NVRAM_SIZE;
14cf11af PM	316
	317	DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
	318
	319	for (i=0; i<NVRAM_SIZE; i++) {
	320	out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
	321	udelay(1);
	322	out_8(base+i, datas[i]);
	323	timeout = 0;
	324	do {
	325	if (++timeout > 1000000) {
	326	printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
	327	break;
	328	}
	329	out_8(base, SM_FLASH_CMD_READ_STATUS);
	330	stat = in_8(base);
	331	} while (!(stat & SM_FLASH_STATUS_DONE));
	332	if (!(stat & SM_FLASH_STATUS_DONE))
	333	break;
	334	}
	335	out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
	336	out_8(base, SM_FLASH_CMD_RESET);
2d4b9712 AM	337	if (memcmp(base, datas, NVRAM_SIZE)) {
	338	printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
	339	return -ENXIO;
	340	}
14cf11af PM	341	return 0;
	342	}
	343
	344	static int amd_erase_bank(int bank)
	345	{
2d4b9712	346	int stat = 0;
14cf11af PM	347	unsigned long timeout;
14cf11af PM	348
af308377	349	u8 __iomem base = (u8 __iomem )nvram_data + core99_bank*NVRAM_SIZE;
14cf11af PM	350
	351	DBG("nvram: AMD Erasing bank %d...\n", bank);
	352
	353	/* Unlock 1 */
	354	out_8(base+0x555, 0xaa);
	355	udelay(1);
	356	/* Unlock 2 */
	357	out_8(base+0x2aa, 0x55);
	358	udelay(1);
	359
	360	/* Sector-Erase */
	361	out_8(base+0x555, 0x80);
	362	udelay(1);
	363	out_8(base+0x555, 0xaa);
	364	udelay(1);
	365	out_8(base+0x2aa, 0x55);
	366	udelay(1);
	367	out_8(base, 0x30);
	368	udelay(1);
	369
	370	timeout = 0;
	371	do {
	372	if (++timeout > 1000000) {
	373	printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
	374	break;
	375	}
	376	stat = in_8(base) ^ in_8(base);
	377	} while (stat != 0);
	378
	379	/* Reset */
	380	out_8(base, 0xf0);
	381	udelay(1);
2d4b9712 AM	382
	383	if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
	384	printk(KERN_ERR "nvram: AMD flash erase failed !\n");
	385	return -ENXIO;
	386	}
14cf11af PM	387	return 0;
	388	}
	389
	390	static int amd_write_bank(int bank, u8* datas)
	391	{
	392	int i, stat = 0;
	393	unsigned long timeout;
	394
af308377	395	u8 __iomem base = (u8 __iomem )nvram_data + core99_bank*NVRAM_SIZE;
14cf11af PM	396
	397	DBG("nvram: AMD Writing bank %d...\n", bank);
	398
	399	for (i=0; i<NVRAM_SIZE; i++) {
	400	/* Unlock 1 */
	401	out_8(base+0x555, 0xaa);
	402	udelay(1);
	403	/* Unlock 2 */
	404	out_8(base+0x2aa, 0x55);
	405	udelay(1);
	406
	407	/* Write single word */
	408	out_8(base+0x555, 0xa0);
	409	udelay(1);
	410	out_8(base+i, datas[i]);
	411
	412	timeout = 0;
	413	do {
	414	if (++timeout > 1000000) {
	415	printk(KERN_ERR "nvram: AMD flash write timeout !\n");
	416	break;
	417	}
	418	stat = in_8(base) ^ in_8(base);
	419	} while (stat != 0);
	420	if (stat != 0)
	421	break;
	422	}
	423
	424	/* Reset */
	425	out_8(base, 0xf0);
	426	udelay(1);
	427
2d4b9712 AM	428	if (memcmp(base, datas, NVRAM_SIZE)) {
	429	printk(KERN_ERR "nvram: AMD flash write failed !\n");
	430	return -ENXIO;
	431	}
14cf11af PM	432	return 0;
	433	}
	434
	435	static void __init lookup_partitions(void)
	436	{
	437	u8 buffer[17];
	438	int i, offset;
	439	struct chrp_header* hdr;
	440
	441	if (pmac_newworld) {
	442	nvram_partitions[pmac_nvram_OF] = -1;
	443	nvram_partitions[pmac_nvram_XPRAM] = -1;
	444	nvram_partitions[pmac_nvram_NR] = -1;
	445	hdr = (struct chrp_header *)buffer;
	446
	447	offset = 0;
	448	buffer[16] = 0;
	449	do {
	450	for (i=0;i<16;i++)
35499c01	451	buffer[i] = ppc_md.nvram_read_val(offset+i);
14cf11af PM	452	if (!strcmp(hdr->name, "common"))
	453	nvram_partitions[pmac_nvram_OF] = offset + 0x10;
	454	if (!strcmp(hdr->name, "APL,MacOS75")) {
	455	nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
	456	nvram_partitions[pmac_nvram_NR] = offset + 0x110;
	457	}
	458	offset += (hdr->len * 0x10);
	459	} while(offset < NVRAM_SIZE);
	460	} else {
	461	nvram_partitions[pmac_nvram_OF] = 0x1800;
	462	nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
	463	nvram_partitions[pmac_nvram_NR] = 0x1400;
	464	}
	465	DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
	466	DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
	467	DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
	468	}
	469
	470	static void core99_nvram_sync(void)
	471	{
	472	struct core99_header* hdr99;
	473	unsigned long flags;
	474
	475	if (!is_core_99 \|\| !nvram_data \|\| !nvram_image)
	476	return;
	477
7d725bdc	478	raw_spin_lock_irqsave(&nv_lock, flags);
14cf11af PM	479	if (!memcmp(nvram_image, (u8)nvram_data + core99_bankNVRAM_SIZE,
	480	NVRAM_SIZE))
	481	goto bail;
	482
	483	DBG("Updating nvram...\n");
	484
	485	hdr99 = (struct core99_header*)nvram_image;
	486	hdr99->generation++;
	487	hdr99->hdr.signature = CORE99_SIGNATURE;
	488	hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
	489	hdr99->adler = core99_calc_adler(nvram_image);
	490	core99_bank = core99_bank ? 0 : 1;
	491	if (core99_erase_bank)
	492	if (core99_erase_bank(core99_bank)) {
	493	printk("nvram: Error erasing bank %d\n", core99_bank);
	494	goto bail;
	495	}
	496	if (core99_write_bank)
	497	if (core99_write_bank(core99_bank, nvram_image))
	498	printk("nvram: Error writing bank %d\n", core99_bank);
	499	bail:
7d725bdc	500	raw_spin_unlock_irqrestore(&nv_lock, flags);
14cf11af PM	501
	502	#ifdef DEBUG
	503	mdelay(2000);
	504	#endif
	505	}
	506
cc5d0189	507	static int __init core99_nvram_setup(struct device_node *dp, unsigned long addr)
35499c01 PM	508	{
	509	int i;
	510	u32 gen_bank0, gen_bank1;
	511
	512	if (nvram_naddrs < 1) {
	513	printk(KERN_ERR "nvram: no address\n");
	514	return -EINVAL;
	515	}
7e1c4e27	516	nvram_image = memblock_alloc(NVRAM_SIZE, SMP_CACHE_BYTES);
cc5d0189	517	nvram_data = ioremap(addr, NVRAM_SIZE*2);
35499c01 PM	518	nvram_naddrs = 1; /* Make sure we get the correct case */
	519
	520	DBG("nvram: Checking bank 0...\n");
	521
	522	gen_bank0 = core99_check((u8 *)nvram_data);
	523	gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
	524	core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
	525
	526	DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
	527	DBG("nvram: Active bank is: %d\n", core99_bank);
	528
	529	for (i=0; i<NVRAM_SIZE; i++)
	530	nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
	531
	532	ppc_md.nvram_read_val = core99_nvram_read_byte;
	533	ppc_md.nvram_write_val = core99_nvram_write_byte;
	534	ppc_md.nvram_read = core99_nvram_read;
	535	ppc_md.nvram_write = core99_nvram_write;
	536	ppc_md.nvram_size = core99_nvram_size;
	537	ppc_md.nvram_sync = core99_nvram_sync;
3d1229d6	538	ppc_md.machine_shutdown = core99_nvram_sync;
35499c01 PM	539	/*
	540	* Maybe we could be smarter here though making an exclusive list
	541	* of known flash chips is a bit nasty as older OF didn't provide us
	542	* with a useful "compatible" entry. A solution would be to really
	543	* identify the chip using flash id commands and base ourselves on
	544	* a list of known chips IDs
	545	*/
55b61fec	546	if (of_device_is_compatible(dp, "amd-0137")) {
35499c01 PM	547	core99_erase_bank = amd_erase_bank;
	548	core99_write_bank = amd_write_bank;
	549	} else {
	550	core99_erase_bank = sm_erase_bank;
	551	core99_write_bank = sm_write_bank;
	552	}
	553	return 0;
	554	}
	555
	556	int __init pmac_nvram_init(void)
14cf11af PM	557	{
14cf11af PM	558	struct device_node *dp;
cc5d0189 BH	559	struct resource r1, r2;
cc5d0189 BH	560	unsigned int s1 = 0, s2 = 0;
35499c01	561	int err = 0;
14cf11af PM	562
	563	nvram_naddrs = 0;
	564
cc5d0189	565	dp = of_find_node_by_name(NULL, "nvram");
14cf11af PM	566	if (dp == NULL) {
14cf11af PM	567	printk(KERN_ERR "Can't find NVRAM device\n");
35499c01	568	return -ENODEV;
14cf11af	569	}
cc5d0189 BH	570
	571	/* Try to obtain an address */
	572	if (of_address_to_resource(dp, 0, &r1) == 0) {
	573	nvram_naddrs = 1;
28f65c11	574	s1 = resource_size(&r1);
cc5d0189 BH	575	if (of_address_to_resource(dp, 1, &r2) == 0) {
cc5d0189 BH	576	nvram_naddrs = 2;
28f65c11	577	s2 = resource_size(&r2);
cc5d0189 BH	578	}
	579	}
	580
55b61fec	581	is_core_99 = of_device_is_compatible(dp, "nvram,flash");
cc5d0189 BH	582	if (is_core_99) {
	583	err = core99_nvram_setup(dp, r1.start);
	584	goto bail;
	585	}
	586
35499c01	587	#ifdef CONFIG_PPC32
e8222502	588	if (machine_is(chrp) && nvram_naddrs == 1) {
cc5d0189	589	nvram_data = ioremap(r1.start, s1);
14cf11af PM	590	nvram_mult = 1;
	591	ppc_md.nvram_read_val = direct_nvram_read_byte;
	592	ppc_md.nvram_write_val = direct_nvram_write_byte;
	593	} else if (nvram_naddrs == 1) {
cc5d0189 BH	594	nvram_data = ioremap(r1.start, s1);
cc5d0189 BH	595	nvram_mult = (s1 + NVRAM_SIZE - 1) / NVRAM_SIZE;
14cf11af PM	596	ppc_md.nvram_read_val = direct_nvram_read_byte;
	597	ppc_md.nvram_write_val = direct_nvram_write_byte;
	598	} else if (nvram_naddrs == 2) {
cc5d0189 BH	599	nvram_addr = ioremap(r1.start, s1);
cc5d0189 BH	600	nvram_data = ioremap(r2.start, s2);
14cf11af PM	601	ppc_md.nvram_read_val = indirect_nvram_read_byte;
	602	ppc_md.nvram_write_val = indirect_nvram_write_byte;
	603	} else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
	604	#ifdef CONFIG_ADB_PMU
	605	nvram_naddrs = -1;
	606	ppc_md.nvram_read_val = pmu_nvram_read_byte;
	607	ppc_md.nvram_write_val = pmu_nvram_write_byte;
	608	#endif /* CONFIG_ADB_PMU */
cc5d0189	609	} else {
35499c01	610	printk(KERN_ERR "Incompatible type of NVRAM\n");
cc5d0189	611	err = -ENXIO;
14cf11af	612	}
cc5d0189 BH	613	#endif /* CONFIG_PPC32 */
	614	bail:
	615	of_node_put(dp);
	616	if (err == 0)
	617	lookup_partitions();
35499c01	618	return err;
14cf11af PM	619	}
	620
	621	int pmac_get_partition(int partition)
	622	{
	623	return nvram_partitions[partition];
	624	}
	625
	626	u8 pmac_xpram_read(int xpaddr)
	627	{
35499c01	628	int offset = pmac_get_partition(pmac_nvram_XPRAM);
14cf11af	629
35499c01	630	if (offset < 0 \|\| xpaddr < 0 \|\| xpaddr > 0x100)
14cf11af PM	631	return 0xff;
	632
	633	return ppc_md.nvram_read_val(xpaddr + offset);
	634	}
	635
	636	void pmac_xpram_write(int xpaddr, u8 data)
	637	{
35499c01	638	int offset = pmac_get_partition(pmac_nvram_XPRAM);
14cf11af	639
35499c01	640	if (offset < 0 \|\| xpaddr < 0 \|\| xpaddr > 0x100)
14cf11af PM	641	return;
	642
	643	ppc_md.nvram_write_val(xpaddr + offset, data);
	644	}
	645
	646	EXPORT_SYMBOL(pmac_get_partition);
	647	EXPORT_SYMBOL(pmac_xpram_read);
	648	EXPORT_SYMBOL(pmac_xpram_write);