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45051539 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
31c56d82 | 2 | /* |
f724bf77 | 3 | * Copyright (C) 2005-2008, PA Semi, Inc |
31c56d82 OJ |
4 | * |
5 | * Maintained by: Olof Johansson <olof@lixom.net> | |
31c56d82 OJ |
6 | */ |
7 | ||
8 | #undef DEBUG | |
9 | ||
beacc6da | 10 | #include <linux/memblock.h> |
31c56d82 OJ |
11 | #include <linux/types.h> |
12 | #include <linux/spinlock.h> | |
13 | #include <linux/pci.h> | |
14 | #include <asm/iommu.h> | |
15 | #include <asm/machdep.h> | |
af289e80 | 16 | #include <asm/firmware.h> |
31c56d82 | 17 | |
d28a0d94 DA |
18 | #include "pasemi.h" |
19 | ||
31c56d82 OJ |
20 | #define IOBMAP_PAGE_SHIFT 12 |
21 | #define IOBMAP_PAGE_SIZE (1 << IOBMAP_PAGE_SHIFT) | |
22 | #define IOBMAP_PAGE_MASK (IOBMAP_PAGE_SIZE - 1) | |
23 | ||
31c56d82 OJ |
24 | #define IOB_BASE 0xe0000000 |
25 | #define IOB_SIZE 0x3000 | |
26 | /* Configuration registers */ | |
f724bf77 OJ |
27 | #define IOBCAP_REG 0x40 |
28 | #define IOBCOM_REG 0x100 | |
31c56d82 OJ |
29 | /* Enable IOB address translation */ |
30 | #define IOBCOM_ATEN 0x00000100 | |
31 | ||
32 | /* Address decode configuration register */ | |
f724bf77 | 33 | #define IOB_AD_REG 0x14c |
31c56d82 OJ |
34 | /* IOBCOM_AD_REG fields */ |
35 | #define IOB_AD_VGPRT 0x00000e00 | |
36 | #define IOB_AD_VGAEN 0x00000100 | |
37 | /* Direct mapping settings */ | |
38 | #define IOB_AD_MPSEL_MASK 0x00000030 | |
39 | #define IOB_AD_MPSEL_B38 0x00000000 | |
40 | #define IOB_AD_MPSEL_B40 0x00000010 | |
41 | #define IOB_AD_MPSEL_B42 0x00000020 | |
42 | /* Translation window size / enable */ | |
43 | #define IOB_AD_TRNG_MASK 0x00000003 | |
44 | #define IOB_AD_TRNG_256M 0x00000000 | |
45 | #define IOB_AD_TRNG_2G 0x00000001 | |
46 | #define IOB_AD_TRNG_128G 0x00000003 | |
47 | ||
f724bf77 | 48 | #define IOB_TABLEBASE_REG 0x154 |
31c56d82 OJ |
49 | |
50 | /* Base of the 64 4-byte L1 registers */ | |
f724bf77 | 51 | #define IOB_XLT_L1_REGBASE 0x2b00 |
31c56d82 OJ |
52 | |
53 | /* Register to invalidate TLB entries */ | |
f724bf77 | 54 | #define IOB_AT_INVAL_TLB_REG 0x2d00 |
31c56d82 OJ |
55 | |
56 | /* The top two bits of the level 1 entry contains valid and type flags */ | |
57 | #define IOBMAP_L1E_V 0x40000000 | |
58 | #define IOBMAP_L1E_V_B 0x80000000 | |
59 | ||
60 | /* For big page entries, the bottom two bits contains flags */ | |
61 | #define IOBMAP_L1E_BIG_CACHED 0x00000002 | |
62 | #define IOBMAP_L1E_BIG_PRIORITY 0x00000001 | |
63 | ||
64 | /* For regular level 2 entries, top 2 bits contain valid and cache flags */ | |
65 | #define IOBMAP_L2E_V 0x80000000 | |
66 | #define IOBMAP_L2E_V_CACHED 0xc0000000 | |
67 | ||
f724bf77 | 68 | static void __iomem *iob; |
31c56d82 OJ |
69 | static u32 iob_l1_emptyval; |
70 | static u32 iob_l2_emptyval; | |
71 | static u32 *iob_l2_base; | |
72 | ||
73 | static struct iommu_table iommu_table_iobmap; | |
74 | static int iommu_table_iobmap_inited; | |
75 | ||
6490c490 | 76 | static int iobmap_build(struct iommu_table *tbl, long index, |
31c56d82 | 77 | long npages, unsigned long uaddr, |
4f3dd8a0 | 78 | enum dma_data_direction direction, |
00085f1e | 79 | unsigned long attrs) |
31c56d82 OJ |
80 | { |
81 | u32 *ip; | |
82 | u32 rpn; | |
83 | unsigned long bus_addr; | |
84 | ||
85 | pr_debug("iobmap: build at: %lx, %lx, addr: %lx\n", index, npages, uaddr); | |
86 | ||
dfa70f81 | 87 | bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT; |
31c56d82 | 88 | |
31c56d82 OJ |
89 | ip = ((u32 *)tbl->it_base) + index; |
90 | ||
91 | while (npages--) { | |
7db90c02 | 92 | rpn = __pa(uaddr) >> IOBMAP_PAGE_SHIFT; |
31c56d82 OJ |
93 | |
94 | *(ip++) = IOBMAP_L2E_V | rpn; | |
95 | /* invalidate tlb, can be optimized more */ | |
96 | out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14); | |
97 | ||
98 | uaddr += IOBMAP_PAGE_SIZE; | |
99 | bus_addr += IOBMAP_PAGE_SIZE; | |
100 | } | |
6490c490 | 101 | return 0; |
31c56d82 OJ |
102 | } |
103 | ||
104 | ||
105 | static void iobmap_free(struct iommu_table *tbl, long index, | |
106 | long npages) | |
107 | { | |
108 | u32 *ip; | |
109 | unsigned long bus_addr; | |
110 | ||
111 | pr_debug("iobmap: free at: %lx, %lx\n", index, npages); | |
112 | ||
dfa70f81 | 113 | bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT; |
31c56d82 | 114 | |
31c56d82 OJ |
115 | ip = ((u32 *)tbl->it_base) + index; |
116 | ||
117 | while (npages--) { | |
118 | *(ip++) = iob_l2_emptyval; | |
119 | /* invalidate tlb, can be optimized more */ | |
120 | out_le32(iob+IOB_AT_INVAL_TLB_REG, bus_addr >> 14); | |
121 | bus_addr += IOBMAP_PAGE_SIZE; | |
122 | } | |
123 | } | |
124 | ||
da004c36 AK |
125 | static struct iommu_table_ops iommu_table_iobmap_ops = { |
126 | .set = iobmap_build, | |
127 | .clear = iobmap_free | |
128 | }; | |
31c56d82 OJ |
129 | |
130 | static void iommu_table_iobmap_setup(void) | |
131 | { | |
132 | pr_debug(" -> %s\n", __func__); | |
133 | iommu_table_iobmap.it_busno = 0; | |
134 | iommu_table_iobmap.it_offset = 0; | |
3a553170 AP |
135 | iommu_table_iobmap.it_page_shift = IOBMAP_PAGE_SHIFT; |
136 | ||
31c56d82 | 137 | /* it_size is in number of entries */ |
3a553170 AP |
138 | iommu_table_iobmap.it_size = |
139 | 0x80000000 >> iommu_table_iobmap.it_page_shift; | |
31c56d82 OJ |
140 | |
141 | /* Initialize the common IOMMU code */ | |
142 | iommu_table_iobmap.it_base = (unsigned long)iob_l2_base; | |
143 | iommu_table_iobmap.it_index = 0; | |
144 | /* XXXOJN tune this to avoid IOB cache invals. | |
145 | * Should probably be 8 (64 bytes) | |
146 | */ | |
147 | iommu_table_iobmap.it_blocksize = 4; | |
da004c36 | 148 | iommu_table_iobmap.it_ops = &iommu_table_iobmap_ops; |
31c56d82 OJ |
149 | iommu_init_table(&iommu_table_iobmap, 0); |
150 | pr_debug(" <- %s\n", __func__); | |
151 | } | |
152 | ||
153 | ||
154 | ||
155 | static void pci_dma_bus_setup_pasemi(struct pci_bus *bus) | |
156 | { | |
31c56d82 OJ |
157 | pr_debug("pci_dma_bus_setup, bus %p, bus->self %p\n", bus, bus->self); |
158 | ||
159 | if (!iommu_table_iobmap_inited) { | |
160 | iommu_table_iobmap_inited = 1; | |
161 | iommu_table_iobmap_setup(); | |
162 | } | |
31c56d82 OJ |
163 | } |
164 | ||
165 | ||
166 | static void pci_dma_dev_setup_pasemi(struct pci_dev *dev) | |
167 | { | |
168 | pr_debug("pci_dma_dev_setup, dev %p (%s)\n", dev, pci_name(dev)); | |
169 | ||
af289e80 OJ |
170 | #if !defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE) |
171 | /* For non-LPAR environment, don't translate anything for the DMA | |
172 | * engine. The exception to this is if the user has enabled | |
173 | * CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE at build time. | |
31c56d82 | 174 | */ |
af289e80 | 175 | if (dev->vendor == 0x1959 && dev->device == 0xa007 && |
24af8cb8 | 176 | !firmware_has_feature(FW_FEATURE_LPAR)) { |
68005b67 | 177 | dev->dev.dma_ops = NULL; |
416f37d0 DS |
178 | /* |
179 | * Set the coherent DMA mask to prevent the iommu | |
180 | * being used unnecessarily | |
181 | */ | |
182 | dev->dev.coherent_dma_mask = DMA_BIT_MASK(44); | |
2da53b01 | 183 | return; |
24af8cb8 | 184 | } |
af289e80 OJ |
185 | #endif |
186 | ||
738ef42e | 187 | set_iommu_table_base(&dev->dev, &iommu_table_iobmap); |
31c56d82 OJ |
188 | } |
189 | ||
7c98bd72 | 190 | static int __init iob_init(struct device_node *dn) |
31c56d82 OJ |
191 | { |
192 | unsigned long tmp; | |
193 | u32 regword; | |
194 | int i; | |
195 | ||
196 | pr_debug(" -> %s\n", __func__); | |
197 | ||
388dc1c3 | 198 | /* For 2G space, 8x64 pages (2^21 bytes) is max total l2 size */ |
f806714f MR |
199 | iob_l2_base = memblock_alloc_try_nid_raw(1UL << 21, 1UL << 21, |
200 | MEMBLOCK_LOW_LIMIT, 0x80000000, | |
201 | NUMA_NO_NODE); | |
8a7f97b9 MR |
202 | if (!iob_l2_base) |
203 | panic("%s: Failed to allocate %lu bytes align=0x%lx max_addr=%x\n", | |
204 | __func__, 1UL << 21, 1UL << 21, 0x80000000); | |
388dc1c3 | 205 | |
e13606d7 | 206 | pr_info("IOBMAP L2 allocated at: %p\n", iob_l2_base); |
388dc1c3 | 207 | |
31c56d82 | 208 | /* Allocate a spare page to map all invalid IOTLB pages. */ |
9a8dd708 | 209 | tmp = memblock_phys_alloc(IOBMAP_PAGE_SIZE, IOBMAP_PAGE_SIZE); |
31c56d82 OJ |
210 | if (!tmp) |
211 | panic("IOBMAP: Cannot allocate spare page!"); | |
212 | /* Empty l1 is marked invalid */ | |
213 | iob_l1_emptyval = 0; | |
214 | /* Empty l2 is mapped to dummy page */ | |
215 | iob_l2_emptyval = IOBMAP_L2E_V | (tmp >> IOBMAP_PAGE_SHIFT); | |
216 | ||
217 | iob = ioremap(IOB_BASE, IOB_SIZE); | |
218 | if (!iob) | |
219 | panic("IOBMAP: Cannot map registers!"); | |
220 | ||
221 | /* setup direct mapping of the L1 entries */ | |
222 | for (i = 0; i < 64; i++) { | |
223 | /* Each L1 covers 32MB, i.e. 8K entries = 32K of ram */ | |
224 | regword = IOBMAP_L1E_V | (__pa(iob_l2_base + i*0x2000) >> 12); | |
f724bf77 | 225 | out_le32(iob+IOB_XLT_L1_REGBASE+i*4, regword); |
31c56d82 OJ |
226 | } |
227 | ||
228 | /* set 2GB translation window, based at 0 */ | |
229 | regword = in_le32(iob+IOB_AD_REG); | |
230 | regword &= ~IOB_AD_TRNG_MASK; | |
231 | regword |= IOB_AD_TRNG_2G; | |
232 | out_le32(iob+IOB_AD_REG, regword); | |
233 | ||
234 | /* Enable translation */ | |
235 | regword = in_le32(iob+IOBCOM_REG); | |
236 | regword |= IOBCOM_ATEN; | |
237 | out_le32(iob+IOBCOM_REG, regword); | |
238 | ||
239 | pr_debug(" <- %s\n", __func__); | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
244 | ||
245 | /* These are called very early. */ | |
750d1d1c | 246 | void __init iommu_init_early_pasemi(void) |
31c56d82 OJ |
247 | { |
248 | int iommu_off; | |
249 | ||
250 | #ifndef CONFIG_PPC_PASEMI_IOMMU | |
251 | iommu_off = 1; | |
252 | #else | |
253 | iommu_off = of_chosen && | |
e2eb6392 | 254 | of_get_property(of_chosen, "linux,iommu-off", NULL); |
31c56d82 | 255 | #endif |
2f9c9be2 | 256 | if (iommu_off) |
31c56d82 | 257 | return; |
31c56d82 OJ |
258 | |
259 | iob_init(NULL); | |
260 | ||
d28a0d94 DA |
261 | pasemi_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pasemi; |
262 | pasemi_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pasemi; | |
98747770 | 263 | set_pci_dma_ops(&dma_iommu_ops); |
31c56d82 | 264 | } |