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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
3 | * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu> | |
4 | * | |
1da177e4 LT |
5 | * Description: |
6 | * Architecture- / platform-specific boot-time initialization code for | |
7 | * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and | |
8 | * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek | |
9 | * <dan@net4x.com>. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
17 | #undef DEBUG | |
18 | ||
19 | #include <linux/config.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/threads.h> | |
22 | #include <linux/smp.h> | |
23 | #include <linux/param.h> | |
24 | #include <linux/string.h> | |
1da177e4 LT |
25 | #include <linux/initrd.h> |
26 | #include <linux/seq_file.h> | |
27 | #include <linux/kdev_t.h> | |
28 | #include <linux/major.h> | |
29 | #include <linux/root_dev.h> | |
bec7c458 | 30 | #include <linux/kernel.h> |
1da177e4 LT |
31 | |
32 | #include <asm/processor.h> | |
33 | #include <asm/machdep.h> | |
34 | #include <asm/page.h> | |
35 | #include <asm/mmu.h> | |
36 | #include <asm/pgtable.h> | |
37 | #include <asm/mmu_context.h> | |
38 | #include <asm/cputable.h> | |
39 | #include <asm/sections.h> | |
40 | #include <asm/iommu.h> | |
aed31351 | 41 | #include <asm/firmware.h> |
49b09853 | 42 | #include <asm/system.h> |
1da177e4 | 43 | #include <asm/time.h> |
1da177e4 LT |
44 | #include <asm/paca.h> |
45 | #include <asm/cache.h> | |
46 | #include <asm/sections.h> | |
0bc0ffd5 | 47 | #include <asm/abs_addr.h> |
15b17189 | 48 | #include <asm/iseries/hv_lp_config.h> |
c0a8d05c | 49 | #include <asm/iseries/hv_call_event.h> |
8021b8a7 | 50 | #include <asm/iseries/hv_call_xm.h> |
8875ccfb | 51 | #include <asm/iseries/it_lp_queue.h> |
bbc8b628 | 52 | #include <asm/iseries/mf.h> |
289f1c74 | 53 | #include <asm/iseries/it_exp_vpd_panel.h> |
e45423ea | 54 | #include <asm/iseries/hv_lp_event.h> |
c43a55ff | 55 | #include <asm/iseries/lpar_map.h> |
bf6a7112 | 56 | #include <asm/udbg.h> |
7d01c880 | 57 | #include <asm/irq.h> |
1da177e4 | 58 | |
f11b7bd8 | 59 | #include "naca.h" |
c8b84976 | 60 | #include "setup.h" |
b08567cb SR |
61 | #include "irq.h" |
62 | #include "vpd_areas.h" | |
63 | #include "processor_vpd.h" | |
64 | #include "main_store.h" | |
65 | #include "call_sm.h" | |
0e29bb1a | 66 | #include "call_hpt.h" |
c8b84976 | 67 | |
1da177e4 | 68 | #ifdef DEBUG |
bf6a7112 | 69 | #define DBG(fmt...) udbg_printf(fmt) |
1da177e4 LT |
70 | #else |
71 | #define DBG(fmt...) | |
72 | #endif | |
73 | ||
74 | /* Function Prototypes */ | |
799d6046 | 75 | static unsigned long build_iSeries_Memory_Map(void); |
143a1dec PM |
76 | static void iseries_shared_idle(void); |
77 | static void iseries_dedicated_idle(void); | |
145d01e4 | 78 | #ifdef CONFIG_PCI |
1da177e4 | 79 | extern void iSeries_pci_final_fixup(void); |
145d01e4 SR |
80 | #else |
81 | static void iSeries_pci_final_fixup(void) { } | |
82 | #endif | |
1da177e4 LT |
83 | |
84 | /* Global Variables */ | |
1da177e4 LT |
85 | int piranha_simulator; |
86 | ||
87 | extern int rd_size; /* Defined in drivers/block/rd.c */ | |
1da177e4 LT |
88 | extern unsigned long embedded_sysmap_start; |
89 | extern unsigned long embedded_sysmap_end; | |
90 | ||
91 | extern unsigned long iSeries_recal_tb; | |
92 | extern unsigned long iSeries_recal_titan; | |
93 | ||
bec7c458 SR |
94 | static unsigned long cmd_mem_limit; |
95 | ||
1da177e4 LT |
96 | struct MemoryBlock { |
97 | unsigned long absStart; | |
98 | unsigned long absEnd; | |
99 | unsigned long logicalStart; | |
100 | unsigned long logicalEnd; | |
101 | }; | |
102 | ||
103 | /* | |
104 | * Process the main store vpd to determine where the holes in memory are | |
105 | * and return the number of physical blocks and fill in the array of | |
106 | * block data. | |
107 | */ | |
108 | static unsigned long iSeries_process_Condor_mainstore_vpd( | |
109 | struct MemoryBlock *mb_array, unsigned long max_entries) | |
110 | { | |
111 | unsigned long holeFirstChunk, holeSizeChunks; | |
112 | unsigned long numMemoryBlocks = 1; | |
113 | struct IoHriMainStoreSegment4 *msVpd = | |
114 | (struct IoHriMainStoreSegment4 *)xMsVpd; | |
115 | unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr; | |
116 | unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr; | |
117 | unsigned long holeSize = holeEnd - holeStart; | |
118 | ||
119 | printk("Mainstore_VPD: Condor\n"); | |
120 | /* | |
121 | * Determine if absolute memory has any | |
122 | * holes so that we can interpret the | |
123 | * access map we get back from the hypervisor | |
124 | * correctly. | |
125 | */ | |
126 | mb_array[0].logicalStart = 0; | |
127 | mb_array[0].logicalEnd = 0x100000000; | |
128 | mb_array[0].absStart = 0; | |
129 | mb_array[0].absEnd = 0x100000000; | |
130 | ||
131 | if (holeSize) { | |
132 | numMemoryBlocks = 2; | |
133 | holeStart = holeStart & 0x000fffffffffffff; | |
134 | holeStart = addr_to_chunk(holeStart); | |
135 | holeFirstChunk = holeStart; | |
136 | holeSize = addr_to_chunk(holeSize); | |
137 | holeSizeChunks = holeSize; | |
138 | printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n", | |
139 | holeFirstChunk, holeSizeChunks ); | |
140 | mb_array[0].logicalEnd = holeFirstChunk; | |
141 | mb_array[0].absEnd = holeFirstChunk; | |
142 | mb_array[1].logicalStart = holeFirstChunk; | |
143 | mb_array[1].logicalEnd = 0x100000000 - holeSizeChunks; | |
144 | mb_array[1].absStart = holeFirstChunk + holeSizeChunks; | |
145 | mb_array[1].absEnd = 0x100000000; | |
146 | } | |
147 | return numMemoryBlocks; | |
148 | } | |
149 | ||
150 | #define MaxSegmentAreas 32 | |
151 | #define MaxSegmentAdrRangeBlocks 128 | |
152 | #define MaxAreaRangeBlocks 4 | |
153 | ||
154 | static unsigned long iSeries_process_Regatta_mainstore_vpd( | |
155 | struct MemoryBlock *mb_array, unsigned long max_entries) | |
156 | { | |
157 | struct IoHriMainStoreSegment5 *msVpdP = | |
158 | (struct IoHriMainStoreSegment5 *)xMsVpd; | |
159 | unsigned long numSegmentBlocks = 0; | |
160 | u32 existsBits = msVpdP->msAreaExists; | |
161 | unsigned long area_num; | |
162 | ||
163 | printk("Mainstore_VPD: Regatta\n"); | |
164 | ||
165 | for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) { | |
166 | unsigned long numAreaBlocks; | |
167 | struct IoHriMainStoreArea4 *currentArea; | |
168 | ||
169 | if (existsBits & 0x80000000) { | |
170 | unsigned long block_num; | |
171 | ||
172 | currentArea = &msVpdP->msAreaArray[area_num]; | |
173 | numAreaBlocks = currentArea->numAdrRangeBlocks; | |
174 | printk("ms_vpd: processing area %2ld blocks=%ld", | |
175 | area_num, numAreaBlocks); | |
176 | for (block_num = 0; block_num < numAreaBlocks; | |
177 | ++block_num ) { | |
178 | /* Process an address range block */ | |
179 | struct MemoryBlock tempBlock; | |
180 | unsigned long i; | |
181 | ||
182 | tempBlock.absStart = | |
183 | (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart; | |
184 | tempBlock.absEnd = | |
185 | (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd; | |
186 | tempBlock.logicalStart = 0; | |
187 | tempBlock.logicalEnd = 0; | |
188 | printk("\n block %ld absStart=%016lx absEnd=%016lx", | |
189 | block_num, tempBlock.absStart, | |
190 | tempBlock.absEnd); | |
191 | ||
192 | for (i = 0; i < numSegmentBlocks; ++i) { | |
193 | if (mb_array[i].absStart == | |
194 | tempBlock.absStart) | |
195 | break; | |
196 | } | |
197 | if (i == numSegmentBlocks) { | |
198 | if (numSegmentBlocks == max_entries) | |
199 | panic("iSeries_process_mainstore_vpd: too many memory blocks"); | |
200 | mb_array[numSegmentBlocks] = tempBlock; | |
201 | ++numSegmentBlocks; | |
202 | } else | |
203 | printk(" (duplicate)"); | |
204 | } | |
205 | printk("\n"); | |
206 | } | |
207 | existsBits <<= 1; | |
208 | } | |
209 | /* Now sort the blocks found into ascending sequence */ | |
210 | if (numSegmentBlocks > 1) { | |
211 | unsigned long m, n; | |
212 | ||
213 | for (m = 0; m < numSegmentBlocks - 1; ++m) { | |
214 | for (n = numSegmentBlocks - 1; m < n; --n) { | |
215 | if (mb_array[n].absStart < | |
216 | mb_array[n-1].absStart) { | |
217 | struct MemoryBlock tempBlock; | |
218 | ||
219 | tempBlock = mb_array[n]; | |
220 | mb_array[n] = mb_array[n-1]; | |
221 | mb_array[n-1] = tempBlock; | |
222 | } | |
223 | } | |
224 | } | |
225 | } | |
226 | /* | |
227 | * Assign "logical" addresses to each block. These | |
228 | * addresses correspond to the hypervisor "bitmap" space. | |
229 | * Convert all addresses into units of 256K chunks. | |
230 | */ | |
231 | { | |
232 | unsigned long i, nextBitmapAddress; | |
233 | ||
234 | printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks); | |
235 | nextBitmapAddress = 0; | |
236 | for (i = 0; i < numSegmentBlocks; ++i) { | |
237 | unsigned long length = mb_array[i].absEnd - | |
238 | mb_array[i].absStart; | |
239 | ||
240 | mb_array[i].logicalStart = nextBitmapAddress; | |
241 | mb_array[i].logicalEnd = nextBitmapAddress + length; | |
242 | nextBitmapAddress += length; | |
243 | printk(" Bitmap range: %016lx - %016lx\n" | |
244 | " Absolute range: %016lx - %016lx\n", | |
245 | mb_array[i].logicalStart, | |
246 | mb_array[i].logicalEnd, | |
247 | mb_array[i].absStart, mb_array[i].absEnd); | |
248 | mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart & | |
249 | 0x000fffffffffffff); | |
250 | mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd & | |
251 | 0x000fffffffffffff); | |
252 | mb_array[i].logicalStart = | |
253 | addr_to_chunk(mb_array[i].logicalStart); | |
254 | mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd); | |
255 | } | |
256 | } | |
257 | ||
258 | return numSegmentBlocks; | |
259 | } | |
260 | ||
261 | static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array, | |
262 | unsigned long max_entries) | |
263 | { | |
264 | unsigned long i; | |
265 | unsigned long mem_blocks = 0; | |
266 | ||
267 | if (cpu_has_feature(CPU_FTR_SLB)) | |
268 | mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array, | |
269 | max_entries); | |
270 | else | |
271 | mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array, | |
272 | max_entries); | |
273 | ||
274 | printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks); | |
275 | for (i = 0; i < mem_blocks; ++i) { | |
276 | printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n" | |
277 | " abs chunks %016lx - %016lx\n", | |
278 | i, mb_array[i].logicalStart, mb_array[i].logicalEnd, | |
279 | mb_array[i].absStart, mb_array[i].absEnd); | |
280 | } | |
281 | return mem_blocks; | |
282 | } | |
283 | ||
284 | static void __init iSeries_get_cmdline(void) | |
285 | { | |
286 | char *p, *q; | |
287 | ||
288 | /* copy the command line parameter from the primary VSP */ | |
289 | HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256, | |
290 | HvLpDma_Direction_RemoteToLocal); | |
291 | ||
292 | p = cmd_line; | |
293 | q = cmd_line + 255; | |
294 | while(p < q) { | |
295 | if (!*p || *p == '\n') | |
296 | break; | |
297 | ++p; | |
298 | } | |
299 | *p = 0; | |
300 | } | |
301 | ||
302 | static void __init iSeries_init_early(void) | |
303 | { | |
1da177e4 LT |
304 | DBG(" -> iSeries_init_early()\n"); |
305 | ||
ba293fff ME |
306 | ppc64_interrupt_controller = IC_ISERIES; |
307 | ||
1da177e4 LT |
308 | #if defined(CONFIG_BLK_DEV_INITRD) |
309 | /* | |
310 | * If the init RAM disk has been configured and there is | |
311 | * a non-zero starting address for it, set it up | |
312 | */ | |
313 | if (naca.xRamDisk) { | |
314 | initrd_start = (unsigned long)__va(naca.xRamDisk); | |
3c726f8d | 315 | initrd_end = initrd_start + naca.xRamDiskSize * HW_PAGE_SIZE; |
1da177e4 LT |
316 | initrd_below_start_ok = 1; // ramdisk in kernel space |
317 | ROOT_DEV = Root_RAM0; | |
3c726f8d BH |
318 | if (((rd_size * 1024) / HW_PAGE_SIZE) < naca.xRamDiskSize) |
319 | rd_size = (naca.xRamDiskSize * HW_PAGE_SIZE) / 1024; | |
1da177e4 LT |
320 | } else |
321 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
322 | { | |
323 | /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */ | |
324 | } | |
325 | ||
326 | iSeries_recal_tb = get_tb(); | |
327 | iSeries_recal_titan = HvCallXm_loadTod(); | |
328 | ||
1da177e4 LT |
329 | /* |
330 | * Initialize the hash table management pointers | |
331 | */ | |
332 | hpte_init_iSeries(); | |
333 | ||
334 | /* | |
335 | * Initialize the DMA/TCE management | |
336 | */ | |
337 | iommu_init_early_iSeries(); | |
338 | ||
1da177e4 LT |
339 | /* Initialize machine-dependency vectors */ |
340 | #ifdef CONFIG_SMP | |
341 | smp_init_iSeries(); | |
342 | #endif | |
343 | if (itLpNaca.xPirEnvironMode == 0) | |
344 | piranha_simulator = 1; | |
345 | ||
346 | /* Associate Lp Event Queue 0 with processor 0 */ | |
347 | HvCallEvent_setLpEventQueueInterruptProc(0, 0); | |
348 | ||
349 | mf_init(); | |
1da177e4 LT |
350 | |
351 | /* If we were passed an initrd, set the ROOT_DEV properly if the values | |
352 | * look sensible. If not, clear initrd reference. | |
353 | */ | |
354 | #ifdef CONFIG_BLK_DEV_INITRD | |
355 | if (initrd_start >= KERNELBASE && initrd_end >= KERNELBASE && | |
356 | initrd_end > initrd_start) | |
357 | ROOT_DEV = Root_RAM0; | |
358 | else | |
359 | initrd_start = initrd_end = 0; | |
360 | #endif /* CONFIG_BLK_DEV_INITRD */ | |
361 | ||
362 | DBG(" <- iSeries_init_early()\n"); | |
363 | } | |
364 | ||
56e97b71 | 365 | struct mschunks_map mschunks_map = { |
34c8f696 ME |
366 | /* XXX We don't use these, but Piranha might need them. */ |
367 | .chunk_size = MSCHUNKS_CHUNK_SIZE, | |
368 | .chunk_shift = MSCHUNKS_CHUNK_SHIFT, | |
369 | .chunk_mask = MSCHUNKS_OFFSET_MASK, | |
370 | }; | |
56e97b71 | 371 | EXPORT_SYMBOL(mschunks_map); |
34c8f696 | 372 | |
56e97b71 | 373 | void mschunks_alloc(unsigned long num_chunks) |
34c8f696 ME |
374 | { |
375 | klimit = _ALIGN(klimit, sizeof(u32)); | |
56e97b71 | 376 | mschunks_map.mapping = (u32 *)klimit; |
34c8f696 | 377 | klimit += num_chunks * sizeof(u32); |
56e97b71 | 378 | mschunks_map.num_chunks = num_chunks; |
34c8f696 ME |
379 | } |
380 | ||
1da177e4 LT |
381 | /* |
382 | * The iSeries may have very large memories ( > 128 GB ) and a partition | |
383 | * may get memory in "chunks" that may be anywhere in the 2**52 real | |
384 | * address space. The chunks are 256K in size. To map this to the | |
385 | * memory model Linux expects, the AS/400 specific code builds a | |
386 | * translation table to translate what Linux thinks are "physical" | |
387 | * addresses to the actual real addresses. This allows us to make | |
388 | * it appear to Linux that we have contiguous memory starting at | |
389 | * physical address zero while in fact this could be far from the truth. | |
390 | * To avoid confusion, I'll let the words physical and/or real address | |
391 | * apply to the Linux addresses while I'll use "absolute address" to | |
392 | * refer to the actual hardware real address. | |
393 | * | |
394 | * build_iSeries_Memory_Map gets information from the Hypervisor and | |
395 | * looks at the Main Store VPD to determine the absolute addresses | |
396 | * of the memory that has been assigned to our partition and builds | |
397 | * a table used to translate Linux's physical addresses to these | |
398 | * absolute addresses. Absolute addresses are needed when | |
399 | * communicating with the hypervisor (e.g. to build HPT entries) | |
799d6046 PM |
400 | * |
401 | * Returns the physical memory size | |
1da177e4 LT |
402 | */ |
403 | ||
799d6046 | 404 | static unsigned long __init build_iSeries_Memory_Map(void) |
1da177e4 LT |
405 | { |
406 | u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize; | |
407 | u32 nextPhysChunk; | |
408 | u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages; | |
1da177e4 LT |
409 | u32 totalChunks,moreChunks; |
410 | u32 currChunk, thisChunk, absChunk; | |
411 | u32 currDword; | |
412 | u32 chunkBit; | |
413 | u64 map; | |
414 | struct MemoryBlock mb[32]; | |
415 | unsigned long numMemoryBlocks, curBlock; | |
416 | ||
417 | /* Chunk size on iSeries is 256K bytes */ | |
418 | totalChunks = (u32)HvLpConfig_getMsChunks(); | |
56e97b71 | 419 | mschunks_alloc(totalChunks); |
1da177e4 LT |
420 | |
421 | /* | |
422 | * Get absolute address of our load area | |
423 | * and map it to physical address 0 | |
424 | * This guarantees that the loadarea ends up at physical 0 | |
425 | * otherwise, it might not be returned by PLIC as the first | |
426 | * chunks | |
427 | */ | |
428 | ||
429 | loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr); | |
430 | loadAreaSize = itLpNaca.xLoadAreaChunks; | |
431 | ||
432 | /* | |
433 | * Only add the pages already mapped here. | |
434 | * Otherwise we might add the hpt pages | |
435 | * The rest of the pages of the load area | |
436 | * aren't in the HPT yet and can still | |
437 | * be assigned an arbitrary physical address | |
438 | */ | |
439 | if ((loadAreaSize * 64) > HvPagesToMap) | |
440 | loadAreaSize = HvPagesToMap / 64; | |
441 | ||
442 | loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1; | |
443 | ||
444 | /* | |
445 | * TODO Do we need to do something if the HPT is in the 64MB load area? | |
446 | * This would be required if the itLpNaca.xLoadAreaChunks includes | |
447 | * the HPT size | |
448 | */ | |
449 | ||
450 | printk("Mapping load area - physical addr = 0000000000000000\n" | |
451 | " absolute addr = %016lx\n", | |
452 | chunk_to_addr(loadAreaFirstChunk)); | |
453 | printk("Load area size %dK\n", loadAreaSize * 256); | |
454 | ||
455 | for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk) | |
56e97b71 | 456 | mschunks_map.mapping[nextPhysChunk] = |
1da177e4 LT |
457 | loadAreaFirstChunk + nextPhysChunk; |
458 | ||
459 | /* | |
460 | * Get absolute address of our HPT and remember it so | |
461 | * we won't map it to any physical address | |
462 | */ | |
463 | hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress()); | |
464 | hptSizePages = (u32)HvCallHpt_getHptPages(); | |
3c726f8d BH |
465 | hptSizeChunks = hptSizePages >> |
466 | (MSCHUNKS_CHUNK_SHIFT - HW_PAGE_SHIFT); | |
1da177e4 LT |
467 | hptLastChunk = hptFirstChunk + hptSizeChunks - 1; |
468 | ||
469 | printk("HPT absolute addr = %016lx, size = %dK\n", | |
470 | chunk_to_addr(hptFirstChunk), hptSizeChunks * 256); | |
471 | ||
1da177e4 LT |
472 | /* |
473 | * Determine if absolute memory has any | |
474 | * holes so that we can interpret the | |
475 | * access map we get back from the hypervisor | |
476 | * correctly. | |
477 | */ | |
478 | numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32); | |
479 | ||
480 | /* | |
481 | * Process the main store access map from the hypervisor | |
482 | * to build up our physical -> absolute translation table | |
483 | */ | |
484 | curBlock = 0; | |
485 | currChunk = 0; | |
486 | currDword = 0; | |
487 | moreChunks = totalChunks; | |
488 | ||
489 | while (moreChunks) { | |
490 | map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex, | |
491 | currDword); | |
492 | thisChunk = currChunk; | |
493 | while (map) { | |
494 | chunkBit = map >> 63; | |
495 | map <<= 1; | |
496 | if (chunkBit) { | |
497 | --moreChunks; | |
498 | while (thisChunk >= mb[curBlock].logicalEnd) { | |
499 | ++curBlock; | |
500 | if (curBlock >= numMemoryBlocks) | |
501 | panic("out of memory blocks"); | |
502 | } | |
503 | if (thisChunk < mb[curBlock].logicalStart) | |
504 | panic("memory block error"); | |
505 | ||
506 | absChunk = mb[curBlock].absStart + | |
507 | (thisChunk - mb[curBlock].logicalStart); | |
508 | if (((absChunk < hptFirstChunk) || | |
509 | (absChunk > hptLastChunk)) && | |
510 | ((absChunk < loadAreaFirstChunk) || | |
511 | (absChunk > loadAreaLastChunk))) { | |
56e97b71 ME |
512 | mschunks_map.mapping[nextPhysChunk] = |
513 | absChunk; | |
1da177e4 LT |
514 | ++nextPhysChunk; |
515 | } | |
516 | } | |
517 | ++thisChunk; | |
518 | } | |
519 | ++currDword; | |
520 | currChunk += 64; | |
521 | } | |
522 | ||
523 | /* | |
524 | * main store size (in chunks) is | |
525 | * totalChunks - hptSizeChunks | |
526 | * which should be equal to | |
527 | * nextPhysChunk | |
528 | */ | |
799d6046 | 529 | return chunk_to_addr(nextPhysChunk); |
1da177e4 LT |
530 | } |
531 | ||
1da177e4 LT |
532 | /* |
533 | * Document me. | |
534 | */ | |
535 | static void __init iSeries_setup_arch(void) | |
536 | { | |
3356bb9f | 537 | if (get_lppaca()->shared_proc) { |
9f497581 ME |
538 | ppc_md.idle_loop = iseries_shared_idle; |
539 | printk(KERN_INFO "Using shared processor idle loop\n"); | |
540 | } else { | |
541 | ppc_md.idle_loop = iseries_dedicated_idle; | |
542 | printk(KERN_INFO "Using dedicated idle loop\n"); | |
543 | } | |
544 | ||
1da177e4 | 545 | /* Setup the Lp Event Queue */ |
512d31d6 | 546 | setup_hvlpevent_queue(); |
1da177e4 | 547 | |
1da177e4 LT |
548 | printk("Max logical processors = %d\n", |
549 | itVpdAreas.xSlicMaxLogicalProcs); | |
550 | printk("Max physical processors = %d\n", | |
551 | itVpdAreas.xSlicMaxPhysicalProcs); | |
1da177e4 LT |
552 | } |
553 | ||
d8699e65 | 554 | static void iSeries_show_cpuinfo(struct seq_file *m) |
1da177e4 LT |
555 | { |
556 | seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n"); | |
557 | } | |
558 | ||
1da177e4 LT |
559 | static void __init iSeries_progress(char * st, unsigned short code) |
560 | { | |
561 | printk("Progress: [%04x] - %s\n", (unsigned)code, st); | |
260de22f | 562 | mf_display_progress(code); |
1da177e4 LT |
563 | } |
564 | ||
565 | static void __init iSeries_fixup_klimit(void) | |
566 | { | |
567 | /* | |
568 | * Change klimit to take into account any ram disk | |
569 | * that may be included | |
570 | */ | |
571 | if (naca.xRamDisk) | |
572 | klimit = KERNELBASE + (u64)naca.xRamDisk + | |
3c726f8d | 573 | (naca.xRamDiskSize * HW_PAGE_SIZE); |
1da177e4 LT |
574 | else { |
575 | /* | |
576 | * No ram disk was included - check and see if there | |
577 | * was an embedded system map. Change klimit to take | |
578 | * into account any embedded system map | |
579 | */ | |
580 | if (embedded_sysmap_end) | |
581 | klimit = KERNELBASE + ((embedded_sysmap_end + 4095) & | |
582 | 0xfffffffffffff000); | |
583 | } | |
584 | } | |
585 | ||
586 | static int __init iSeries_src_init(void) | |
587 | { | |
588 | /* clear the progress line */ | |
589 | ppc_md.progress(" ", 0xffff); | |
590 | return 0; | |
591 | } | |
592 | ||
593 | late_initcall(iSeries_src_init); | |
594 | ||
d200903e ME |
595 | static inline void process_iSeries_events(void) |
596 | { | |
597 | asm volatile ("li 0,0x5555; sc" : : : "r0", "r3"); | |
598 | } | |
599 | ||
600 | static void yield_shared_processor(void) | |
601 | { | |
602 | unsigned long tb; | |
d200903e ME |
603 | |
604 | HvCall_setEnabledInterrupts(HvCall_MaskIPI | | |
605 | HvCall_MaskLpEvent | | |
606 | HvCall_MaskLpProd | | |
607 | HvCall_MaskTimeout); | |
608 | ||
609 | tb = get_tb(); | |
610 | /* Compute future tb value when yield should expire */ | |
611 | HvCall_yieldProcessor(HvCall_YieldTimed, tb+tb_ticks_per_jiffy); | |
612 | ||
d200903e ME |
613 | /* |
614 | * The decrementer stops during the yield. Force a fake decrementer | |
615 | * here and let the timer_interrupt code sort out the actual time. | |
616 | */ | |
3356bb9f | 617 | get_lppaca()->int_dword.fields.decr_int = 1; |
cb2c9b27 | 618 | ppc64_runlatch_on(); |
d200903e ME |
619 | process_iSeries_events(); |
620 | } | |
621 | ||
143a1dec | 622 | static void iseries_shared_idle(void) |
d200903e | 623 | { |
3c57bb9f AB |
624 | while (1) { |
625 | while (!need_resched() && !hvlpevent_is_pending()) { | |
626 | local_irq_disable(); | |
627 | ppc64_runlatch_off(); | |
628 | ||
629 | /* Recheck with irqs off */ | |
630 | if (!need_resched() && !hvlpevent_is_pending()) | |
631 | yield_shared_processor(); | |
d200903e | 632 | |
3c57bb9f AB |
633 | HMT_medium(); |
634 | local_irq_enable(); | |
635 | } | |
636 | ||
637 | ppc64_runlatch_on(); | |
d200903e | 638 | |
3c57bb9f AB |
639 | if (hvlpevent_is_pending()) |
640 | process_iSeries_events(); | |
641 | ||
5bfb5d69 | 642 | preempt_enable_no_resched(); |
3c57bb9f | 643 | schedule(); |
5bfb5d69 | 644 | preempt_disable(); |
3c57bb9f | 645 | } |
3c57bb9f AB |
646 | } |
647 | ||
143a1dec | 648 | static void iseries_dedicated_idle(void) |
3c57bb9f | 649 | { |
64c7c8f8 | 650 | set_thread_flag(TIF_POLLING_NRFLAG); |
d200903e ME |
651 | |
652 | while (1) { | |
64c7c8f8 | 653 | if (!need_resched()) { |
3c57bb9f AB |
654 | while (!need_resched()) { |
655 | ppc64_runlatch_off(); | |
656 | HMT_low(); | |
657 | ||
658 | if (hvlpevent_is_pending()) { | |
d200903e | 659 | HMT_medium(); |
3c57bb9f AB |
660 | ppc64_runlatch_on(); |
661 | process_iSeries_events(); | |
d200903e | 662 | } |
d200903e | 663 | } |
3c57bb9f AB |
664 | |
665 | HMT_medium(); | |
d200903e ME |
666 | } |
667 | ||
668 | ppc64_runlatch_on(); | |
5bfb5d69 | 669 | preempt_enable_no_resched(); |
d200903e | 670 | schedule(); |
5bfb5d69 | 671 | preempt_disable(); |
d200903e | 672 | } |
d200903e ME |
673 | } |
674 | ||
145d01e4 SR |
675 | #ifndef CONFIG_PCI |
676 | void __init iSeries_init_IRQ(void) { } | |
677 | #endif | |
678 | ||
e8222502 | 679 | static int __init iseries_probe(void) |
4762713a | 680 | { |
e8222502 BH |
681 | unsigned long root = of_get_flat_dt_root(); |
682 | if (!of_flat_dt_is_compatible(root, "IBM,iSeries")) | |
57cfb814 ME |
683 | return 0; |
684 | ||
d0160bf0 ME |
685 | powerpc_firmware_features |= FW_FEATURE_ISERIES; |
686 | powerpc_firmware_features |= FW_FEATURE_LPAR; | |
57cfb814 | 687 | |
7d01c880 SR |
688 | /* |
689 | * The Hypervisor only allows us up to 256 interrupt | |
690 | * sources (the irq number is passed in a u8). | |
691 | */ | |
692 | virt_irq_max = 255; | |
693 | ||
57cfb814 | 694 | return 1; |
4762713a ME |
695 | } |
696 | ||
e8222502 BH |
697 | define_machine(iseries) { |
698 | .name = "iSeries", | |
9f497581 | 699 | .setup_arch = iSeries_setup_arch, |
d8699e65 | 700 | .show_cpuinfo = iSeries_show_cpuinfo, |
9f497581 ME |
701 | .init_IRQ = iSeries_init_IRQ, |
702 | .get_irq = iSeries_get_irq, | |
703 | .init_early = iSeries_init_early, | |
704 | .pcibios_fixup = iSeries_pci_final_fixup, | |
a9ea2101 ME |
705 | .restart = mf_reboot, |
706 | .power_off = mf_power_off, | |
707 | .halt = mf_power_off, | |
9f497581 ME |
708 | .get_boot_time = iSeries_get_boot_time, |
709 | .set_rtc_time = iSeries_set_rtc_time, | |
710 | .get_rtc_time = iSeries_get_rtc_time, | |
95b29380 | 711 | .calibrate_decr = generic_calibrate_decr, |
9f497581 | 712 | .progress = iSeries_progress, |
4762713a | 713 | .probe = iseries_probe, |
9f497581 ME |
714 | /* XXX Implement enable_pmcs for iSeries */ |
715 | }; | |
716 | ||
c0a59491 ME |
717 | struct blob { |
718 | unsigned char data[PAGE_SIZE]; | |
719 | unsigned long next; | |
720 | }; | |
721 | ||
722 | struct iseries_flat_dt { | |
723 | struct boot_param_header header; | |
724 | u64 reserve_map[2]; | |
725 | struct blob dt; | |
726 | struct blob strings; | |
727 | }; | |
728 | ||
729 | struct iseries_flat_dt iseries_dt; | |
730 | ||
731 | void dt_init(struct iseries_flat_dt *dt) | |
732 | { | |
733 | dt->header.off_mem_rsvmap = | |
734 | offsetof(struct iseries_flat_dt, reserve_map); | |
735 | dt->header.off_dt_struct = offsetof(struct iseries_flat_dt, dt); | |
736 | dt->header.off_dt_strings = offsetof(struct iseries_flat_dt, strings); | |
737 | dt->header.totalsize = sizeof(struct iseries_flat_dt); | |
738 | dt->header.dt_strings_size = sizeof(struct blob); | |
739 | ||
740 | /* There is no notion of hardware cpu id on iSeries */ | |
741 | dt->header.boot_cpuid_phys = smp_processor_id(); | |
742 | ||
743 | dt->dt.next = (unsigned long)&dt->dt.data; | |
744 | dt->strings.next = (unsigned long)&dt->strings.data; | |
745 | ||
746 | dt->header.magic = OF_DT_HEADER; | |
747 | dt->header.version = 0x10; | |
748 | dt->header.last_comp_version = 0x10; | |
749 | ||
750 | dt->reserve_map[0] = 0; | |
751 | dt->reserve_map[1] = 0; | |
752 | } | |
753 | ||
754 | void dt_check_blob(struct blob *b) | |
755 | { | |
756 | if (b->next >= (unsigned long)&b->next) { | |
757 | DBG("Ran out of space in flat device tree blob!\n"); | |
758 | BUG(); | |
759 | } | |
760 | } | |
761 | ||
762 | void dt_push_u32(struct iseries_flat_dt *dt, u32 value) | |
763 | { | |
764 | *((u32*)dt->dt.next) = value; | |
765 | dt->dt.next += sizeof(u32); | |
766 | ||
767 | dt_check_blob(&dt->dt); | |
768 | } | |
769 | ||
770 | void dt_push_u64(struct iseries_flat_dt *dt, u64 value) | |
771 | { | |
772 | *((u64*)dt->dt.next) = value; | |
773 | dt->dt.next += sizeof(u64); | |
774 | ||
775 | dt_check_blob(&dt->dt); | |
776 | } | |
777 | ||
778 | unsigned long dt_push_bytes(struct blob *blob, char *data, int len) | |
779 | { | |
780 | unsigned long start = blob->next - (unsigned long)blob->data; | |
781 | ||
782 | memcpy((char *)blob->next, data, len); | |
783 | blob->next = _ALIGN(blob->next + len, 4); | |
784 | ||
785 | dt_check_blob(blob); | |
786 | ||
787 | return start; | |
788 | } | |
789 | ||
790 | void dt_start_node(struct iseries_flat_dt *dt, char *name) | |
791 | { | |
792 | dt_push_u32(dt, OF_DT_BEGIN_NODE); | |
793 | dt_push_bytes(&dt->dt, name, strlen(name) + 1); | |
794 | } | |
795 | ||
796 | #define dt_end_node(dt) dt_push_u32(dt, OF_DT_END_NODE) | |
797 | ||
798 | void dt_prop(struct iseries_flat_dt *dt, char *name, char *data, int len) | |
799 | { | |
800 | unsigned long offset; | |
801 | ||
802 | dt_push_u32(dt, OF_DT_PROP); | |
803 | ||
804 | /* Length of the data */ | |
805 | dt_push_u32(dt, len); | |
806 | ||
807 | /* Put the property name in the string blob. */ | |
808 | offset = dt_push_bytes(&dt->strings, name, strlen(name) + 1); | |
809 | ||
810 | /* The offset of the properties name in the string blob. */ | |
811 | dt_push_u32(dt, (u32)offset); | |
812 | ||
813 | /* The actual data. */ | |
814 | dt_push_bytes(&dt->dt, data, len); | |
815 | } | |
816 | ||
817 | void dt_prop_str(struct iseries_flat_dt *dt, char *name, char *data) | |
818 | { | |
819 | dt_prop(dt, name, data, strlen(data) + 1); /* + 1 for NULL */ | |
820 | } | |
821 | ||
822 | void dt_prop_u32(struct iseries_flat_dt *dt, char *name, u32 data) | |
823 | { | |
824 | dt_prop(dt, name, (char *)&data, sizeof(u32)); | |
825 | } | |
826 | ||
827 | void dt_prop_u64(struct iseries_flat_dt *dt, char *name, u64 data) | |
828 | { | |
829 | dt_prop(dt, name, (char *)&data, sizeof(u64)); | |
830 | } | |
831 | ||
832 | void dt_prop_u64_list(struct iseries_flat_dt *dt, char *name, u64 *data, int n) | |
833 | { | |
834 | dt_prop(dt, name, (char *)data, sizeof(u64) * n); | |
835 | } | |
836 | ||
7eb5476f ME |
837 | void dt_prop_u32_list(struct iseries_flat_dt *dt, char *name, u32 *data, int n) |
838 | { | |
839 | dt_prop(dt, name, (char *)data, sizeof(u32) * n); | |
840 | } | |
841 | ||
c0a59491 ME |
842 | void dt_prop_empty(struct iseries_flat_dt *dt, char *name) |
843 | { | |
844 | dt_prop(dt, name, NULL, 0); | |
845 | } | |
846 | ||
95b29380 ME |
847 | void dt_cpus(struct iseries_flat_dt *dt) |
848 | { | |
849 | unsigned char buf[32]; | |
850 | unsigned char *p; | |
851 | unsigned int i, index; | |
852 | struct IoHriProcessorVpd *d; | |
7eb5476f | 853 | u32 pft_size[2]; |
95b29380 ME |
854 | |
855 | /* yuck */ | |
856 | snprintf(buf, 32, "PowerPC,%s", cur_cpu_spec->cpu_name); | |
857 | p = strchr(buf, ' '); | |
858 | if (!p) p = buf + strlen(buf); | |
859 | ||
860 | dt_start_node(dt, "cpus"); | |
861 | dt_prop_u32(dt, "#address-cells", 1); | |
862 | dt_prop_u32(dt, "#size-cells", 0); | |
863 | ||
7eb5476f ME |
864 | pft_size[0] = 0; /* NUMA CEC cookie, 0 for non NUMA */ |
865 | pft_size[1] = __ilog2(HvCallHpt_getHptPages() * HW_PAGE_SIZE); | |
866 | ||
95b29380 | 867 | for (i = 0; i < NR_CPUS; i++) { |
3356bb9f | 868 | if (lppaca[i].dyn_proc_status >= 2) |
95b29380 ME |
869 | continue; |
870 | ||
871 | snprintf(p, 32 - (p - buf), "@%d", i); | |
872 | dt_start_node(dt, buf); | |
873 | ||
874 | dt_prop_str(dt, "device_type", "cpu"); | |
875 | ||
3356bb9f | 876 | index = lppaca[i].dyn_hv_phys_proc_index; |
95b29380 ME |
877 | d = &xIoHriProcessorVpd[index]; |
878 | ||
879 | dt_prop_u32(dt, "i-cache-size", d->xInstCacheSize * 1024); | |
880 | dt_prop_u32(dt, "i-cache-line-size", d->xInstCacheOperandSize); | |
881 | ||
882 | dt_prop_u32(dt, "d-cache-size", d->xDataL1CacheSizeKB * 1024); | |
883 | dt_prop_u32(dt, "d-cache-line-size", d->xDataCacheOperandSize); | |
884 | ||
885 | /* magic conversions to Hz copied from old code */ | |
886 | dt_prop_u32(dt, "clock-frequency", | |
887 | ((1UL << 34) * 1000000) / d->xProcFreq); | |
888 | dt_prop_u32(dt, "timebase-frequency", | |
889 | ((1UL << 32) * 1000000) / d->xTimeBaseFreq); | |
890 | ||
891 | dt_prop_u32(dt, "reg", i); | |
892 | ||
7eb5476f ME |
893 | dt_prop_u32_list(dt, "ibm,pft-size", pft_size, 2); |
894 | ||
95b29380 ME |
895 | dt_end_node(dt); |
896 | } | |
897 | ||
898 | dt_end_node(dt); | |
899 | } | |
900 | ||
289f1c74 ME |
901 | void dt_model(struct iseries_flat_dt *dt) |
902 | { | |
903 | char buf[16] = "IBM,"; | |
904 | ||
905 | /* "IBM," + mfgId[2:3] + systemSerial[1:5] */ | |
906 | strne2a(buf + 4, xItExtVpdPanel.mfgID + 2, 2); | |
907 | strne2a(buf + 6, xItExtVpdPanel.systemSerial + 1, 5); | |
908 | buf[11] = '\0'; | |
909 | dt_prop_str(dt, "system-id", buf); | |
910 | ||
911 | /* "IBM," + machineType[0:4] */ | |
912 | strne2a(buf + 4, xItExtVpdPanel.machineType, 4); | |
913 | buf[8] = '\0'; | |
914 | dt_prop_str(dt, "model", buf); | |
915 | ||
916 | dt_prop_str(dt, "compatible", "IBM,iSeries"); | |
917 | } | |
918 | ||
799d6046 | 919 | void build_flat_dt(struct iseries_flat_dt *dt, unsigned long phys_mem_size) |
c0a59491 | 920 | { |
3ab42407 ME |
921 | u64 tmp[2]; |
922 | ||
c0a59491 ME |
923 | dt_init(dt); |
924 | ||
925 | dt_start_node(dt, ""); | |
3ab42407 ME |
926 | |
927 | dt_prop_u32(dt, "#address-cells", 2); | |
928 | dt_prop_u32(dt, "#size-cells", 2); | |
289f1c74 | 929 | dt_model(dt); |
3ab42407 ME |
930 | |
931 | /* /memory */ | |
932 | dt_start_node(dt, "memory@0"); | |
933 | dt_prop_str(dt, "name", "memory"); | |
934 | dt_prop_str(dt, "device_type", "memory"); | |
935 | tmp[0] = 0; | |
799d6046 | 936 | tmp[1] = phys_mem_size; |
3ab42407 ME |
937 | dt_prop_u64_list(dt, "reg", tmp, 2); |
938 | dt_end_node(dt); | |
939 | ||
47db3603 ME |
940 | /* /chosen */ |
941 | dt_start_node(dt, "chosen"); | |
6c600ad8 | 942 | dt_prop_str(dt, "bootargs", cmd_line); |
bec7c458 SR |
943 | if (cmd_mem_limit) |
944 | dt_prop_u64(dt, "linux,memory-limit", cmd_mem_limit); | |
47db3603 ME |
945 | dt_end_node(dt); |
946 | ||
95b29380 ME |
947 | dt_cpus(dt); |
948 | ||
c0a59491 ME |
949 | dt_end_node(dt); |
950 | ||
951 | dt_push_u32(dt, OF_DT_END); | |
952 | } | |
953 | ||
4762713a | 954 | void * __init iSeries_early_setup(void) |
1da177e4 | 955 | { |
799d6046 PM |
956 | unsigned long phys_mem_size; |
957 | ||
1da177e4 | 958 | iSeries_fixup_klimit(); |
c0a59491 | 959 | |
4762713a ME |
960 | /* |
961 | * Initialize the table which translate Linux physical addresses to | |
962 | * AS/400 absolute addresses | |
963 | */ | |
799d6046 | 964 | phys_mem_size = build_iSeries_Memory_Map(); |
4762713a | 965 | |
bec7c458 SR |
966 | iSeries_get_cmdline(); |
967 | ||
968 | /* Save unparsed command line copy for /proc/cmdline */ | |
969 | strlcpy(saved_command_line, cmd_line, COMMAND_LINE_SIZE); | |
970 | ||
971 | /* Parse early parameters, in particular mem=x */ | |
972 | parse_early_param(); | |
973 | ||
799d6046 | 974 | build_flat_dt(&iseries_dt, phys_mem_size); |
4762713a ME |
975 | |
976 | return (void *) __pa(&iseries_dt); | |
1da177e4 | 977 | } |
bec7c458 SR |
978 | |
979 | /* | |
980 | * On iSeries we just parse the mem=X option from the command line. | |
981 | * On pSeries it's a bit more complicated, see prom_init_mem() | |
982 | */ | |
983 | static int __init early_parsemem(char *p) | |
984 | { | |
985 | if (p) | |
986 | cmd_mem_limit = ALIGN(memparse(p, &p), PAGE_SIZE); | |
987 | return 0; | |
988 | } | |
989 | early_param("mem", early_parsemem); | |
bf6a7112 ME |
990 | |
991 | static void hvputc(char c) | |
992 | { | |
993 | if (c == '\n') | |
994 | hvputc('\r'); | |
995 | ||
996 | HvCall_writeLogBuffer(&c, 1); | |
997 | } | |
998 | ||
999 | void __init udbg_init_iseries(void) | |
1000 | { | |
1001 | udbg_putc = hvputc; | |
1002 | } |