Commit | Line | Data |
---|---|---|
bbd0abda | 1 | /* |
bbd0abda PM |
2 | * Copyright (C) 1995 Linus Torvalds |
3 | * Adapted from 'alpha' version by Gary Thomas | |
4 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
5 | */ | |
6 | ||
7 | /* | |
8 | * bootup setup stuff.. | |
9 | */ | |
10 | ||
bbd0abda PM |
11 | #include <linux/errno.h> |
12 | #include <linux/sched.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/stddef.h> | |
16 | #include <linux/unistd.h> | |
17 | #include <linux/ptrace.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/user.h> | |
bbd0abda PM |
20 | #include <linux/tty.h> |
21 | #include <linux/major.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/reboot.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/pci.h> | |
63104eec | 26 | #include <linux/utsrelease.h> |
bbd0abda PM |
27 | #include <linux/adb.h> |
28 | #include <linux/module.h> | |
29 | #include <linux/delay.h> | |
bbd0abda PM |
30 | #include <linux/console.h> |
31 | #include <linux/seq_file.h> | |
32 | #include <linux/root_dev.h> | |
33 | #include <linux/initrd.h> | |
9618edab | 34 | #include <linux/timer.h> |
bbd0abda PM |
35 | |
36 | #include <asm/io.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/prom.h> | |
bbd0abda PM |
39 | #include <asm/pci-bridge.h> |
40 | #include <asm/dma.h> | |
41 | #include <asm/machdep.h> | |
42 | #include <asm/irq.h> | |
43 | #include <asm/hydra.h> | |
44 | #include <asm/sections.h> | |
45 | #include <asm/time.h> | |
bbd0abda PM |
46 | #include <asm/i8259.h> |
47 | #include <asm/mpic.h> | |
48 | #include <asm/rtas.h> | |
49 | #include <asm/xmon.h> | |
50 | ||
35e95e63 | 51 | #include "chrp.h" |
33d71d26 | 52 | #include "gg2.h" |
bbd0abda | 53 | |
bbd0abda | 54 | void rtas_indicator_progress(char *, unsigned short); |
bbd0abda PM |
55 | |
56 | int _chrp_type; | |
57 | EXPORT_SYMBOL(_chrp_type); | |
58 | ||
0ebfff14 | 59 | static struct mpic *chrp_mpic; |
bbd0abda | 60 | |
9618edab PM |
61 | /* Used for doing CHRP event-scans */ |
62 | DEFINE_PER_CPU(struct timer_list, heartbeat_timer); | |
63 | unsigned long event_scan_interval; | |
64 | ||
bbd0abda PM |
65 | extern unsigned long loops_per_jiffy; |
66 | ||
26c5032e | 67 | /* To be replaced by RTAS when available */ |
9340b0d3 | 68 | static unsigned int __iomem *briq_SPOR; |
26c5032e | 69 | |
bbd0abda PM |
70 | #ifdef CONFIG_SMP |
71 | extern struct smp_ops_t chrp_smp_ops; | |
72 | #endif | |
73 | ||
74 | static const char *gg2_memtypes[4] = { | |
75 | "FPM", "SDRAM", "EDO", "BEDO" | |
76 | }; | |
77 | static const char *gg2_cachesizes[4] = { | |
78 | "256 KB", "512 KB", "1 MB", "Reserved" | |
79 | }; | |
80 | static const char *gg2_cachetypes[4] = { | |
81 | "Asynchronous", "Reserved", "Flow-Through Synchronous", | |
82 | "Pipelined Synchronous" | |
83 | }; | |
84 | static const char *gg2_cachemodes[4] = { | |
85 | "Disabled", "Write-Through", "Copy-Back", "Transparent Mode" | |
86 | }; | |
87 | ||
26c5032e BH |
88 | static const char *chrp_names[] = { |
89 | "Unknown", | |
90 | "","","", | |
91 | "Motorola", | |
92 | "IBM or Longtrail", | |
93 | "Genesi Pegasos", | |
94 | "Total Impact Briq" | |
95 | }; | |
96 | ||
bbd0abda PM |
97 | void chrp_show_cpuinfo(struct seq_file *m) |
98 | { | |
99 | int i, sdramen; | |
100 | unsigned int t; | |
101 | struct device_node *root; | |
102 | const char *model = ""; | |
103 | ||
8c8dc322 | 104 | root = of_find_node_by_path("/"); |
bbd0abda | 105 | if (root) |
e2eb6392 | 106 | model = of_get_property(root, "model", NULL); |
bbd0abda PM |
107 | seq_printf(m, "machine\t\t: CHRP %s\n", model); |
108 | ||
109 | /* longtrail (goldengate) stuff */ | |
9ac71d00 | 110 | if (model && !strncmp(model, "IBM,LongTrail", 13)) { |
bbd0abda PM |
111 | /* VLSI VAS96011/12 `Golden Gate 2' */ |
112 | /* Memory banks */ | |
113 | sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL) | |
114 | >>31) & 1; | |
115 | for (i = 0; i < (sdramen ? 4 : 6); i++) { | |
116 | t = in_le32(gg2_pci_config_base+ | |
117 | GG2_PCI_DRAM_BANK0+ | |
118 | i*4); | |
119 | if (!(t & 1)) | |
120 | continue; | |
121 | switch ((t>>8) & 0x1f) { | |
122 | case 0x1f: | |
123 | model = "4 MB"; | |
124 | break; | |
125 | case 0x1e: | |
126 | model = "8 MB"; | |
127 | break; | |
128 | case 0x1c: | |
129 | model = "16 MB"; | |
130 | break; | |
131 | case 0x18: | |
132 | model = "32 MB"; | |
133 | break; | |
134 | case 0x10: | |
135 | model = "64 MB"; | |
136 | break; | |
137 | case 0x00: | |
138 | model = "128 MB"; | |
139 | break; | |
140 | default: | |
141 | model = "Reserved"; | |
142 | break; | |
143 | } | |
144 | seq_printf(m, "memory bank %d\t: %s %s\n", i, model, | |
145 | gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]); | |
146 | } | |
147 | /* L2 cache */ | |
148 | t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL); | |
149 | seq_printf(m, "board l2\t: %s %s (%s)\n", | |
150 | gg2_cachesizes[(t>>7) & 3], | |
151 | gg2_cachetypes[(t>>2) & 3], | |
152 | gg2_cachemodes[t & 3]); | |
153 | } | |
8c8dc322 | 154 | of_node_put(root); |
bbd0abda PM |
155 | } |
156 | ||
157 | /* | |
158 | * Fixes for the National Semiconductor PC78308VUL SuperI/O | |
159 | * | |
160 | * Some versions of Open Firmware incorrectly initialize the IRQ settings | |
161 | * for keyboard and mouse | |
162 | */ | |
163 | static inline void __init sio_write(u8 val, u8 index) | |
164 | { | |
165 | outb(index, 0x15c); | |
166 | outb(val, 0x15d); | |
167 | } | |
168 | ||
169 | static inline u8 __init sio_read(u8 index) | |
170 | { | |
171 | outb(index, 0x15c); | |
172 | return inb(0x15d); | |
173 | } | |
174 | ||
175 | static void __init sio_fixup_irq(const char *name, u8 device, u8 level, | |
176 | u8 type) | |
177 | { | |
178 | u8 level0, type0, active; | |
179 | ||
180 | /* select logical device */ | |
181 | sio_write(device, 0x07); | |
182 | active = sio_read(0x30); | |
183 | level0 = sio_read(0x70); | |
184 | type0 = sio_read(0x71); | |
185 | if (level0 != level || type0 != type || !active) { | |
186 | printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: " | |
187 | "remapping to level %d, type %d, active\n", | |
188 | name, level0, type0, !active ? "in" : "", level, type); | |
189 | sio_write(0x01, 0x30); | |
190 | sio_write(level, 0x70); | |
191 | sio_write(type, 0x71); | |
192 | } | |
193 | } | |
194 | ||
195 | static void __init sio_init(void) | |
196 | { | |
197 | struct device_node *root; | |
9ac71d00 | 198 | const char *model; |
bbd0abda | 199 | |
9ac71d00 CG |
200 | root = of_find_node_by_path("/"); |
201 | if (!root) | |
202 | return; | |
203 | ||
204 | model = of_get_property(root, "model", NULL); | |
205 | if (model && !strncmp(model, "IBM,LongTrail", 13)) { | |
bbd0abda PM |
206 | /* logical device 0 (KBC/Keyboard) */ |
207 | sio_fixup_irq("keyboard", 0, 1, 2); | |
208 | /* select logical device 1 (KBC/Mouse) */ | |
209 | sio_fixup_irq("mouse", 1, 12, 2); | |
210 | } | |
9ac71d00 | 211 | |
8c8dc322 | 212 | of_node_put(root); |
bbd0abda PM |
213 | } |
214 | ||
215 | ||
216 | static void __init pegasos_set_l2cr(void) | |
217 | { | |
218 | struct device_node *np; | |
219 | ||
220 | /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */ | |
221 | if (_chrp_type != _CHRP_Pegasos) | |
222 | return; | |
223 | ||
224 | /* Enable L2 cache if needed */ | |
1658ab66 | 225 | np = of_find_node_by_type(NULL, "cpu"); |
bbd0abda | 226 | if (np != NULL) { |
e2eb6392 | 227 | const unsigned int *l2cr = of_get_property(np, "l2cr", NULL); |
bbd0abda PM |
228 | if (l2cr == NULL) { |
229 | printk ("Pegasos l2cr : no cpu l2cr property found\n"); | |
1658ab66 | 230 | goto out; |
bbd0abda PM |
231 | } |
232 | if (!((*l2cr) & 0x80000000)) { | |
233 | printk ("Pegasos l2cr : L2 cache was not active, " | |
234 | "activating\n"); | |
235 | _set_L2CR(0); | |
236 | _set_L2CR((*l2cr) | 0x80000000); | |
237 | } | |
238 | } | |
1658ab66 SR |
239 | out: |
240 | of_node_put(np); | |
bbd0abda PM |
241 | } |
242 | ||
26c5032e BH |
243 | static void briq_restart(char *cmd) |
244 | { | |
245 | local_irq_disable(); | |
246 | if (briq_SPOR) | |
247 | out_be32(briq_SPOR, 0); | |
248 | for(;;); | |
249 | } | |
250 | ||
5bc97786 OH |
251 | /* |
252 | * Per default, input/output-device points to the keyboard/screen | |
253 | * If no card is installed, the built-in serial port is used as a fallback. | |
254 | * But unfortunately, the firmware does not connect /chosen/{stdin,stdout} | |
255 | * the the built-in serial node. Instead, a /failsafe node is created. | |
256 | */ | |
257 | static void chrp_init_early(void) | |
258 | { | |
259 | struct device_node *node; | |
260 | const char *property; | |
261 | ||
262 | if (strstr(cmd_line, "console=")) | |
263 | return; | |
264 | /* find the boot console from /chosen/stdout */ | |
265 | if (!of_chosen) | |
266 | return; | |
267 | node = of_find_node_by_path("/"); | |
268 | if (!node) | |
269 | return; | |
270 | property = of_get_property(node, "model", NULL); | |
271 | if (!property) | |
272 | goto out_put; | |
273 | if (strcmp(property, "Pegasos2")) | |
274 | goto out_put; | |
275 | /* this is a Pegasos2 */ | |
276 | property = of_get_property(of_chosen, "linux,stdout-path", NULL); | |
277 | if (!property) | |
278 | goto out_put; | |
279 | of_node_put(node); | |
280 | node = of_find_node_by_path(property); | |
281 | if (!node) | |
282 | return; | |
283 | property = of_get_property(node, "device_type", NULL); | |
284 | if (!property) | |
285 | goto out_put; | |
286 | if (strcmp(property, "serial")) | |
287 | goto out_put; | |
288 | /* | |
289 | * The 9pin connector is either /failsafe | |
290 | * or /pci@80000000/isa@C/serial@i2F8 | |
291 | * The optional graphics card has also type 'serial' in VGA mode. | |
292 | */ | |
293 | property = of_get_property(node, "name", NULL); | |
294 | if (!property) | |
295 | goto out_put; | |
296 | if (!strcmp(property, "failsafe") || !strcmp(property, "serial")) | |
297 | add_preferred_console("ttyS", 0, NULL); | |
298 | out_put: | |
299 | of_node_put(node); | |
300 | } | |
301 | ||
bbd0abda PM |
302 | void __init chrp_setup_arch(void) |
303 | { | |
8c8dc322 | 304 | struct device_node *root = of_find_node_by_path("/"); |
ae6b4101 | 305 | const char *machine = NULL; |
bbd0abda PM |
306 | |
307 | /* init to some ~sane value until calibrate_delay() runs */ | |
308 | loops_per_jiffy = 50000000/HZ; | |
309 | ||
310 | if (root) | |
e2eb6392 | 311 | machine = of_get_property(root, "model", NULL); |
bbd0abda PM |
312 | if (machine && strncmp(machine, "Pegasos", 7) == 0) { |
313 | _chrp_type = _CHRP_Pegasos; | |
314 | } else if (machine && strncmp(machine, "IBM", 3) == 0) { | |
315 | _chrp_type = _CHRP_IBM; | |
316 | } else if (machine && strncmp(machine, "MOT", 3) == 0) { | |
317 | _chrp_type = _CHRP_Motorola; | |
26c5032e BH |
318 | } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) { |
319 | _chrp_type = _CHRP_briq; | |
320 | /* Map the SPOR register on briq and change the restart hook */ | |
9340b0d3 | 321 | briq_SPOR = ioremap(0xff0000e8, 4); |
26c5032e | 322 | ppc_md.restart = briq_restart; |
bbd0abda PM |
323 | } else { |
324 | /* Let's assume it is an IBM chrp if all else fails */ | |
325 | _chrp_type = _CHRP_IBM; | |
326 | } | |
8c8dc322 | 327 | of_node_put(root); |
26c5032e | 328 | printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]); |
bbd0abda PM |
329 | |
330 | rtas_initialize(); | |
331 | if (rtas_token("display-character") >= 0) | |
332 | ppc_md.progress = rtas_progress; | |
333 | ||
49e16b7b PM |
334 | /* use RTAS time-of-day routines if available */ |
335 | if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) { | |
336 | ppc_md.get_boot_time = rtas_get_boot_time; | |
337 | ppc_md.get_rtc_time = rtas_get_rtc_time; | |
338 | ppc_md.set_rtc_time = rtas_set_rtc_time; | |
339 | } | |
340 | ||
bbd0abda PM |
341 | /* On pegasos, enable the L2 cache if not already done by OF */ |
342 | pegasos_set_l2cr(); | |
343 | ||
344 | /* Lookup PCI host bridges */ | |
345 | chrp_find_bridges(); | |
346 | ||
347 | /* | |
348 | * Temporary fixes for PCI devices. | |
349 | * -- Geert | |
350 | */ | |
351 | hydra_init(); /* Mac I/O */ | |
352 | ||
353 | /* | |
354 | * Fix the Super I/O configuration | |
355 | */ | |
356 | sio_init(); | |
357 | ||
bbd0abda PM |
358 | pci_create_OF_bus_map(); |
359 | ||
360 | /* | |
361 | * Print the banner, then scroll down so boot progress | |
362 | * can be printed. -- Cort | |
363 | */ | |
364 | if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0); | |
365 | } | |
366 | ||
367 | void | |
9618edab | 368 | chrp_event_scan(unsigned long unused) |
bbd0abda PM |
369 | { |
370 | unsigned char log[1024]; | |
371 | int ret = 0; | |
372 | ||
373 | /* XXX: we should loop until the hardware says no more error logs -- Cort */ | |
374 | rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0, | |
375 | __pa(log), 1024); | |
9618edab PM |
376 | mod_timer(&__get_cpu_var(heartbeat_timer), |
377 | jiffies + event_scan_interval); | |
bbd0abda PM |
378 | } |
379 | ||
35a84c2f | 380 | static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) |
b9e5b4e6 | 381 | { |
35a84c2f | 382 | unsigned int cascade_irq = i8259_irq(); |
0ebfff14 | 383 | if (cascade_irq != NO_IRQ) |
49f19ce4 | 384 | generic_handle_irq(cascade_irq); |
0ebfff14 | 385 | desc->chip->eoi(irq); |
b9e5b4e6 BH |
386 | } |
387 | ||
bbd0abda PM |
388 | /* |
389 | * Finds the open-pic node and sets up the mpic driver. | |
390 | */ | |
391 | static void __init chrp_find_openpic(void) | |
392 | { | |
393 | struct device_node *np, *root; | |
0ebfff14 | 394 | int len, i, j; |
bbd0abda | 395 | int isu_size, idu_size; |
ae6b4101 | 396 | const unsigned int *iranges, *opprop = NULL; |
bbd0abda PM |
397 | int oplen = 0; |
398 | unsigned long opaddr; | |
399 | int na = 1; | |
bbd0abda | 400 | |
0ebfff14 | 401 | np = of_find_node_by_type(NULL, "open-pic"); |
bbd0abda PM |
402 | if (np == NULL) |
403 | return; | |
0ebfff14 | 404 | root = of_find_node_by_path("/"); |
bbd0abda | 405 | if (root) { |
e2eb6392 | 406 | opprop = of_get_property(root, "platform-open-pic", &oplen); |
a8bda5dd | 407 | na = of_n_addr_cells(root); |
bbd0abda PM |
408 | } |
409 | if (opprop && oplen >= na * sizeof(unsigned int)) { | |
410 | opaddr = opprop[na-1]; /* assume 32-bit */ | |
411 | oplen /= na * sizeof(unsigned int); | |
412 | } else { | |
575e3216 | 413 | struct resource r; |
0ebfff14 BH |
414 | if (of_address_to_resource(np, 0, &r)) { |
415 | goto bail; | |
416 | } | |
575e3216 | 417 | opaddr = r.start; |
bbd0abda PM |
418 | oplen = 0; |
419 | } | |
420 | ||
421 | printk(KERN_INFO "OpenPIC at %lx\n", opaddr); | |
422 | ||
e2eb6392 | 423 | iranges = of_get_property(np, "interrupt-ranges", &len); |
bbd0abda PM |
424 | if (iranges == NULL) |
425 | len = 0; /* non-distributed mpic */ | |
426 | else | |
427 | len /= 2 * sizeof(unsigned int); | |
428 | ||
429 | /* | |
430 | * The first pair of cells in interrupt-ranges refers to the | |
431 | * IDU; subsequent pairs refer to the ISUs. | |
432 | */ | |
433 | if (oplen < len) { | |
434 | printk(KERN_ERR "Insufficient addresses for distributed" | |
575e3216 | 435 | " OpenPIC (%d < %d)\n", oplen, len); |
bbd0abda PM |
436 | len = oplen; |
437 | } | |
438 | ||
439 | isu_size = 0; | |
440 | idu_size = 0; | |
441 | if (len > 0 && iranges[1] != 0) { | |
442 | printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n", | |
443 | iranges[0], iranges[0] + iranges[1] - 1); | |
444 | idu_size = iranges[1]; | |
445 | } | |
446 | if (len > 1) | |
447 | isu_size = iranges[3]; | |
448 | ||
0ebfff14 BH |
449 | chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY, |
450 | isu_size, 0, " MPIC "); | |
bbd0abda PM |
451 | if (chrp_mpic == NULL) { |
452 | printk(KERN_ERR "Failed to allocate MPIC structure\n"); | |
0ebfff14 | 453 | goto bail; |
bbd0abda | 454 | } |
bbd0abda PM |
455 | j = na - 1; |
456 | for (i = 1; i < len; ++i) { | |
457 | iranges += 2; | |
458 | j += na; | |
459 | printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n", | |
460 | iranges[0], iranges[0] + iranges[1] - 1, | |
461 | opprop[j]); | |
462 | mpic_assign_isu(chrp_mpic, i - 1, opprop[j]); | |
463 | } | |
464 | ||
465 | mpic_init(chrp_mpic); | |
0ebfff14 BH |
466 | ppc_md.get_irq = mpic_get_irq; |
467 | bail: | |
468 | of_node_put(root); | |
469 | of_node_put(np); | |
bbd0abda PM |
470 | } |
471 | ||
e85f008d | 472 | #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) |
bbd0abda PM |
473 | static struct irqaction xmon_irqaction = { |
474 | .handler = xmon_irq, | |
475 | .mask = CPU_MASK_NONE, | |
476 | .name = "XMON break", | |
477 | }; | |
478 | #endif | |
479 | ||
0ebfff14 | 480 | static void __init chrp_find_8259(void) |
bbd0abda | 481 | { |
0ebfff14 | 482 | struct device_node *np, *pic = NULL; |
bbd0abda | 483 | unsigned long chrp_int_ack = 0; |
0ebfff14 | 484 | unsigned int cascade_irq; |
bbd0abda | 485 | |
0ebfff14 BH |
486 | /* Look for cascade */ |
487 | for_each_node_by_type(np, "interrupt-controller") | |
55b61fec | 488 | if (of_device_is_compatible(np, "chrp,iic")) { |
0ebfff14 BH |
489 | pic = np; |
490 | break; | |
491 | } | |
492 | /* Ok, 8259 wasn't found. We need to handle the case where | |
493 | * we have a pegasos that claims to be chrp but doesn't have | |
494 | * a proper interrupt tree | |
495 | */ | |
496 | if (pic == NULL && chrp_mpic != NULL) { | |
497 | printk(KERN_ERR "i8259: Not found in device-tree" | |
498 | " assuming no legacy interrupts\n"); | |
499 | return; | |
500 | } | |
501 | ||
502 | /* Look for intack. In a perfect world, we would look for it on | |
503 | * the ISA bus that holds the 8259 but heh... Works that way. If | |
504 | * we ever see a problem, we can try to re-use the pSeries code here. | |
505 | * Also, Pegasos-type platforms don't have a proper node to start | |
506 | * from anyway | |
507 | */ | |
30686ba6 | 508 | for_each_node_by_name(np, "pci") { |
e2eb6392 | 509 | const unsigned int *addrp = of_get_property(np, |
ae6b4101 | 510 | "8259-interrupt-acknowledge", NULL); |
bbd0abda PM |
511 | |
512 | if (addrp == NULL) | |
513 | continue; | |
a8bda5dd | 514 | chrp_int_ack = addrp[of_n_addr_cells(np)-1]; |
bbd0abda PM |
515 | break; |
516 | } | |
30686ba6 | 517 | of_node_put(np); |
bbd0abda | 518 | if (np == NULL) |
0ebfff14 BH |
519 | printk(KERN_WARNING "Cannot find PCI interrupt acknowledge" |
520 | " address, polling\n"); | |
521 | ||
522 | i8259_init(pic, chrp_int_ack); | |
f4d4c354 | 523 | if (ppc_md.get_irq == NULL) { |
0ebfff14 | 524 | ppc_md.get_irq = i8259_irq; |
f4d4c354 BH |
525 | irq_set_default_host(i8259_get_host()); |
526 | } | |
0ebfff14 BH |
527 | if (chrp_mpic != NULL) { |
528 | cascade_irq = irq_of_parse_and_map(pic, 0); | |
529 | if (cascade_irq == NO_IRQ) | |
530 | printk(KERN_ERR "i8259: failed to map cascade irq\n"); | |
531 | else | |
532 | set_irq_chained_handler(cascade_irq, | |
533 | chrp_8259_cascade); | |
534 | } | |
535 | } | |
bbd0abda | 536 | |
0ebfff14 BH |
537 | void __init chrp_init_IRQ(void) |
538 | { | |
e85f008d | 539 | #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) |
0ebfff14 BH |
540 | struct device_node *kbd; |
541 | #endif | |
bbd0abda | 542 | chrp_find_openpic(); |
0ebfff14 | 543 | chrp_find_8259(); |
bbd0abda | 544 | |
1e031d65 BH |
545 | #ifdef CONFIG_SMP |
546 | /* Pegasos has no MPIC, those ops would make it crash. It might be an | |
547 | * option to move setting them to after we probe the PIC though | |
548 | */ | |
549 | if (chrp_mpic != NULL) | |
550 | smp_ops = &chrp_smp_ops; | |
551 | #endif /* CONFIG_SMP */ | |
552 | ||
bbd0abda PM |
553 | if (_chrp_type == _CHRP_Pegasos) |
554 | ppc_md.get_irq = i8259_irq; | |
bbd0abda | 555 | |
e85f008d | 556 | #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) |
bbd0abda PM |
557 | /* see if there is a keyboard in the device tree |
558 | with a parent of type "adb" */ | |
30686ba6 | 559 | for_each_node_by_name(kbd, "keyboard") |
bbd0abda PM |
560 | if (kbd->parent && kbd->parent->type |
561 | && strcmp(kbd->parent->type, "adb") == 0) | |
562 | break; | |
30686ba6 | 563 | of_node_put(kbd); |
bbd0abda PM |
564 | if (kbd) |
565 | setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction); | |
566 | #endif | |
567 | } | |
568 | ||
569 | void __init | |
570 | chrp_init2(void) | |
571 | { | |
9618edab | 572 | struct device_node *device; |
ae6b4101 | 573 | const unsigned int *p = NULL; |
9618edab | 574 | |
35e95e63 OH |
575 | #ifdef CONFIG_NVRAM |
576 | chrp_nvram_init(); | |
577 | #endif | |
578 | ||
bbd0abda PM |
579 | request_region(0x20,0x20,"pic1"); |
580 | request_region(0xa0,0x20,"pic2"); | |
581 | request_region(0x00,0x20,"dma1"); | |
582 | request_region(0x40,0x20,"timer"); | |
583 | request_region(0x80,0x10,"dma page reg"); | |
584 | request_region(0xc0,0x20,"dma2"); | |
585 | ||
9618edab PM |
586 | /* Get the event scan rate for the rtas so we know how |
587 | * often it expects a heartbeat. -- Cort | |
588 | */ | |
30686ba6 | 589 | device = of_find_node_by_name(NULL, "rtas"); |
9618edab | 590 | if (device) |
e2eb6392 | 591 | p = of_get_property(device, "rtas-event-scan-rate", NULL); |
9618edab PM |
592 | if (p && *p) { |
593 | /* | |
594 | * Arrange to call chrp_event_scan at least *p times | |
595 | * per minute. We use 59 rather than 60 here so that | |
596 | * the rate will be slightly higher than the minimum. | |
597 | * This all assumes we don't do hotplug CPU on any | |
598 | * machine that needs the event scans done. | |
599 | */ | |
600 | unsigned long interval, offset; | |
601 | int cpu, ncpus; | |
602 | struct timer_list *timer; | |
603 | ||
604 | interval = HZ * 59 / *p; | |
605 | offset = HZ; | |
606 | ncpus = num_online_cpus(); | |
607 | event_scan_interval = ncpus * interval; | |
608 | for (cpu = 0; cpu < ncpus; ++cpu) { | |
609 | timer = &per_cpu(heartbeat_timer, cpu); | |
610 | setup_timer(timer, chrp_event_scan, 0); | |
611 | timer->expires = jiffies + offset; | |
612 | add_timer_on(timer, cpu); | |
613 | offset += interval; | |
614 | } | |
615 | printk("RTAS Event Scan Rate: %u (%lu jiffies)\n", | |
616 | *p, interval); | |
617 | } | |
30686ba6 | 618 | of_node_put(device); |
9618edab | 619 | |
bbd0abda PM |
620 | if (ppc_md.progress) |
621 | ppc_md.progress(" Have fun! ", 0x7777); | |
622 | } | |
623 | ||
e8222502 | 624 | static int __init chrp_probe(void) |
bbd0abda | 625 | { |
e8222502 BH |
626 | char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), |
627 | "device_type", NULL); | |
628 | if (dtype == NULL) | |
629 | return 0; | |
630 | if (strcmp(dtype, "chrp")) | |
631 | return 0; | |
632 | ||
bbd0abda PM |
633 | ISA_DMA_THRESHOLD = ~0L; |
634 | DMA_MODE_READ = 0x44; | |
635 | DMA_MODE_WRITE = 0x48; | |
bbd0abda | 636 | |
b86756ae | 637 | return 1; |
bbd0abda | 638 | } |
b86756ae PM |
639 | |
640 | define_machine(chrp) { | |
641 | .name = "CHRP", | |
642 | .probe = chrp_probe, | |
643 | .setup_arch = chrp_setup_arch, | |
644 | .init = chrp_init2, | |
5bc97786 | 645 | .init_early = chrp_init_early, |
b86756ae PM |
646 | .show_cpuinfo = chrp_show_cpuinfo, |
647 | .init_IRQ = chrp_init_IRQ, | |
b86756ae PM |
648 | .restart = rtas_restart, |
649 | .power_off = rtas_power_off, | |
650 | .halt = rtas_halt, | |
651 | .time_init = chrp_time_init, | |
652 | .set_rtc_time = chrp_set_rtc_time, | |
653 | .get_rtc_time = chrp_get_rtc_time, | |
654 | .calibrate_decr = generic_calibrate_decr, | |
655 | .phys_mem_access_prot = pci_phys_mem_access_prot, | |
656 | }; |