Commit | Line | Data |
---|---|---|
bbd0abda | 1 | /* |
bbd0abda PM |
2 | * Copyright (C) 1995 Linus Torvalds |
3 | * Adapted from 'alpha' version by Gary Thomas | |
4 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
5 | */ | |
6 | ||
7 | /* | |
8 | * bootup setup stuff.. | |
9 | */ | |
10 | ||
bbd0abda PM |
11 | #include <linux/errno.h> |
12 | #include <linux/sched.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/stddef.h> | |
16 | #include <linux/unistd.h> | |
17 | #include <linux/ptrace.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/user.h> | |
20 | #include <linux/a.out.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/major.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/reboot.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/version.h> | |
28 | #include <linux/adb.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/ide.h> | |
32 | #include <linux/console.h> | |
33 | #include <linux/seq_file.h> | |
34 | #include <linux/root_dev.h> | |
35 | #include <linux/initrd.h> | |
36 | #include <linux/module.h> | |
9618edab | 37 | #include <linux/timer.h> |
bbd0abda PM |
38 | |
39 | #include <asm/io.h> | |
40 | #include <asm/pgtable.h> | |
41 | #include <asm/prom.h> | |
42 | #include <asm/gg2.h> | |
43 | #include <asm/pci-bridge.h> | |
44 | #include <asm/dma.h> | |
45 | #include <asm/machdep.h> | |
46 | #include <asm/irq.h> | |
47 | #include <asm/hydra.h> | |
48 | #include <asm/sections.h> | |
49 | #include <asm/time.h> | |
bbd0abda PM |
50 | #include <asm/i8259.h> |
51 | #include <asm/mpic.h> | |
52 | #include <asm/rtas.h> | |
53 | #include <asm/xmon.h> | |
54 | ||
35e95e63 | 55 | #include "chrp.h" |
bbd0abda | 56 | |
bbd0abda | 57 | void rtas_indicator_progress(char *, unsigned short); |
bbd0abda PM |
58 | |
59 | int _chrp_type; | |
60 | EXPORT_SYMBOL(_chrp_type); | |
61 | ||
62 | struct mpic *chrp_mpic; | |
63 | ||
9618edab PM |
64 | /* Used for doing CHRP event-scans */ |
65 | DEFINE_PER_CPU(struct timer_list, heartbeat_timer); | |
66 | unsigned long event_scan_interval; | |
67 | ||
bbd0abda PM |
68 | /* |
69 | * XXX this should be in xmon.h, but putting it there means xmon.h | |
70 | * has to include <linux/interrupt.h> (to get irqreturn_t), which | |
71 | * causes all sorts of problems. -- paulus | |
72 | */ | |
73 | extern irqreturn_t xmon_irq(int, void *, struct pt_regs *); | |
74 | ||
75 | extern unsigned long loops_per_jiffy; | |
76 | ||
77 | #ifdef CONFIG_SMP | |
78 | extern struct smp_ops_t chrp_smp_ops; | |
79 | #endif | |
80 | ||
81 | static const char *gg2_memtypes[4] = { | |
82 | "FPM", "SDRAM", "EDO", "BEDO" | |
83 | }; | |
84 | static const char *gg2_cachesizes[4] = { | |
85 | "256 KB", "512 KB", "1 MB", "Reserved" | |
86 | }; | |
87 | static const char *gg2_cachetypes[4] = { | |
88 | "Asynchronous", "Reserved", "Flow-Through Synchronous", | |
89 | "Pipelined Synchronous" | |
90 | }; | |
91 | static const char *gg2_cachemodes[4] = { | |
92 | "Disabled", "Write-Through", "Copy-Back", "Transparent Mode" | |
93 | }; | |
94 | ||
95 | void chrp_show_cpuinfo(struct seq_file *m) | |
96 | { | |
97 | int i, sdramen; | |
98 | unsigned int t; | |
99 | struct device_node *root; | |
100 | const char *model = ""; | |
101 | ||
102 | root = find_path_device("/"); | |
103 | if (root) | |
104 | model = get_property(root, "model", NULL); | |
105 | seq_printf(m, "machine\t\t: CHRP %s\n", model); | |
106 | ||
107 | /* longtrail (goldengate) stuff */ | |
108 | if (!strncmp(model, "IBM,LongTrail", 13)) { | |
109 | /* VLSI VAS96011/12 `Golden Gate 2' */ | |
110 | /* Memory banks */ | |
111 | sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL) | |
112 | >>31) & 1; | |
113 | for (i = 0; i < (sdramen ? 4 : 6); i++) { | |
114 | t = in_le32(gg2_pci_config_base+ | |
115 | GG2_PCI_DRAM_BANK0+ | |
116 | i*4); | |
117 | if (!(t & 1)) | |
118 | continue; | |
119 | switch ((t>>8) & 0x1f) { | |
120 | case 0x1f: | |
121 | model = "4 MB"; | |
122 | break; | |
123 | case 0x1e: | |
124 | model = "8 MB"; | |
125 | break; | |
126 | case 0x1c: | |
127 | model = "16 MB"; | |
128 | break; | |
129 | case 0x18: | |
130 | model = "32 MB"; | |
131 | break; | |
132 | case 0x10: | |
133 | model = "64 MB"; | |
134 | break; | |
135 | case 0x00: | |
136 | model = "128 MB"; | |
137 | break; | |
138 | default: | |
139 | model = "Reserved"; | |
140 | break; | |
141 | } | |
142 | seq_printf(m, "memory bank %d\t: %s %s\n", i, model, | |
143 | gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]); | |
144 | } | |
145 | /* L2 cache */ | |
146 | t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL); | |
147 | seq_printf(m, "board l2\t: %s %s (%s)\n", | |
148 | gg2_cachesizes[(t>>7) & 3], | |
149 | gg2_cachetypes[(t>>2) & 3], | |
150 | gg2_cachemodes[t & 3]); | |
151 | } | |
152 | } | |
153 | ||
154 | /* | |
155 | * Fixes for the National Semiconductor PC78308VUL SuperI/O | |
156 | * | |
157 | * Some versions of Open Firmware incorrectly initialize the IRQ settings | |
158 | * for keyboard and mouse | |
159 | */ | |
160 | static inline void __init sio_write(u8 val, u8 index) | |
161 | { | |
162 | outb(index, 0x15c); | |
163 | outb(val, 0x15d); | |
164 | } | |
165 | ||
166 | static inline u8 __init sio_read(u8 index) | |
167 | { | |
168 | outb(index, 0x15c); | |
169 | return inb(0x15d); | |
170 | } | |
171 | ||
172 | static void __init sio_fixup_irq(const char *name, u8 device, u8 level, | |
173 | u8 type) | |
174 | { | |
175 | u8 level0, type0, active; | |
176 | ||
177 | /* select logical device */ | |
178 | sio_write(device, 0x07); | |
179 | active = sio_read(0x30); | |
180 | level0 = sio_read(0x70); | |
181 | type0 = sio_read(0x71); | |
182 | if (level0 != level || type0 != type || !active) { | |
183 | printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: " | |
184 | "remapping to level %d, type %d, active\n", | |
185 | name, level0, type0, !active ? "in" : "", level, type); | |
186 | sio_write(0x01, 0x30); | |
187 | sio_write(level, 0x70); | |
188 | sio_write(type, 0x71); | |
189 | } | |
190 | } | |
191 | ||
192 | static void __init sio_init(void) | |
193 | { | |
194 | struct device_node *root; | |
195 | ||
196 | if ((root = find_path_device("/")) && | |
197 | !strncmp(get_property(root, "model", NULL), "IBM,LongTrail", 13)) { | |
198 | /* logical device 0 (KBC/Keyboard) */ | |
199 | sio_fixup_irq("keyboard", 0, 1, 2); | |
200 | /* select logical device 1 (KBC/Mouse) */ | |
201 | sio_fixup_irq("mouse", 1, 12, 2); | |
202 | } | |
203 | } | |
204 | ||
205 | ||
206 | static void __init pegasos_set_l2cr(void) | |
207 | { | |
208 | struct device_node *np; | |
209 | ||
210 | /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */ | |
211 | if (_chrp_type != _CHRP_Pegasos) | |
212 | return; | |
213 | ||
214 | /* Enable L2 cache if needed */ | |
215 | np = find_type_devices("cpu"); | |
216 | if (np != NULL) { | |
217 | unsigned int *l2cr = (unsigned int *) | |
218 | get_property (np, "l2cr", NULL); | |
219 | if (l2cr == NULL) { | |
220 | printk ("Pegasos l2cr : no cpu l2cr property found\n"); | |
221 | return; | |
222 | } | |
223 | if (!((*l2cr) & 0x80000000)) { | |
224 | printk ("Pegasos l2cr : L2 cache was not active, " | |
225 | "activating\n"); | |
226 | _set_L2CR(0); | |
227 | _set_L2CR((*l2cr) | 0x80000000); | |
228 | } | |
229 | } | |
230 | } | |
231 | ||
232 | void __init chrp_setup_arch(void) | |
233 | { | |
234 | struct device_node *root = find_path_device ("/"); | |
235 | char *machine = NULL; | |
bbd0abda PM |
236 | |
237 | /* init to some ~sane value until calibrate_delay() runs */ | |
238 | loops_per_jiffy = 50000000/HZ; | |
239 | ||
240 | if (root) | |
241 | machine = get_property(root, "model", NULL); | |
242 | if (machine && strncmp(machine, "Pegasos", 7) == 0) { | |
243 | _chrp_type = _CHRP_Pegasos; | |
244 | } else if (machine && strncmp(machine, "IBM", 3) == 0) { | |
245 | _chrp_type = _CHRP_IBM; | |
246 | } else if (machine && strncmp(machine, "MOT", 3) == 0) { | |
247 | _chrp_type = _CHRP_Motorola; | |
248 | } else { | |
249 | /* Let's assume it is an IBM chrp if all else fails */ | |
250 | _chrp_type = _CHRP_IBM; | |
251 | } | |
252 | printk("chrp type = %x\n", _chrp_type); | |
253 | ||
254 | rtas_initialize(); | |
255 | if (rtas_token("display-character") >= 0) | |
256 | ppc_md.progress = rtas_progress; | |
257 | ||
49e16b7b PM |
258 | /* use RTAS time-of-day routines if available */ |
259 | if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) { | |
260 | ppc_md.get_boot_time = rtas_get_boot_time; | |
261 | ppc_md.get_rtc_time = rtas_get_rtc_time; | |
262 | ppc_md.set_rtc_time = rtas_set_rtc_time; | |
263 | } | |
264 | ||
bbd0abda PM |
265 | #ifdef CONFIG_BLK_DEV_INITRD |
266 | /* this is fine for chrp */ | |
267 | initrd_below_start_ok = 1; | |
268 | ||
269 | if (initrd_start) | |
270 | ROOT_DEV = Root_RAM0; | |
271 | else | |
272 | #endif | |
273 | ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */ | |
274 | ||
275 | /* On pegasos, enable the L2 cache if not already done by OF */ | |
276 | pegasos_set_l2cr(); | |
277 | ||
278 | /* Lookup PCI host bridges */ | |
279 | chrp_find_bridges(); | |
280 | ||
281 | /* | |
282 | * Temporary fixes for PCI devices. | |
283 | * -- Geert | |
284 | */ | |
285 | hydra_init(); /* Mac I/O */ | |
286 | ||
287 | /* | |
288 | * Fix the Super I/O configuration | |
289 | */ | |
290 | sio_init(); | |
291 | ||
bbd0abda PM |
292 | pci_create_OF_bus_map(); |
293 | ||
e8222502 BH |
294 | #ifdef CONFIG_SMP |
295 | smp_ops = &chrp_smp_ops; | |
296 | #endif /* CONFIG_SMP */ | |
297 | ||
bbd0abda PM |
298 | /* |
299 | * Print the banner, then scroll down so boot progress | |
300 | * can be printed. -- Cort | |
301 | */ | |
302 | if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0); | |
303 | } | |
304 | ||
305 | void | |
9618edab | 306 | chrp_event_scan(unsigned long unused) |
bbd0abda PM |
307 | { |
308 | unsigned char log[1024]; | |
309 | int ret = 0; | |
310 | ||
311 | /* XXX: we should loop until the hardware says no more error logs -- Cort */ | |
312 | rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0, | |
313 | __pa(log), 1024); | |
9618edab PM |
314 | mod_timer(&__get_cpu_var(heartbeat_timer), |
315 | jiffies + event_scan_interval); | |
bbd0abda PM |
316 | } |
317 | ||
318 | /* | |
319 | * Finds the open-pic node and sets up the mpic driver. | |
320 | */ | |
321 | static void __init chrp_find_openpic(void) | |
322 | { | |
323 | struct device_node *np, *root; | |
324 | int len, i, j, irq_count; | |
325 | int isu_size, idu_size; | |
326 | unsigned int *iranges, *opprop = NULL; | |
327 | int oplen = 0; | |
328 | unsigned long opaddr; | |
329 | int na = 1; | |
330 | unsigned char init_senses[NR_IRQS - NUM_8259_INTERRUPTS]; | |
331 | ||
332 | np = find_type_devices("open-pic"); | |
333 | if (np == NULL) | |
334 | return; | |
335 | root = find_path_device("/"); | |
336 | if (root) { | |
337 | opprop = (unsigned int *) get_property | |
338 | (root, "platform-open-pic", &oplen); | |
339 | na = prom_n_addr_cells(root); | |
340 | } | |
341 | if (opprop && oplen >= na * sizeof(unsigned int)) { | |
342 | opaddr = opprop[na-1]; /* assume 32-bit */ | |
343 | oplen /= na * sizeof(unsigned int); | |
344 | } else { | |
575e3216 DW |
345 | struct resource r; |
346 | if (of_address_to_resource(np, 0, &r)) | |
bbd0abda | 347 | return; |
575e3216 | 348 | opaddr = r.start; |
bbd0abda PM |
349 | oplen = 0; |
350 | } | |
351 | ||
352 | printk(KERN_INFO "OpenPIC at %lx\n", opaddr); | |
353 | ||
354 | irq_count = NR_IRQS - NUM_ISA_INTERRUPTS - 4; /* leave room for IPIs */ | |
a23414be PM |
355 | prom_get_irq_senses(init_senses, NUM_ISA_INTERRUPTS, NR_IRQS - 4); |
356 | /* i8259 cascade is always positive level */ | |
357 | init_senses[0] = IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE; | |
bbd0abda PM |
358 | |
359 | iranges = (unsigned int *) get_property(np, "interrupt-ranges", &len); | |
360 | if (iranges == NULL) | |
361 | len = 0; /* non-distributed mpic */ | |
362 | else | |
363 | len /= 2 * sizeof(unsigned int); | |
364 | ||
365 | /* | |
366 | * The first pair of cells in interrupt-ranges refers to the | |
367 | * IDU; subsequent pairs refer to the ISUs. | |
368 | */ | |
369 | if (oplen < len) { | |
370 | printk(KERN_ERR "Insufficient addresses for distributed" | |
575e3216 | 371 | " OpenPIC (%d < %d)\n", oplen, len); |
bbd0abda PM |
372 | len = oplen; |
373 | } | |
374 | ||
375 | isu_size = 0; | |
376 | idu_size = 0; | |
377 | if (len > 0 && iranges[1] != 0) { | |
378 | printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n", | |
379 | iranges[0], iranges[0] + iranges[1] - 1); | |
380 | idu_size = iranges[1]; | |
381 | } | |
382 | if (len > 1) | |
383 | isu_size = iranges[3]; | |
384 | ||
385 | chrp_mpic = mpic_alloc(opaddr, MPIC_PRIMARY, | |
386 | isu_size, NUM_ISA_INTERRUPTS, irq_count, | |
387 | NR_IRQS - 4, init_senses, irq_count, | |
388 | " MPIC "); | |
389 | if (chrp_mpic == NULL) { | |
390 | printk(KERN_ERR "Failed to allocate MPIC structure\n"); | |
391 | return; | |
392 | } | |
393 | ||
394 | j = na - 1; | |
395 | for (i = 1; i < len; ++i) { | |
396 | iranges += 2; | |
397 | j += na; | |
398 | printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n", | |
399 | iranges[0], iranges[0] + iranges[1] - 1, | |
400 | opprop[j]); | |
401 | mpic_assign_isu(chrp_mpic, i - 1, opprop[j]); | |
402 | } | |
403 | ||
404 | mpic_init(chrp_mpic); | |
405 | mpic_setup_cascade(NUM_ISA_INTERRUPTS, i8259_irq_cascade, NULL); | |
406 | } | |
407 | ||
408 | #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) | |
409 | static struct irqaction xmon_irqaction = { | |
410 | .handler = xmon_irq, | |
411 | .mask = CPU_MASK_NONE, | |
412 | .name = "XMON break", | |
413 | }; | |
414 | #endif | |
415 | ||
416 | void __init chrp_init_IRQ(void) | |
417 | { | |
418 | struct device_node *np; | |
419 | unsigned long chrp_int_ack = 0; | |
420 | #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) | |
421 | struct device_node *kbd; | |
422 | #endif | |
423 | ||
424 | for (np = find_devices("pci"); np != NULL; np = np->next) { | |
425 | unsigned int *addrp = (unsigned int *) | |
426 | get_property(np, "8259-interrupt-acknowledge", NULL); | |
427 | ||
428 | if (addrp == NULL) | |
429 | continue; | |
430 | chrp_int_ack = addrp[prom_n_addr_cells(np)-1]; | |
431 | break; | |
432 | } | |
433 | if (np == NULL) | |
434 | printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n"); | |
435 | ||
436 | chrp_find_openpic(); | |
437 | ||
438 | i8259_init(chrp_int_ack, 0); | |
439 | ||
440 | if (_chrp_type == _CHRP_Pegasos) | |
441 | ppc_md.get_irq = i8259_irq; | |
bbd0abda PM |
442 | |
443 | #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON) | |
444 | /* see if there is a keyboard in the device tree | |
445 | with a parent of type "adb" */ | |
446 | for (kbd = find_devices("keyboard"); kbd; kbd = kbd->next) | |
447 | if (kbd->parent && kbd->parent->type | |
448 | && strcmp(kbd->parent->type, "adb") == 0) | |
449 | break; | |
450 | if (kbd) | |
451 | setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction); | |
452 | #endif | |
453 | } | |
454 | ||
455 | void __init | |
456 | chrp_init2(void) | |
457 | { | |
9618edab PM |
458 | struct device_node *device; |
459 | unsigned int *p = NULL; | |
460 | ||
35e95e63 OH |
461 | #ifdef CONFIG_NVRAM |
462 | chrp_nvram_init(); | |
463 | #endif | |
464 | ||
bbd0abda PM |
465 | request_region(0x20,0x20,"pic1"); |
466 | request_region(0xa0,0x20,"pic2"); | |
467 | request_region(0x00,0x20,"dma1"); | |
468 | request_region(0x40,0x20,"timer"); | |
469 | request_region(0x80,0x10,"dma page reg"); | |
470 | request_region(0xc0,0x20,"dma2"); | |
471 | ||
9618edab PM |
472 | /* Get the event scan rate for the rtas so we know how |
473 | * often it expects a heartbeat. -- Cort | |
474 | */ | |
475 | device = find_devices("rtas"); | |
476 | if (device) | |
477 | p = (unsigned int *) get_property | |
478 | (device, "rtas-event-scan-rate", NULL); | |
479 | if (p && *p) { | |
480 | /* | |
481 | * Arrange to call chrp_event_scan at least *p times | |
482 | * per minute. We use 59 rather than 60 here so that | |
483 | * the rate will be slightly higher than the minimum. | |
484 | * This all assumes we don't do hotplug CPU on any | |
485 | * machine that needs the event scans done. | |
486 | */ | |
487 | unsigned long interval, offset; | |
488 | int cpu, ncpus; | |
489 | struct timer_list *timer; | |
490 | ||
491 | interval = HZ * 59 / *p; | |
492 | offset = HZ; | |
493 | ncpus = num_online_cpus(); | |
494 | event_scan_interval = ncpus * interval; | |
495 | for (cpu = 0; cpu < ncpus; ++cpu) { | |
496 | timer = &per_cpu(heartbeat_timer, cpu); | |
497 | setup_timer(timer, chrp_event_scan, 0); | |
498 | timer->expires = jiffies + offset; | |
499 | add_timer_on(timer, cpu); | |
500 | offset += interval; | |
501 | } | |
502 | printk("RTAS Event Scan Rate: %u (%lu jiffies)\n", | |
503 | *p, interval); | |
504 | } | |
505 | ||
bbd0abda PM |
506 | if (ppc_md.progress) |
507 | ppc_md.progress(" Have fun! ", 0x7777); | |
508 | } | |
509 | ||
e8222502 | 510 | static int __init chrp_probe(void) |
bbd0abda | 511 | { |
e8222502 BH |
512 | char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), |
513 | "device_type", NULL); | |
514 | if (dtype == NULL) | |
515 | return 0; | |
516 | if (strcmp(dtype, "chrp")) | |
517 | return 0; | |
518 | ||
bbd0abda PM |
519 | ISA_DMA_THRESHOLD = ~0L; |
520 | DMA_MODE_READ = 0x44; | |
521 | DMA_MODE_WRITE = 0x48; | |
522 | isa_io_base = CHRP_ISA_IO_BASE; /* default value */ | |
523 | ppc_do_canonicalize_irqs = 1; | |
524 | ||
525 | /* Assume we have an 8259... */ | |
526 | __irq_offset_value = NUM_ISA_INTERRUPTS; | |
527 | ||
b86756ae | 528 | return 1; |
bbd0abda | 529 | } |
b86756ae PM |
530 | |
531 | define_machine(chrp) { | |
532 | .name = "CHRP", | |
533 | .probe = chrp_probe, | |
534 | .setup_arch = chrp_setup_arch, | |
535 | .init = chrp_init2, | |
536 | .show_cpuinfo = chrp_show_cpuinfo, | |
537 | .init_IRQ = chrp_init_IRQ, | |
538 | .get_irq = mpic_get_irq, | |
539 | .pcibios_fixup = chrp_pcibios_fixup, | |
540 | .restart = rtas_restart, | |
541 | .power_off = rtas_power_off, | |
542 | .halt = rtas_halt, | |
543 | .time_init = chrp_time_init, | |
544 | .set_rtc_time = chrp_set_rtc_time, | |
545 | .get_rtc_time = chrp_get_rtc_time, | |
546 | .calibrate_decr = generic_calibrate_decr, | |
547 | .phys_mem_access_prot = pci_phys_mem_access_prot, | |
548 | }; |