[linux-block.git] / arch / powerpc / platforms / chrp / pci.c

/*
 * CHRP pci routines.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/hydra.h>
#include <asm/prom.h>
#include <asm/gg2.h>
#include <asm/machdep.h>
#include <asm/sections.h>
#include <asm/pci-bridge.h>
#include <asm/open_pic.h>
#include <asm/grackle.h>
#include <asm/rtas.h>

#include "chrp.h"

/* LongTrail */
void __iomem *gg2_pci_config_base;

/*
 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
 * limit the bus number to 3 bits
 */

int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
			   int len, u32 *val)
{
	volatile void __iomem *cfg_data;
	struct pci_controller *hose = bus->sysdata;

	if (bus->number > 7)
		return PCIBIOS_DEVICE_NOT_FOUND;
	/*
	 * Note: the caller has already checked that off is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
	switch (len) {
	case 1:
		*val =  in_8(cfg_data);
		break;
	case 2:
		*val = in_le16(cfg_data);
		break;
	default:
		*val = in_le32(cfg_data);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
			    int len, u32 val)
{
	volatile void __iomem *cfg_data;
	struct pci_controller *hose = bus->sysdata;

	if (bus->number > 7)
		return PCIBIOS_DEVICE_NOT_FOUND;
	/*
	 * Note: the caller has already checked that off is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
	switch (len) {
	case 1:
		out_8(cfg_data, val);
		break;
	case 2:
		out_le16(cfg_data, val);
		break;
	default:
		out_le32(cfg_data, val);
		break;
	}
	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops gg2_pci_ops =
{
	gg2_read_config,
	gg2_write_config
};

/*
 * Access functions for PCI config space using RTAS calls.
 */
int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
		     int len, u32 *val)
{
	struct pci_controller *hose = bus->sysdata;
	unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
		| (((bus->number - hose->first_busno) & 0xff) << 16)
		| (hose->index << 24);
        int ret = -1;
	int rval;

	rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
	*val = ret;
	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
}

int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
		      int len, u32 val)
{
	struct pci_controller *hose = bus->sysdata;
	unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
		| (((bus->number - hose->first_busno) & 0xff) << 16)
		| (hose->index << 24);
	int rval;

	rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
			 addr, len, val);
	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
}

static struct pci_ops rtas_pci_ops =
{
	rtas_read_config,
	rtas_write_config
};

volatile struct Hydra __iomem *Hydra = NULL;

int __init
hydra_init(void)
{
	struct device_node *np;
	struct resource r;

	np = find_devices("mac-io");
	if (np == NULL || of_address_to_resource(np, 0, &r))
		return 0;
	Hydra = ioremap(r.start, r.end-r.start);
	printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start);
	printk("Hydra Feature_Control was %x",
	       in_le32(&Hydra->Feature_Control));
	out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
					   HYDRA_FC_SCSI_CELL_EN |
					   HYDRA_FC_SCCA_ENABLE |
					   HYDRA_FC_SCCB_ENABLE |
					   HYDRA_FC_ARB_BYPASS |
					   HYDRA_FC_MPIC_ENABLE |
					   HYDRA_FC_SLOW_SCC_PCLK |
					   HYDRA_FC_MPIC_IS_MASTER));
	printk(", now %x\n", in_le32(&Hydra->Feature_Control));
	return 1;
}

void __init
chrp_pcibios_fixup(void)
{
	struct pci_dev *dev = NULL;
	struct device_node *np;

	/* PCI interrupts are controlled by the OpenPIC */
	for_each_pci_dev(dev) {
		np = pci_device_to_OF_node(dev);
		if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
			dev->irq = np->intrs[0].line;
		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
	}
}

#define PRG_CL_RESET_VALID 0x00010000

static void __init
setup_python(struct pci_controller *hose, struct device_node *dev)
{
	u32 __iomem *reg;
	u32 val;
	struct resource r;

	if (of_address_to_resource(dev, 0, &r)) {
		printk(KERN_ERR "No address for Python PCI controller\n");
		return;
	}

	/* Clear the magic go-slow bit */
	reg = ioremap(r.start + 0xf6000, 0x40);
	BUG_ON(!reg); 
	val = in_be32(&reg[12]);
	if (val & PRG_CL_RESET_VALID) {
		out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
		in_be32(&reg[12]);
	}
	iounmap(reg);

	setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010);
}

/* Marvell Discovery II based Pegasos 2 */
static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
{
	struct device_node *root = find_path_device("/");
	struct device_node *rtas;

	of_node_get(root);
	rtas = of_find_node_by_name (root, "rtas");
	if (rtas) {
		hose->ops = &rtas_pci_ops;
		of_node_put(rtas);
	} else {
		printk ("RTAS supporting Pegasos OF not found, please upgrade"
			" your firmware\n");
	}
	pci_assign_all_buses = 1;
}

void __init
chrp_find_bridges(void)
{
	struct device_node *dev;
	int *bus_range;
	int len, index = -1;
	struct pci_controller *hose;
	unsigned int *dma;
	char *model, *machine;
	int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
	struct device_node *root = find_path_device("/");
	struct resource r;
	/*
	 * The PCI host bridge nodes on some machines don't have
	 * properties to adequately identify them, so we have to
	 * look at what sort of machine this is as well.
	 */
	machine = get_property(root, "model", NULL);
	if (machine != NULL) {
		is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
		is_mot = strncmp(machine, "MOT", 3) == 0;
		if (strncmp(machine, "Pegasos2", 8) == 0)
			is_pegasos = 2;
		else if (strncmp(machine, "Pegasos", 7) == 0)
			is_pegasos = 1;
	}
	for (dev = root->child; dev != NULL; dev = dev->sibling) {
		if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
			continue;
		++index;
		/* The GG2 bridge on the LongTrail doesn't have an address */
		if (of_address_to_resource(dev, 0, &r) && !is_longtrail) {
			printk(KERN_WARNING "Can't use %s: no address\n",
			       dev->full_name);
			continue;
		}
		bus_range = (int *) get_property(dev, "bus-range", &len);
		if (bus_range == NULL || len < 2 * sizeof(int)) {
			printk(KERN_WARNING "Can't get bus-range for %s\n",
				dev->full_name);
			continue;
		}
		if (bus_range[1] == bus_range[0])
			printk(KERN_INFO "PCI bus %d", bus_range[0]);
		else
			printk(KERN_INFO "PCI buses %d..%d",
			       bus_range[0], bus_range[1]);
		printk(" controlled by %s", dev->type);
		if (!is_longtrail)
			printk(" at %llx", (unsigned long long)r.start);
		printk("\n");

		hose = pcibios_alloc_controller();
		if (!hose) {
			printk("Can't allocate PCI controller structure for %s\n",
				dev->full_name);
			continue;
		}
		hose->arch_data = dev;
		hose->first_busno = bus_range[0];
		hose->last_busno = bus_range[1];

		model = get_property(dev, "model", NULL);
		if (model == NULL)
			model = "<none>";
		if (device_is_compatible(dev, "IBM,python")) {
			setup_python(hose, dev);
		} else if (is_mot
			   || strncmp(model, "Motorola, Grackle", 17) == 0) {
			setup_grackle(hose);
		} else if (is_longtrail) {
			void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
			hose->ops = &gg2_pci_ops;
			hose->cfg_data = p;
			gg2_pci_config_base = p;
		} else if (is_pegasos == 1) {
			setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
		} else if (is_pegasos == 2) {
			setup_peg2(hose, dev);
		} else {
			printk("No methods for %s (model %s), using RTAS\n",
			       dev->full_name, model);
			hose->ops = &rtas_pci_ops;
		}

		pci_process_bridge_OF_ranges(hose, dev, index == 0);

		/* check the first bridge for a property that we can
		   use to set pci_dram_offset */
		dma = (unsigned int *)
			get_property(dev, "ibm,dma-ranges", &len);
		if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
			pci_dram_offset = dma[2] - dma[3];
			printk("pci_dram_offset = %lx\n", pci_dram_offset);
		}
	}

	/* Do not fixup interrupts from OF tree on pegasos */
	if (is_pegasos)
		ppc_md.pcibios_fixup = NULL;
}
Commit	Line	Data
bbd0abda PM	1	/*
	2	* CHRP pci routines.
	3	*/
	4
bbd0abda PM	5	#include <linux/kernel.h>
	6	#include <linux/pci.h>
	7	#include <linux/delay.h>
	8	#include <linux/string.h>
	9	#include <linux/init.h>
	10	#include <linux/ide.h>
	11
	12	#include <asm/io.h>
	13	#include <asm/pgtable.h>
	14	#include <asm/irq.h>
	15	#include <asm/hydra.h>
	16	#include <asm/prom.h>
	17	#include <asm/gg2.h>
	18	#include <asm/machdep.h>
	19	#include <asm/sections.h>
	20	#include <asm/pci-bridge.h>
	21	#include <asm/open_pic.h>
	22	#include <asm/grackle.h>
	23	#include <asm/rtas.h>
	24
b86756ae PM	25	#include "chrp.h"
b86756ae PM	26
bbd0abda PM	27	/* LongTrail */
	28	void __iomem *gg2_pci_config_base;
	29
	30	/*
	31	* The VLSI Golden Gate II has only 512K of PCI configuration space, so we
	32	* limit the bus number to 3 bits
	33	*/
	34
	35	int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
	36	int len, u32 *val)
	37	{
	38	volatile void __iomem *cfg_data;
	39	struct pci_controller *hose = bus->sysdata;
	40
	41	if (bus->number > 7)
	42	return PCIBIOS_DEVICE_NOT_FOUND;
	43	/*
	44	* Note: the caller has already checked that off is
	45	* suitably aligned and that len is 1, 2 or 4.
	46	*/
	47	cfg_data = hose->cfg_data + ((bus->number<<16) \| (devfn<<8) \| off);
	48	switch (len) {
	49	case 1:
	50	*val = in_8(cfg_data);
	51	break;
	52	case 2:
	53	*val = in_le16(cfg_data);
	54	break;
	55	default:
	56	*val = in_le32(cfg_data);
	57	break;
	58	}
	59	return PCIBIOS_SUCCESSFUL;
	60	}
	61
	62	int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
	63	int len, u32 val)
	64	{
	65	volatile void __iomem *cfg_data;
	66	struct pci_controller *hose = bus->sysdata;
	67
	68	if (bus->number > 7)
	69	return PCIBIOS_DEVICE_NOT_FOUND;
	70	/*
	71	* Note: the caller has already checked that off is
	72	* suitably aligned and that len is 1, 2 or 4.
	73	*/
	74	cfg_data = hose->cfg_data + ((bus->number<<16) \| (devfn<<8) \| off);
	75	switch (len) {
	76	case 1:
	77	out_8(cfg_data, val);
	78	break;
	79	case 2:
	80	out_le16(cfg_data, val);
	81	break;
	82	default:
	83	out_le32(cfg_data, val);
	84	break;
	85	}
	86	return PCIBIOS_SUCCESSFUL;
	87	}
	88
	89	static struct pci_ops gg2_pci_ops =
	90	{
91	gg2_read_config,
92	gg2_write_config
93	};
94
95	/*
96	* Access functions for PCI config space using RTAS calls.
97	*/
98	int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
99	int len, u32 *val)
100	{
101	struct pci_controller *hose = bus->sysdata;
102	unsigned long addr = (offset & 0xff) \| ((devfn & 0xff) << 8)
103	\| (((bus->number - hose->first_busno) & 0xff) << 16)
104	\| (hose->index << 24);
105	int ret = -1;
106	int rval;
107
108	rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
109	*val = ret;
110	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
111	}
112
113	int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
114	int len, u32 val)
115	{
116	struct pci_controller *hose = bus->sysdata;
117	unsigned long addr = (offset & 0xff) \| ((devfn & 0xff) << 8)
118	\| (((bus->number - hose->first_busno) & 0xff) << 16)
119	\| (hose->index << 24);
120	int rval;
121
122	rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
123	addr, len, val);
124	return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
125	}
126
127	static struct pci_ops rtas_pci_ops =
128	{
129	rtas_read_config,
130	rtas_write_config
131	};
132
133	volatile struct Hydra __iomem *Hydra = NULL;
134
135	int __init
136	hydra_init(void)
137	{
138	struct device_node *np;
575e3216	139	struct resource r;
bbd0abda PM	140
bbd0abda PM	141	np = find_devices("mac-io");
575e3216	142	if (np == NULL \|\| of_address_to_resource(np, 0, &r))
bbd0abda	143	return 0;
575e3216	144	Hydra = ioremap(r.start, r.end-r.start);
685143ac	145	printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start);
bbd0abda PM	146	printk("Hydra Feature_Control was %x",
	147	in_le32(&Hydra->Feature_Control));
	148	out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN \|
	149	HYDRA_FC_SCSI_CELL_EN \|
	150	HYDRA_FC_SCCA_ENABLE \|
	151	HYDRA_FC_SCCB_ENABLE \|
	152	HYDRA_FC_ARB_BYPASS \|
	153	HYDRA_FC_MPIC_ENABLE \|
	154	HYDRA_FC_SLOW_SCC_PCLK \|
	155	HYDRA_FC_MPIC_IS_MASTER));
	156	printk(", now %x\n", in_le32(&Hydra->Feature_Control));
	157	return 1;
	158	}
	159
	160	void __init
	161	chrp_pcibios_fixup(void)
	162	{
	163	struct pci_dev *dev = NULL;
	164	struct device_node *np;
	165
	166	/* PCI interrupts are controlled by the OpenPIC */
	167	for_each_pci_dev(dev) {
	168	np = pci_device_to_OF_node(dev);
	169	if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
	170	dev->irq = np->intrs[0].line;
	171	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
	172	}
	173	}
	174
	175	#define PRG_CL_RESET_VALID 0x00010000
	176
	177	static void __init
	178	setup_python(struct pci_controller hose, struct device_node dev)
	179	{
	180	u32 __iomem *reg;
	181	u32 val;
575e3216	182	struct resource r;
bbd0abda	183
575e3216 DW	184	if (of_address_to_resource(dev, 0, &r)) {
	185	printk(KERN_ERR "No address for Python PCI controller\n");
	186	return;
	187	}
bbd0abda PM	188
bbd0abda PM	189	/* Clear the magic go-slow bit */
575e3216 DW	190	reg = ioremap(r.start + 0xf6000, 0x40);
575e3216 DW	191	BUG_ON(!reg);
bbd0abda PM	192	val = in_be32(&reg[12]);
	193	if (val & PRG_CL_RESET_VALID) {
	194	out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
	195	in_be32(&reg[12]);
	196	}
	197	iounmap(reg);
575e3216 DW	198
575e3216 DW	199	setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010);
bbd0abda PM	200	}
	201
	202	/* Marvell Discovery II based Pegasos 2 */
	203	static void __init setup_peg2(struct pci_controller hose, struct device_node dev)
	204	{
	205	struct device_node *root = find_path_device("/");
	206	struct device_node *rtas;
	207
d60dcd94	208	of_node_get(root);
bbd0abda PM	209	rtas = of_find_node_by_name (root, "rtas");
	210	if (rtas) {
	211	hose->ops = &rtas_pci_ops;
d60dcd94	212	of_node_put(rtas);
bbd0abda PM	213	} else {
	214	printk ("RTAS supporting Pegasos OF not found, please upgrade"
	215	" your firmware\n");
	216	}
	217	pci_assign_all_buses = 1;
	218	}
	219
	220	void __init
	221	chrp_find_bridges(void)
	222	{
	223	struct device_node *dev;
	224	int *bus_range;
	225	int len, index = -1;
	226	struct pci_controller *hose;
	227	unsigned int *dma;
	228	char model, machine;
	229	int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
	230	struct device_node *root = find_path_device("/");
575e3216	231	struct resource r;
bbd0abda PM	232	/*
	233	* The PCI host bridge nodes on some machines don't have
	234	* properties to adequately identify them, so we have to
	235	* look at what sort of machine this is as well.
	236	*/
	237	machine = get_property(root, "model", NULL);
	238	if (machine != NULL) {
	239	is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
	240	is_mot = strncmp(machine, "MOT", 3) == 0;
	241	if (strncmp(machine, "Pegasos2", 8) == 0)
	242	is_pegasos = 2;
	243	else if (strncmp(machine, "Pegasos", 7) == 0)
	244	is_pegasos = 1;
	245	}
	246	for (dev = root->child; dev != NULL; dev = dev->sibling) {
	247	if (dev->type == NULL \|\| strcmp(dev->type, "pci") != 0)
	248	continue;
	249	++index;
	250	/* The GG2 bridge on the LongTrail doesn't have an address */
575e3216	251	if (of_address_to_resource(dev, 0, &r) && !is_longtrail) {
bbd0abda PM	252	printk(KERN_WARNING "Can't use %s: no address\n",
	253	dev->full_name);
	254	continue;
	255	}
	256	bus_range = (int *) get_property(dev, "bus-range", &len);
	257	if (bus_range == NULL \|\| len < 2 * sizeof(int)) {
	258	printk(KERN_WARNING "Can't get bus-range for %s\n",
	259	dev->full_name);
	260	continue;
	261	}
	262	if (bus_range[1] == bus_range[0])
	263	printk(KERN_INFO "PCI bus %d", bus_range[0]);
	264	else
	265	printk(KERN_INFO "PCI buses %d..%d",
	266	bus_range[0], bus_range[1]);
	267	printk(" controlled by %s", dev->type);
575e3216	268	if (!is_longtrail)
685143ac	269	printk(" at %llx", (unsigned long long)r.start);
bbd0abda PM	270	printk("\n");
	271
	272	hose = pcibios_alloc_controller();
	273	if (!hose) {
	274	printk("Can't allocate PCI controller structure for %s\n",
	275	dev->full_name);
	276	continue;
	277	}
	278	hose->arch_data = dev;
	279	hose->first_busno = bus_range[0];
	280	hose->last_busno = bus_range[1];
	281
	282	model = get_property(dev, "model", NULL);
	283	if (model == NULL)
	284	model = "<none>";
	285	if (device_is_compatible(dev, "IBM,python")) {
	286	setup_python(hose, dev);
	287	} else if (is_mot
	288	\|\| strncmp(model, "Motorola, Grackle", 17) == 0) {
	289	setup_grackle(hose);
	290	} else if (is_longtrail) {
	291	void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
	292	hose->ops = &gg2_pci_ops;
	293	hose->cfg_data = p;
	294	gg2_pci_config_base = p;
	295	} else if (is_pegasos == 1) {
	296	setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
	297	} else if (is_pegasos == 2) {
	298	setup_peg2(hose, dev);
	299	} else {
	300	printk("No methods for %s (model %s), using RTAS\n",
	301	dev->full_name, model);
	302	hose->ops = &rtas_pci_ops;
	303	}
	304
	305	pci_process_bridge_OF_ranges(hose, dev, index == 0);
	306
	307	/* check the first bridge for a property that we can
	308	use to set pci_dram_offset */
	309	dma = (unsigned int *)
	310	get_property(dev, "ibm,dma-ranges", &len);
	311	if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
	312	pci_dram_offset = dma[2] - dma[3];
	313	printk("pci_dram_offset = %lx\n", pci_dram_offset);
	314	}
	315	}
	316
	317	/* Do not fixup interrupts from OF tree on pegasos */
b86756ae PM	318	if (is_pegasos)
b86756ae PM	319	ppc_md.pcibios_fixup = NULL;
bbd0abda	320	}