Commit | Line | Data |
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bbd0abda PM |
1 | /* |
2 | * CHRP pci routines. | |
3 | */ | |
4 | ||
bbd0abda PM |
5 | #include <linux/kernel.h> |
6 | #include <linux/pci.h> | |
7 | #include <linux/delay.h> | |
8 | #include <linux/string.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/ide.h> | |
11 | ||
12 | #include <asm/io.h> | |
13 | #include <asm/pgtable.h> | |
14 | #include <asm/irq.h> | |
15 | #include <asm/hydra.h> | |
16 | #include <asm/prom.h> | |
17 | #include <asm/gg2.h> | |
18 | #include <asm/machdep.h> | |
19 | #include <asm/sections.h> | |
20 | #include <asm/pci-bridge.h> | |
bbd0abda PM |
21 | #include <asm/grackle.h> |
22 | #include <asm/rtas.h> | |
23 | ||
b86756ae PM |
24 | #include "chrp.h" |
25 | ||
bbd0abda PM |
26 | /* LongTrail */ |
27 | void __iomem *gg2_pci_config_base; | |
28 | ||
29 | /* | |
30 | * The VLSI Golden Gate II has only 512K of PCI configuration space, so we | |
31 | * limit the bus number to 3 bits | |
32 | */ | |
33 | ||
34 | int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off, | |
35 | int len, u32 *val) | |
36 | { | |
37 | volatile void __iomem *cfg_data; | |
38 | struct pci_controller *hose = bus->sysdata; | |
39 | ||
40 | if (bus->number > 7) | |
41 | return PCIBIOS_DEVICE_NOT_FOUND; | |
42 | /* | |
43 | * Note: the caller has already checked that off is | |
44 | * suitably aligned and that len is 1, 2 or 4. | |
45 | */ | |
46 | cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); | |
47 | switch (len) { | |
48 | case 1: | |
49 | *val = in_8(cfg_data); | |
50 | break; | |
51 | case 2: | |
52 | *val = in_le16(cfg_data); | |
53 | break; | |
54 | default: | |
55 | *val = in_le32(cfg_data); | |
56 | break; | |
57 | } | |
58 | return PCIBIOS_SUCCESSFUL; | |
59 | } | |
60 | ||
61 | int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off, | |
62 | int len, u32 val) | |
63 | { | |
64 | volatile void __iomem *cfg_data; | |
65 | struct pci_controller *hose = bus->sysdata; | |
66 | ||
67 | if (bus->number > 7) | |
68 | return PCIBIOS_DEVICE_NOT_FOUND; | |
69 | /* | |
70 | * Note: the caller has already checked that off is | |
71 | * suitably aligned and that len is 1, 2 or 4. | |
72 | */ | |
73 | cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); | |
74 | switch (len) { | |
75 | case 1: | |
76 | out_8(cfg_data, val); | |
77 | break; | |
78 | case 2: | |
79 | out_le16(cfg_data, val); | |
80 | break; | |
81 | default: | |
82 | out_le32(cfg_data, val); | |
83 | break; | |
84 | } | |
85 | return PCIBIOS_SUCCESSFUL; | |
86 | } | |
87 | ||
88 | static struct pci_ops gg2_pci_ops = | |
89 | { | |
90 | gg2_read_config, | |
91 | gg2_write_config | |
92 | }; | |
93 | ||
94 | /* | |
95 | * Access functions for PCI config space using RTAS calls. | |
96 | */ | |
97 | int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
98 | int len, u32 *val) | |
99 | { | |
100 | struct pci_controller *hose = bus->sysdata; | |
101 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) | |
102 | | (((bus->number - hose->first_busno) & 0xff) << 16) | |
103 | | (hose->index << 24); | |
104 | int ret = -1; | |
105 | int rval; | |
106 | ||
107 | rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len); | |
108 | *val = ret; | |
109 | return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; | |
110 | } | |
111 | ||
112 | int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
113 | int len, u32 val) | |
114 | { | |
115 | struct pci_controller *hose = bus->sysdata; | |
116 | unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) | |
117 | | (((bus->number - hose->first_busno) & 0xff) << 16) | |
118 | | (hose->index << 24); | |
119 | int rval; | |
120 | ||
121 | rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL, | |
122 | addr, len, val); | |
123 | return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; | |
124 | } | |
125 | ||
126 | static struct pci_ops rtas_pci_ops = | |
127 | { | |
128 | rtas_read_config, | |
129 | rtas_write_config | |
130 | }; | |
131 | ||
132 | volatile struct Hydra __iomem *Hydra = NULL; | |
133 | ||
134 | int __init | |
135 | hydra_init(void) | |
136 | { | |
137 | struct device_node *np; | |
575e3216 | 138 | struct resource r; |
bbd0abda PM |
139 | |
140 | np = find_devices("mac-io"); | |
575e3216 | 141 | if (np == NULL || of_address_to_resource(np, 0, &r)) |
bbd0abda | 142 | return 0; |
575e3216 | 143 | Hydra = ioremap(r.start, r.end-r.start); |
685143ac | 144 | printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start); |
bbd0abda PM |
145 | printk("Hydra Feature_Control was %x", |
146 | in_le32(&Hydra->Feature_Control)); | |
147 | out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN | | |
148 | HYDRA_FC_SCSI_CELL_EN | | |
149 | HYDRA_FC_SCCA_ENABLE | | |
150 | HYDRA_FC_SCCB_ENABLE | | |
151 | HYDRA_FC_ARB_BYPASS | | |
152 | HYDRA_FC_MPIC_ENABLE | | |
153 | HYDRA_FC_SLOW_SCC_PCLK | | |
154 | HYDRA_FC_MPIC_IS_MASTER)); | |
155 | printk(", now %x\n", in_le32(&Hydra->Feature_Control)); | |
156 | return 1; | |
157 | } | |
158 | ||
159 | void __init | |
160 | chrp_pcibios_fixup(void) | |
161 | { | |
162 | struct pci_dev *dev = NULL; | |
bbd0abda | 163 | |
0ebfff14 BH |
164 | for_each_pci_dev(dev) |
165 | pci_read_irq_line(dev); | |
bbd0abda PM |
166 | } |
167 | ||
168 | #define PRG_CL_RESET_VALID 0x00010000 | |
169 | ||
170 | static void __init | |
171 | setup_python(struct pci_controller *hose, struct device_node *dev) | |
172 | { | |
173 | u32 __iomem *reg; | |
174 | u32 val; | |
575e3216 | 175 | struct resource r; |
bbd0abda | 176 | |
575e3216 DW |
177 | if (of_address_to_resource(dev, 0, &r)) { |
178 | printk(KERN_ERR "No address for Python PCI controller\n"); | |
179 | return; | |
180 | } | |
bbd0abda PM |
181 | |
182 | /* Clear the magic go-slow bit */ | |
575e3216 DW |
183 | reg = ioremap(r.start + 0xf6000, 0x40); |
184 | BUG_ON(!reg); | |
bbd0abda PM |
185 | val = in_be32(®[12]); |
186 | if (val & PRG_CL_RESET_VALID) { | |
187 | out_be32(®[12], val & ~PRG_CL_RESET_VALID); | |
188 | in_be32(®[12]); | |
189 | } | |
190 | iounmap(reg); | |
575e3216 DW |
191 | |
192 | setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); | |
bbd0abda PM |
193 | } |
194 | ||
195 | /* Marvell Discovery II based Pegasos 2 */ | |
196 | static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev) | |
197 | { | |
198 | struct device_node *root = find_path_device("/"); | |
199 | struct device_node *rtas; | |
200 | ||
d60dcd94 | 201 | of_node_get(root); |
bbd0abda PM |
202 | rtas = of_find_node_by_name (root, "rtas"); |
203 | if (rtas) { | |
204 | hose->ops = &rtas_pci_ops; | |
d60dcd94 | 205 | of_node_put(rtas); |
bbd0abda PM |
206 | } else { |
207 | printk ("RTAS supporting Pegasos OF not found, please upgrade" | |
208 | " your firmware\n"); | |
209 | } | |
210 | pci_assign_all_buses = 1; | |
211 | } | |
212 | ||
213 | void __init | |
214 | chrp_find_bridges(void) | |
215 | { | |
216 | struct device_node *dev; | |
217 | int *bus_range; | |
218 | int len, index = -1; | |
219 | struct pci_controller *hose; | |
220 | unsigned int *dma; | |
221 | char *model, *machine; | |
222 | int is_longtrail = 0, is_mot = 0, is_pegasos = 0; | |
223 | struct device_node *root = find_path_device("/"); | |
575e3216 | 224 | struct resource r; |
bbd0abda PM |
225 | /* |
226 | * The PCI host bridge nodes on some machines don't have | |
227 | * properties to adequately identify them, so we have to | |
228 | * look at what sort of machine this is as well. | |
229 | */ | |
230 | machine = get_property(root, "model", NULL); | |
231 | if (machine != NULL) { | |
232 | is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0; | |
233 | is_mot = strncmp(machine, "MOT", 3) == 0; | |
234 | if (strncmp(machine, "Pegasos2", 8) == 0) | |
235 | is_pegasos = 2; | |
236 | else if (strncmp(machine, "Pegasos", 7) == 0) | |
237 | is_pegasos = 1; | |
238 | } | |
239 | for (dev = root->child; dev != NULL; dev = dev->sibling) { | |
240 | if (dev->type == NULL || strcmp(dev->type, "pci") != 0) | |
241 | continue; | |
242 | ++index; | |
243 | /* The GG2 bridge on the LongTrail doesn't have an address */ | |
575e3216 | 244 | if (of_address_to_resource(dev, 0, &r) && !is_longtrail) { |
bbd0abda PM |
245 | printk(KERN_WARNING "Can't use %s: no address\n", |
246 | dev->full_name); | |
247 | continue; | |
248 | } | |
249 | bus_range = (int *) get_property(dev, "bus-range", &len); | |
250 | if (bus_range == NULL || len < 2 * sizeof(int)) { | |
251 | printk(KERN_WARNING "Can't get bus-range for %s\n", | |
252 | dev->full_name); | |
253 | continue; | |
254 | } | |
255 | if (bus_range[1] == bus_range[0]) | |
256 | printk(KERN_INFO "PCI bus %d", bus_range[0]); | |
257 | else | |
258 | printk(KERN_INFO "PCI buses %d..%d", | |
259 | bus_range[0], bus_range[1]); | |
260 | printk(" controlled by %s", dev->type); | |
575e3216 | 261 | if (!is_longtrail) |
685143ac | 262 | printk(" at %llx", (unsigned long long)r.start); |
bbd0abda PM |
263 | printk("\n"); |
264 | ||
265 | hose = pcibios_alloc_controller(); | |
266 | if (!hose) { | |
267 | printk("Can't allocate PCI controller structure for %s\n", | |
268 | dev->full_name); | |
269 | continue; | |
270 | } | |
271 | hose->arch_data = dev; | |
272 | hose->first_busno = bus_range[0]; | |
273 | hose->last_busno = bus_range[1]; | |
274 | ||
275 | model = get_property(dev, "model", NULL); | |
276 | if (model == NULL) | |
277 | model = "<none>"; | |
278 | if (device_is_compatible(dev, "IBM,python")) { | |
279 | setup_python(hose, dev); | |
280 | } else if (is_mot | |
281 | || strncmp(model, "Motorola, Grackle", 17) == 0) { | |
282 | setup_grackle(hose); | |
283 | } else if (is_longtrail) { | |
284 | void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000); | |
285 | hose->ops = &gg2_pci_ops; | |
286 | hose->cfg_data = p; | |
287 | gg2_pci_config_base = p; | |
288 | } else if (is_pegasos == 1) { | |
289 | setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); | |
290 | } else if (is_pegasos == 2) { | |
291 | setup_peg2(hose, dev); | |
292 | } else { | |
293 | printk("No methods for %s (model %s), using RTAS\n", | |
294 | dev->full_name, model); | |
295 | hose->ops = &rtas_pci_ops; | |
296 | } | |
297 | ||
298 | pci_process_bridge_OF_ranges(hose, dev, index == 0); | |
299 | ||
300 | /* check the first bridge for a property that we can | |
301 | use to set pci_dram_offset */ | |
302 | dma = (unsigned int *) | |
303 | get_property(dev, "ibm,dma-ranges", &len); | |
304 | if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) { | |
305 | pci_dram_offset = dma[2] - dma[3]; | |
306 | printk("pci_dram_offset = %lx\n", pci_dram_offset); | |
307 | } | |
308 | } | |
309 | ||
310 | /* Do not fixup interrupts from OF tree on pegasos */ | |
b86756ae PM |
311 | if (is_pegasos) |
312 | ppc_md.pcibios_fixup = NULL; | |
bbd0abda | 313 | } |