[linux-2.6-block.git] / arch / powerpc / platforms / cell / spufs / hw_ops.c

/* hw_ops.c - query/set operations on active SPU context.
 *
 * Copyright (C) IBM 2005
 * Author: Mark Nutter <mnutter@us.ibm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/poll.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <linux/stddef.h>
#include <linux/unistd.h>

#include <asm/io.h>
#include <asm/spu.h>
#include <asm/spu_csa.h>
#include <asm/mmu_context.h>
#include "spufs.h"

static int spu_hw_mbox_read(struct spu_context *ctx, u32 * data)
{
	struct spu *spu = ctx->spu;
	struct spu_problem __iomem *prob = spu->problem;
	u32 mbox_stat;
	int ret = 0;

	spin_lock_irq(&spu->register_lock);
	mbox_stat = in_be32(&prob->mb_stat_R);
	if (mbox_stat & 0x0000ff) {
		*data = in_be32(&prob->pu_mb_R);
		ret = 4;
	}
	spin_unlock_irq(&spu->register_lock);
	return ret;
}

static u32 spu_hw_mbox_stat_read(struct spu_context *ctx)
{
	return in_be32(&ctx->spu->problem->mb_stat_R);
}

static unsigned int spu_hw_mbox_stat_poll(struct spu_context *ctx,
					  unsigned int events)
{
	struct spu *spu = ctx->spu;
	int ret = 0;
	u32 stat;

	spin_lock_irq(&spu->register_lock);
	stat = in_be32(&spu->problem->mb_stat_R);

	/* if the requested event is there, return the poll
	   mask, otherwise enable the interrupt to get notified,
	   but first mark any pending interrupts as done so
	   we don't get woken up unnecessarily */

	if (events & (POLLIN | POLLRDNORM)) {
		if (stat & 0xff0000)
			ret |= POLLIN | POLLRDNORM;
		else {
			spu_int_stat_clear(spu, 2, 0x1);
			spu_int_mask_or(spu, 2, 0x1);
		}
	}
	if (events & (POLLOUT | POLLWRNORM)) {
		if (stat & 0x00ff00)
			ret = POLLOUT | POLLWRNORM;
		else {
			spu_int_stat_clear(spu, 2, 0x10);
			spu_int_mask_or(spu, 2, 0x10);
		}
	}
	spin_unlock_irq(&spu->register_lock);
	return ret;
}

static int spu_hw_ibox_read(struct spu_context *ctx, u32 * data)
{
	struct spu *spu = ctx->spu;
	struct spu_problem __iomem *prob = spu->problem;
	struct spu_priv2 __iomem *priv2 = spu->priv2;
	int ret;

	spin_lock_irq(&spu->register_lock);
	if (in_be32(&prob->mb_stat_R) & 0xff0000) {
		/* read the first available word */
		*data = in_be64(&priv2->puint_mb_R);
		ret = 4;
	} else {
		/* make sure we get woken up by the interrupt */
		spu_int_mask_or(spu, 2, 0x1);
		ret = 0;
	}
	spin_unlock_irq(&spu->register_lock);
	return ret;
}

static int spu_hw_wbox_write(struct spu_context *ctx, u32 data)
{
	struct spu *spu = ctx->spu;
	struct spu_problem __iomem *prob = spu->problem;
	int ret;

	spin_lock_irq(&spu->register_lock);
	if (in_be32(&prob->mb_stat_R) & 0x00ff00) {
		/* we have space to write wbox_data to */
		out_be32(&prob->spu_mb_W, data);
		ret = 4;
	} else {
		/* make sure we get woken up by the interrupt when space
		   becomes available */
		spu_int_mask_or(spu, 2, 0x10);
		ret = 0;
	}
	spin_unlock_irq(&spu->register_lock);
	return ret;
}

static u32 spu_hw_signal1_read(struct spu_context *ctx)
{
	return in_be32(&ctx->spu->problem->signal_notify1);
}

static void spu_hw_signal1_write(struct spu_context *ctx, u32 data)
{
	out_be32(&ctx->spu->problem->signal_notify1, data);
}

static u32 spu_hw_signal2_read(struct spu_context *ctx)
{
	return in_be32(&ctx->spu->problem->signal_notify1);
}

static void spu_hw_signal2_write(struct spu_context *ctx, u32 data)
{
	out_be32(&ctx->spu->problem->signal_notify2, data);
}

static void spu_hw_signal1_type_set(struct spu_context *ctx, u64 val)
{
	struct spu *spu = ctx->spu;
	struct spu_priv2 __iomem *priv2 = spu->priv2;
	u64 tmp;

	spin_lock_irq(&spu->register_lock);
	tmp = in_be64(&priv2->spu_cfg_RW);
	if (val)
		tmp |= 1;
	else
		tmp &= ~1;
	out_be64(&priv2->spu_cfg_RW, tmp);
	spin_unlock_irq(&spu->register_lock);
}

static u64 spu_hw_signal1_type_get(struct spu_context *ctx)
{
	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);
}

static void spu_hw_signal2_type_set(struct spu_context *ctx, u64 val)
{
	struct spu *spu = ctx->spu;
	struct spu_priv2 __iomem *priv2 = spu->priv2;
	u64 tmp;

	spin_lock_irq(&spu->register_lock);
	tmp = in_be64(&priv2->spu_cfg_RW);
	if (val)
		tmp |= 2;
	else
		tmp &= ~2;
	out_be64(&priv2->spu_cfg_RW, tmp);
	spin_unlock_irq(&spu->register_lock);
}

static u64 spu_hw_signal2_type_get(struct spu_context *ctx)
{
	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);
}

static u32 spu_hw_npc_read(struct spu_context *ctx)
{
	return in_be32(&ctx->spu->problem->spu_npc_RW);
}

static void spu_hw_npc_write(struct spu_context *ctx, u32 val)
{
	out_be32(&ctx->spu->problem->spu_npc_RW, val);
}

static u32 spu_hw_status_read(struct spu_context *ctx)
{
	return in_be32(&ctx->spu->problem->spu_status_R);
}

static char *spu_hw_get_ls(struct spu_context *ctx)
{
	return ctx->spu->local_store;
}

static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val)
{
	eieio();
	out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
}

static void spu_hw_runcntl_stop(struct spu_context *ctx)
{
	spin_lock_irq(&ctx->spu->register_lock);
	out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);
	while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)
		cpu_relax();
	spin_unlock_irq(&ctx->spu->register_lock);
}

static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode)
{
	struct spu_problem *prob = ctx->spu->problem;
	int ret;

	spin_lock_irq(&ctx->spu->register_lock);
	ret = -EAGAIN;
	if (in_be32(&prob->dma_querytype_RW))
		goto out;
	ret = 0;
	out_be32(&prob->dma_querymask_RW, mask);
	out_be32(&prob->dma_querytype_RW, mode);
out:
	spin_unlock_irq(&ctx->spu->register_lock);
	return ret;
}

static u32 spu_hw_read_mfc_tagstatus(struct spu_context * ctx)
{
	return in_be32(&ctx->spu->problem->dma_tagstatus_R);
}

static u32 spu_hw_get_mfc_free_elements(struct spu_context *ctx)
{
	return in_be32(&ctx->spu->problem->dma_qstatus_R);
}

static int spu_hw_send_mfc_command(struct spu_context *ctx,
					struct mfc_dma_command *cmd)
{
	u32 status;
	struct spu_problem *prob = ctx->spu->problem;

	spin_lock_irq(&ctx->spu->register_lock);
	out_be32(&prob->mfc_lsa_W, cmd->lsa);
	out_be64(&prob->mfc_ea_W, cmd->ea);
	out_be32(&prob->mfc_union_W.by32.mfc_size_tag32,
				cmd->size << 16 | cmd->tag);
	out_be32(&prob->mfc_union_W.by32.mfc_class_cmd32,
				cmd->class << 16 | cmd->cmd);
	status = in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
	spin_unlock_irq(&ctx->spu->register_lock);

	switch (status & 0xffff) {
	case 0:
		return 0;
	case 2:
		return -EAGAIN;
	default:
		return -EINVAL;
	}
}

struct spu_context_ops spu_hw_ops = {
	.mbox_read = spu_hw_mbox_read,
	.mbox_stat_read = spu_hw_mbox_stat_read,
	.mbox_stat_poll = spu_hw_mbox_stat_poll,
	.ibox_read = spu_hw_ibox_read,
	.wbox_write = spu_hw_wbox_write,
	.signal1_read = spu_hw_signal1_read,
	.signal1_write = spu_hw_signal1_write,
	.signal2_read = spu_hw_signal2_read,
	.signal2_write = spu_hw_signal2_write,
	.signal1_type_set = spu_hw_signal1_type_set,
	.signal1_type_get = spu_hw_signal1_type_get,
	.signal2_type_set = spu_hw_signal2_type_set,
	.signal2_type_get = spu_hw_signal2_type_get,
	.npc_read = spu_hw_npc_read,
	.npc_write = spu_hw_npc_write,
	.status_read = spu_hw_status_read,
	.get_ls = spu_hw_get_ls,
	.runcntl_write = spu_hw_runcntl_write,
	.runcntl_stop = spu_hw_runcntl_stop,
	.set_mfc_query = spu_hw_set_mfc_query,
	.read_mfc_tagstatus = spu_hw_read_mfc_tagstatus,
	.get_mfc_free_elements = spu_hw_get_mfc_free_elements,
	.send_mfc_command = spu_hw_send_mfc_command,
};
Commit	Line	Data
8b3d6663 AB	1	/* hw_ops.c - query/set operations on active SPU context.
	2	*
	3	* Copyright (C) IBM 2005
	4	* Author: Mark Nutter <mnutter@us.ibm.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2, or (at your option)
	9	* any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#include <linux/config.h>
	22	#include <linux/module.h>
	23	#include <linux/errno.h>
	24	#include <linux/sched.h>
	25	#include <linux/kernel.h>
	26	#include <linux/mm.h>
3a843d7c	27	#include <linux/poll.h>
8b3d6663 AB	28	#include <linux/smp.h>
	29	#include <linux/smp_lock.h>
	30	#include <linux/stddef.h>
	31	#include <linux/unistd.h>
	32
	33	#include <asm/io.h>
	34	#include <asm/spu.h>
	35	#include <asm/spu_csa.h>
	36	#include <asm/mmu_context.h>
	37	#include "spufs.h"
	38
	39	static int spu_hw_mbox_read(struct spu_context ctx, u32 data)
	40	{
	41	struct spu *spu = ctx->spu;
	42	struct spu_problem __iomem *prob = spu->problem;
	43	u32 mbox_stat;
	44	int ret = 0;
	45
	46	spin_lock_irq(&spu->register_lock);
	47	mbox_stat = in_be32(&prob->mb_stat_R);
	48	if (mbox_stat & 0x0000ff) {
	49	*data = in_be32(&prob->pu_mb_R);
	50	ret = 4;
	51	}
	52	spin_unlock_irq(&spu->register_lock);
	53	return ret;
	54	}
	55
	56	static u32 spu_hw_mbox_stat_read(struct spu_context *ctx)
	57	{
	58	return in_be32(&ctx->spu->problem->mb_stat_R);
	59	}
	60
3a843d7c AB	61	static unsigned int spu_hw_mbox_stat_poll(struct spu_context *ctx,
	62	unsigned int events)
	63	{
	64	struct spu *spu = ctx->spu;
3a843d7c AB	65	int ret = 0;
	66	u32 stat;
	67
	68	spin_lock_irq(&spu->register_lock);
	69	stat = in_be32(&spu->problem->mb_stat_R);
	70
	71	/* if the requested event is there, return the poll
	72	mask, otherwise enable the interrupt to get notified,
	73	but first mark any pending interrupts as done so
	74	we don't get woken up unnecessarily */
	75
	76	if (events & (POLLIN \| POLLRDNORM)) {
	77	if (stat & 0xff0000)
	78	ret \|= POLLIN \| POLLRDNORM;
	79	else {
f0831acc AB	80	spu_int_stat_clear(spu, 2, 0x1);
f0831acc AB	81	spu_int_mask_or(spu, 2, 0x1);
3a843d7c AB	82	}
	83	}
	84	if (events & (POLLOUT \| POLLWRNORM)) {
	85	if (stat & 0x00ff00)
	86	ret = POLLOUT \| POLLWRNORM;
	87	else {
f0831acc AB	88	spu_int_stat_clear(spu, 2, 0x10);
f0831acc AB	89	spu_int_mask_or(spu, 2, 0x10);
3a843d7c AB	90	}
	91	}
	92	spin_unlock_irq(&spu->register_lock);
	93	return ret;
	94	}
	95
8b3d6663 AB	96	static int spu_hw_ibox_read(struct spu_context ctx, u32 data)
	97	{
	98	struct spu *spu = ctx->spu;
	99	struct spu_problem __iomem *prob = spu->problem;
8b3d6663 AB	100	struct spu_priv2 __iomem *priv2 = spu->priv2;
	101	int ret;
	102
	103	spin_lock_irq(&spu->register_lock);
	104	if (in_be32(&prob->mb_stat_R) & 0xff0000) {
	105	/* read the first available word */
	106	*data = in_be64(&priv2->puint_mb_R);
	107	ret = 4;
	108	} else {
	109	/* make sure we get woken up by the interrupt */
f0831acc	110	spu_int_mask_or(spu, 2, 0x1);
8b3d6663 AB	111	ret = 0;
	112	}
	113	spin_unlock_irq(&spu->register_lock);
	114	return ret;
	115	}
	116
	117	static int spu_hw_wbox_write(struct spu_context *ctx, u32 data)
	118	{
	119	struct spu *spu = ctx->spu;
	120	struct spu_problem __iomem *prob = spu->problem;
8b3d6663 AB	121	int ret;
	122
	123	spin_lock_irq(&spu->register_lock);
	124	if (in_be32(&prob->mb_stat_R) & 0x00ff00) {
	125	/* we have space to write wbox_data to */
	126	out_be32(&prob->spu_mb_W, data);
	127	ret = 4;
	128	} else {
	129	/* make sure we get woken up by the interrupt when space
	130	becomes available */
f0831acc	131	spu_int_mask_or(spu, 2, 0x10);
8b3d6663 AB	132	ret = 0;
	133	}
	134	spin_unlock_irq(&spu->register_lock);
	135	return ret;
	136	}
	137
	138	static u32 spu_hw_signal1_read(struct spu_context *ctx)
	139	{
	140	return in_be32(&ctx->spu->problem->signal_notify1);
	141	}
	142
	143	static void spu_hw_signal1_write(struct spu_context *ctx, u32 data)
	144	{
	145	out_be32(&ctx->spu->problem->signal_notify1, data);
	146	}
	147
	148	static u32 spu_hw_signal2_read(struct spu_context *ctx)
	149	{
	150	return in_be32(&ctx->spu->problem->signal_notify1);
	151	}
	152
	153	static void spu_hw_signal2_write(struct spu_context *ctx, u32 data)
	154	{
	155	out_be32(&ctx->spu->problem->signal_notify2, data);
	156	}
	157
	158	static void spu_hw_signal1_type_set(struct spu_context *ctx, u64 val)
	159	{
	160	struct spu *spu = ctx->spu;
	161	struct spu_priv2 __iomem *priv2 = spu->priv2;
	162	u64 tmp;
	163
	164	spin_lock_irq(&spu->register_lock);
	165	tmp = in_be64(&priv2->spu_cfg_RW);
	166	if (val)
	167	tmp \|= 1;
	168	else
	169	tmp &= ~1;
	170	out_be64(&priv2->spu_cfg_RW, tmp);
	171	spin_unlock_irq(&spu->register_lock);
	172	}
	173
	174	static u64 spu_hw_signal1_type_get(struct spu_context *ctx)
	175	{
	176	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);
	177	}
	178
	179	static void spu_hw_signal2_type_set(struct spu_context *ctx, u64 val)
	180	{
	181	struct spu *spu = ctx->spu;
	182	struct spu_priv2 __iomem *priv2 = spu->priv2;
	183	u64 tmp;
	184
	185	spin_lock_irq(&spu->register_lock);
	186	tmp = in_be64(&priv2->spu_cfg_RW);
	187	if (val)
	188	tmp \|= 2;
	189	else
	190	tmp &= ~2;
	191	out_be64(&priv2->spu_cfg_RW, tmp);
	192	spin_unlock_irq(&spu->register_lock);
	193	}
	194
	195	static u64 spu_hw_signal2_type_get(struct spu_context *ctx)
196	{
197	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);
198	}
199
200	static u32 spu_hw_npc_read(struct spu_context *ctx)
201	{
202	return in_be32(&ctx->spu->problem->spu_npc_RW);
203	}
204
205	static void spu_hw_npc_write(struct spu_context *ctx, u32 val)
206	{
207	out_be32(&ctx->spu->problem->spu_npc_RW, val);
208	}
209
210	static u32 spu_hw_status_read(struct spu_context *ctx)
211	{
212	return in_be32(&ctx->spu->problem->spu_status_R);
213	}
214
215	static char spu_hw_get_ls(struct spu_context ctx)
216	{
217	return ctx->spu->local_store;
218	}
219
5110459f AB	220	static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val)
	221	{
	222	eieio();
	223	out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
	224	}
	225
	226	static void spu_hw_runcntl_stop(struct spu_context *ctx)
	227	{
	228	spin_lock_irq(&ctx->spu->register_lock);
	229	out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);
	230	while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)
	231	cpu_relax();
	232	spin_unlock_irq(&ctx->spu->register_lock);
	233	}
	234
a33a7d73 AB	235	static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode)
	236	{
	237	struct spu_problem *prob = ctx->spu->problem;
	238	int ret;
	239
	240	spin_lock_irq(&ctx->spu->register_lock);
	241	ret = -EAGAIN;
	242	if (in_be32(&prob->dma_querytype_RW))
	243	goto out;
	244	ret = 0;
	245	out_be32(&prob->dma_querymask_RW, mask);
	246	out_be32(&prob->dma_querytype_RW, mode);
	247	out:
	248	spin_unlock_irq(&ctx->spu->register_lock);
	249	return ret;
	250	}
	251
	252	static u32 spu_hw_read_mfc_tagstatus(struct spu_context * ctx)
	253	{
	254	return in_be32(&ctx->spu->problem->dma_tagstatus_R);
	255	}
	256
	257	static u32 spu_hw_get_mfc_free_elements(struct spu_context *ctx)
	258	{
	259	return in_be32(&ctx->spu->problem->dma_qstatus_R);
	260	}
	261
	262	static int spu_hw_send_mfc_command(struct spu_context *ctx,
	263	struct mfc_dma_command *cmd)
	264	{
	265	u32 status;
	266	struct spu_problem *prob = ctx->spu->problem;
	267
	268	spin_lock_irq(&ctx->spu->register_lock);
	269	out_be32(&prob->mfc_lsa_W, cmd->lsa);
	270	out_be64(&prob->mfc_ea_W, cmd->ea);
	271	out_be32(&prob->mfc_union_W.by32.mfc_size_tag32,
	272	cmd->size << 16 \| cmd->tag);
	273	out_be32(&prob->mfc_union_W.by32.mfc_class_cmd32,
	274	cmd->class << 16 \| cmd->cmd);
	275	status = in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
	276	spin_unlock_irq(&ctx->spu->register_lock);
	277
	278	switch (status & 0xffff) {
	279	case 0:
	280	return 0;
	281	case 2:
	282	return -EAGAIN;
	283	default:
	284	return -EINVAL;
	285	}
	286	}
	287
8b3d6663 AB	288	struct spu_context_ops spu_hw_ops = {
	289	.mbox_read = spu_hw_mbox_read,
	290	.mbox_stat_read = spu_hw_mbox_stat_read,
3a843d7c	291	.mbox_stat_poll = spu_hw_mbox_stat_poll,
8b3d6663 AB	292	.ibox_read = spu_hw_ibox_read,
	293	.wbox_write = spu_hw_wbox_write,
	294	.signal1_read = spu_hw_signal1_read,
	295	.signal1_write = spu_hw_signal1_write,
	296	.signal2_read = spu_hw_signal2_read,
	297	.signal2_write = spu_hw_signal2_write,
	298	.signal1_type_set = spu_hw_signal1_type_set,
	299	.signal1_type_get = spu_hw_signal1_type_get,
	300	.signal2_type_set = spu_hw_signal2_type_set,
	301	.signal2_type_get = spu_hw_signal2_type_get,
	302	.npc_read = spu_hw_npc_read,
	303	.npc_write = spu_hw_npc_write,
	304	.status_read = spu_hw_status_read,
	305	.get_ls = spu_hw_get_ls,
5110459f AB	306	.runcntl_write = spu_hw_runcntl_write,
5110459f AB	307	.runcntl_stop = spu_hw_runcntl_stop,
a33a7d73 AB	308	.set_mfc_query = spu_hw_set_mfc_query,
	309	.read_mfc_tagstatus = spu_hw_read_mfc_tagstatus,
	310	.get_mfc_free_elements = spu_hw_get_mfc_free_elements,
	311	.send_mfc_command = spu_hw_send_mfc_command,
8b3d6663	312	};